Hi Paul,
On 2019年10月21日 20:31, Paul Cercueil wrote:
Hi Zhou,
Le sam., oct. 19, 2019 at 01:50, Zhou Yanjie a
écrit :
Add support for the clocks provided by the CGU in the Ingenic X1000
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: Zhou Yanjie
---
drivers/clk
v1->v2:use BIT() macro instead left shift, add a call of
"ingenic_cgu_register_syscore_ops()", replace "CLK_OF_DECLARE"
with a "CLK_OF_DECLARE_DRIVER".
Add support for the clocks provided by the CGU in the Ingenic X1000
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: Zhou Yanjie
---
drivers/clk/ingenic/Kconfig | 10 ++
drivers/clk/ingenic/Makefile| 1 +
drivers/clk/ingenic/x1000-cgu.c | 256
Add the clock bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
include/dt-bindings/clock/x1000-cgu.h | 41 ++
2 files changed, 42 insertions(+)
create mode 100644 include/dt
1.Add the DMA bindings for the X1000 SoC from Ingenic.
2.Add support for probing the dma-jz4780 driver on the
X1000 SoC from Ingenic.
Add support for probing the dma-jz4780 driver on the X1000 Soc.
Signed-off-by: Zhou Yanjie
---
drivers/dma/dma-jz4780.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index 7fe9309..c7f1199 100644
--- a/drivers/dma/dma-jz4780.c
Add the DMA bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/dma/jz4780-dma.txt | 3 +-
include/dt-bindings/dma/x1000-dma.h| 40 ++
2 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644
Add support for probing the dma-jz4780 driver on the X1000 Soc.
Signed-off-by: Zhou Yanjie
---
drivers/dma/dma-jz4780.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index cafb1cc0..f809a6e 100644
--- a/drivers/dma/dma-jz4780.c
Add the dmaengine bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/dma/jz4780-dma.txt | 3 +-
include/dt-bindings/dma/x1000-dma.h| 40 ++
2 files changed, 42 insertions(+), 1 deletion(-)
create mode
Hi Vinod,
On 2019年10月23日 13:15, Vinod Koul wrote:
On 23-10-19, 11:05, Zhou Yanjie wrote:
1.Add the DMA bindings for the X1000 SoC from Ingenic.
2.Add support for probing the dma-jz4780 driver on the
X1000 SoC from Ingenic.
The subsystem in dmaengine and not dma
Please resend with correct
1.Add the dmaengine bindings for the X1000 SoC from Ingenic.
2.Add support for probing the dma-jz4780 driver on the
X1000 SoC from Ingenic.
v1->v2: drop macro definition rename, split patch, add support for x1000.
Add support for 8bit mode, now supports 1bit/4bit/8bit modes.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index ffdbfaa..69c4a8b
Add the MMC bindings for the JZ4760 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/jz4740.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/jz4740.txt
b/Documentation/devicetree/bindings
Add the MMC bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/mmc/jz4740.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/jz4740.txt
b/Documentation/devicetree/bindings
Add support for probing mmc driver on the JZ4760 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index 69c4a8b..f4c4890 100644
--- a/drivers/mmc
Add support for probing mmc driver on the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index f4c4890..44a04fe 100644
--- a
add support for low power mode of Ingenic's MMC/SD Controller.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index 44a04fe..4cbe7fb 1
From: Paul Cercueil
The same behaviour can be obtained by using the IRQCHIP_MASK_ON_SUSPEND
flag on the IRQ chip.
Signed-off-by: Paul Cercueil
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 24 +---
include/linux/irqchip/ingenic.h | 14 --
2
v5->v6: add my Signed-off-by for patches from Paul Cercueil.
From: Paul Cercueil
If we cannot create the IRQ domain, the driver should fail to probe
instead of succeeding with just a warning message.
Signed-off-by: Paul Cercueil
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 15 ++-
1 file changed, 10 insertions(+), 5
From: Paul Cercueil
Get the virq number from the IRQ domain instead of calculating it from
the hardcoded irq base.
Signed-off-by: Paul Cercueil
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers
From: Paul Cercueil
By creating the generic chips from the IRQ domain, we don't rely on the
JZ4740_IRQ_BASE macro. It also makes the code a bit cleaner.
Signed-off-by: Paul Cercueil
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 30 +-
1
are still unresponsive interrupts after processing the lowest
setted bit interrupt. If there are any, the processing will be
processed according to the bit in JZ_REG_INTC_PENDING, and the
interrupt dispatch function will be exited until all processing
is completed.
Signed-off-by: Zhou Yanjie
Hi Greg,
I'm sorry, maybe it was a problem when I git send-email,
causing the wrong patch to be sent to you. Just ignore
the email about the serial patch please.
Best regards!
On 2019年10月12日 15:35, Greg KH wrote:
On Sat, Oct 12, 2019 at 01:13:23PM +0800, Zhou Yanjie wrote:
Add suppor
Hi Uffe,
On 2019年10月18日 16:52, Ulf Hansson wrote:
On Sat, 12 Oct 2019 at 07:19, Zhou Yanjie wrote:
add support for low power mode of Ingenic's MMC/SD Controller.
Signed-off-by: Zhou Yanjie
I couldn't find a proper coverletter for the series, please provide
that next time as it re
1.Add the clock bindings for X1000 from Ingenic.
2.Add support for the clocks provided by the CGU in the
Ingenic X1000 SoC.
Add the clock bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
include/dt-bindings/clock/x1000-cgu.h | 41 ++
2 files changed, 42 insertions(+)
create mode 100644 include/dt
Add support for the clocks provided by the CGU in the Ingenic X1000
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: Zhou Yanjie
---
drivers/clk/ingenic/Kconfig | 10 ++
drivers/clk/ingenic/Makefile| 1 +
drivers/clk/ingenic/x1000-cgu.c | 253
v1->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
v2->v3: Add support for probing irq-ingenic driver on JZ4760 and X1500 Soc.
v3->v4: Combined with patches 5 and 7, combined with patches 4, 6 and 8.
For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b
Add the interrupt-controller bindings for the JZ4760/JZ4760B and
the X1000/X1000E and the X1500 Socs from Ingenic.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/interrupt-controller/ingenic,intc.txt| 5 +
1 file changed, 5 insertions(+)
diff --git
a/Documentation
The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 37
Add support for probing the irq-ingenic driver on the JZ4760/JZ4760B
and the X1000/X1000E and the X1500 Socs from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq
Hi Marc,
These patches has been combined in v4.
Thanks
On 2019年07月26日 21:36, Marc Zyngier wrote:
On Mon, 15 Jul 2019 13:09:50 +0100,
Zhou Yanjie wrote:
Add the interrupt-controller bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation
OK, thanks for your suggestions. I'll drop this patch.
On 2019年01月29日 04:48, Paul Cercueil wrote:
Hi,
Hello,
This seems like a useless renaming to me, can you elaborate a bit more?
I'd also like to have Paul and Lars-Peter comment.
According to the patchset, the RTC in the X1000 does not b
I would prefer to keep it. There are many other drivers that also use
this header file.
On 2019年01月29日 03:22, Joe Perches wrote:
On Fri, 2019-01-25 at 14:59 -0300, Paul Cercueil wrote:
On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie
wrote:
Warning is reported when checkpatch indicates that
Fix booting time warnings.
Dt-bindings doc about CPU node of Ingenic XBurst based SOCs.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/mips/ingenic/ingenic,cpu.txt| 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
diff
Current kernels complain when booting on CI20:
[0.329630] cacheinfo: Failed to find cpu0 device node
[0.335023] cacheinfo: Unable to detect cache hierarchy for CPU 0
Add the CPU node and the L2 cache node, then let each CPU point to it.
Signed-off-by: Zhou Yanjie
---
arch/mips/boot/dts
From: Zhou Yanjie
Add mmc2 for JZ4770 and JZ4780:
According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
part of the original code is missing. It is worth noting that JZ4770's
mmc2 supports 8bit mode while JZ4780's does not, so we added the
corresponding code for b
From: Zhou Yanjie
In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".
Signed-off-by: Zhou Yanjie
---
drivers/
From: Zhou Yanjie
Delete uart4 and i2c3/4 from JZ4770:
According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
remove it from the JZ4770 code and add a section corresponding the JZ4780.
Fix bugs in i2c0/1:
The pin number was wrong in the original code.
Fix bugs in uart2:
JZ4770
From: Zhou Yanjie
Warning is reported when checkpatch indicates that
"static const char * array" should be changed to
"static const char * const".
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 136 +-
1 file ch
From: Zhou Yanjie
According to the Schematic, the hardware of ci20 leads to uart3,
but not to uart2. Uart2 is miswritten in the original code.
Signed-off-by: Zhou Yanjie
---
arch/mips/boot/dts/ingenic/ci20.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch
According to the Schematic, the hardware of ci20 leads to uart3,
but not to uart2. Uart2 is miswritten in the original code.
Signed-off-by: Zhou Yanjie
---
arch/mips/boot/dts/ingenic/ci20.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic
Resend because previous mail is blocked by server.
In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".
Signed-off-by: Zhou Yanjie
---
drivers/
of
JZ4780 has been added.
Fix bugs in lcd:
Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit.
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 249 +-
1 file changed, 191 insertions(+), 58 deletions(-)
diff --git a/drivers/pinctrl/p
c-wait for JZ4770 and JZ4780:
Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the
original code is missing.
Add mac for JZ4770:
JZ4770 have a mac. But this part of the original code is missing.
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-inge
Warning is reported when checkpatch indicates that
"static const char * array" should be changed to
"static const char * const".
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 136 +-
1 file changed, 76 insertions(+), 6
Add support for Ingenic JZ4760, JZ4760B, X1000, X1000E and X1500.
Add the pinctrl bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic
Add support for probing the pinctrl-ingenic driver on the
JZ4760 Soc and the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 336 ++
1 file changed, 305 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl
Add the pinctrl bindings for the X1000 Soc and
the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
.../devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl
Add support for probing the pinctrl-ingenic driver on the
X1000 Soc and the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 307 --
1 file changed, 296 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl
Add the pinctrl bindings for the X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
b/Documentation/devicetree
Add support for probing the pinctrl-ingenic driver on the
X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 118 +-
1 file changed, 117 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c
b
The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 37
Add the interrupt-controller bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/interrupt
For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b
v1->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
v2->v3: Add support for probing irq-ingenic driver on JZ4760 and X1500 Soc.
Add support for probing the irq-ingenic driver on the JZ4760 Soc
and the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 8430f5a
Add support for probing the irq-ingenic driver on the X1000 Soc
and the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index e9e959c
Add the interrupt-controller bindings for the X1000 Soc and
the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/interrupt
Add the interrupt-controller bindings for the
X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ingenic
Add support for probing the irq-ingenic driver on the
X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/irqchip/irq-ingenic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index e8f7ae7..b72430c 100644
--- a
Hi Paul,
On 2019年08月01日 04:34, Paul Burton wrote:
Hi Zhou,
On Wed, Jul 31, 2019 at 12:39:03PM +0800, Zhou Yanjie wrote:
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
3.fix bugs when calculate bogoMips and loops_per_jiffy.
This should be split
v1->v2: Use "set_c0_config7(BIT(4))" to simplify code and add comment.
v2->v3: Split patch and use "MIPS_CONF7_BTB_LOOP_EN" to instead "BIT(4)".
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
Signed-off-by: Zhou Yanjie
---
arch/mips/mm/sc-mips.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
Enable BTB lookups for short loops to fix bugs when calculate
bogomips and loops_per_jiffy.
Signed-off-by: Zhou Yanjie
---
arch/mips/include/asm/mipsregs.h | 4
arch/mips/kernel/cpu-probe.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b
On 2019年08月02日 09:26, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 1 août 2019 à 8:16, Zhou Yanjie a écrit :
Enable BTB lookups for short loops to fix bugs when calculate
bogomips and loops_per_jiffy.
The commit description and the code comment below seem to say two
different things. Are we
v1->v2: Use "set_c0_config7(BIT(4))" to simplify code and add comment.
v2->v3: Split patch and use "MIPS_CONF7_BTB_LOOP_EN" to instead "BIT(4)".
v3->v4: Change the commit title.
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
Signed-off-by: Zhou Yanjie
---
arch/mips/mm/sc-mips.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
In order to further reduce power consumption, the XBurst core
by default attempts to avoid branch target buffer lookups by
detecting & special casing loops. This feature will cause
BogoMIPS and lpj calculate in error. Set cp0 config7 bit 4 to
disable this feature.
Signed-off-by: Zhou Ya
think chained irq is more generic way.
Look forward
to your and Marc's comments.
On 2019年07月30日 00:57, Paul Cercueil wrote:
Hi Marc,
Le lun. 29 juil. 2019 à 6:38, Marc Zyngier a
écrit :
[+ Zhou Yanjie]
Paul,
On 27/07/2019 20:17, Paul Cercueil wrote:
Get the virq number from the IRQ d
n the same way. So I
followed
the same method to add the declare of jz4760/x1000/x1500, this may be a
little
better.
On 2019年07月30日 01:25, Paul Cercueil wrote:
Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie a
écrit :
Add support for probing the irq-ingenic driver on the JZ4760/JZ4760B
and the
Hi Paul,
Thanks for your suggestion, and after receiving Marc's comments,
if this patch can be continued, I'll use for_each_set_bit() to simplify
code in v5.
On 2019年07月30日 01:19, Paul Cercueil wrote:
Hi Zhou,
Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie a
écrit :
The interrup
Add X1000 system type for cat /proc/cpuinfo to give out X1000.
Add X1000 system type for cat /proc/cpuinfo to give out X1000.
Signed-off-by: Zhou Yanjie
---
arch/mips/include/asm/bootinfo.h | 1 +
arch/mips/include/asm/cpu.h | 2 +-
arch/mips/jz4740/setup.c | 4
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/mips
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
3.fix bugs when calculate bogoMips and loops_per_jiffy.
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
3.fix bugs when calculate bogoMips and loops_per_jiffy.
Signed-off-by: Zhou Yanjie
---
arch/mips/kernel/cpu-probe.c | 7 ++-
arch/mips/mm/sc-mips.c | 18 +++---
2 files changed
Hi Paul,
On 2019年07月31日 02:02, Paul Cercueil wrote:
Hi Zhou,
Le mar. 30 juil. 2019 à 10:55, Zhou Yanjie a
écrit :
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
3.fix bugs when calculate bogoMips and loops_per_jiffy.
Signed-off-by: Zhou
v1->v2: Use "set_c0_config7(BIT(4))" to simplify code and add comment.
1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.
3.fix bugs when calculate bogoMips and loops_per_jiffy.
Signed-off-by: Zhou Yanjie
---
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/kernel/cpu-probe.c | 7 +++
arch/mips/mm/sc-mips.c
在 2020/5/27 上午3:29, Rob Herring 写道:
On Tue, May 19, 2020 at 10:35:21PM +0800, 周琰杰 (Zhou Yanjie) wrote:
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Signed-off
Hi Paul,
在 2020/5/27 上午3:10, Paul Cercueil 写道:
Hi Zhou,
Le mer. 27 mai 2020 à 1:07, 周琰杰 (Zhou Yanjie)
a écrit :
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller
Tested-by: Paul Boddie
Hi Stephen,
在 2020/5/27 下午4:12, Stephen Boyd 写道:
Quoting 周琰杰 (Zhou Yanjie) (2020-05-26 07:40:41)
Add the clock bindings for the X1830 Soc from Ingenic.
Signed-off-by: \u5468\u7430\u6770 (Zhou Yanjie)
Reviewed-by: Rob Herring
---
Notes:
v2->v3:
Adjust order from [3/5] in v2 to
multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2->v3:
Adjust order from [1/5] in v2 to [2/5]
It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.
Suggested-by: Paul Cercueil
Suggested-by: Paul Burton
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Adjust order from [5/5] in v2 to [
Add the clock bindings for the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v11:
New patch, split from [3/6] in v10.
include/dt-bindings/clock/x1830-cgu.h | 55 +++
1 file changed, 55 insertions(+)
create mode 100644 include/dt
Add support for the clocks provided by the CGU in the Ingenic X1830
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
1.Use two fields (pll_reg & bypass_reg) instead of the 2-values
array
00_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added.
Sign
LK_SSIMUX" when initializing the clocks.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU, and gates of CPU, PCLK
are also added.
3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v5:
New patch.
V
v10->v11:
Split [3/6] in v10 to [3/7] in v11 and [4/7] in v11.
周琰杰 (Zhou Yanjie) (7):
clk: Ingenic: Remove unnecessary spinlock when reading registers.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
dt-bindings: clock: Add documentation for X1830 bindings.
dt-bindi
Add documentation for the clock bindings of the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v11:
New patch, split from [3/6] in v10.
Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation
It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.
Suggested-by: Paul Cercueil
Suggested-by: Paul Burton
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Adjust order from [5/5] in v2 to [
00_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added.
Sign
v10->v11:
Split [3/6] in v10 to [3/7] in v11 and [4/7] in v11.
周琰杰 (Zhou Yanjie) (7):
clk: Ingenic: Remove unnecessary spinlock when reading registers.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
dt-bindings: clock: Add documentation for X1830 bindings.
dt-bindi
Add documentation for the clock bindings of the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Rob Herring
---
Notes:
v11:
New patch, split from [3/6] in v10.
Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff
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