Hi Paul,
On 2021/4/17 下午5:49, Paul Cercueil wrote:
Hi Zhou,
Le sam. 17 avril 2021 à 0:14, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3
Hi Paul,
On 2021/4/17 下午6:12, Paul Cercueil wrote:
Hi Zhou,
Le sam. 17 avril 2021 à 0:14, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3
schmitt and slew.
v5->v6:
1.Add the missing lcd-24bit group.
2.Add DMIC pins support for Ingenic SoCs.
3.Adjust and simplify the code.
周琰杰 (Zhou Yanjie) (12):
pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.
pinctrl: Ingenic: Add support for read the pin configuratio
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and
JZ4780.")
Cc:
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.")
Cc:
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Add Paul Cercueil's Reviewed-by.
e two interfaces supported by X1830 are respectively referred to as
"TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced
with "lcd-tft-xxx" to avoid confusion.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
1.Add DMIC pins support for the JZ4780 SoC.
2.Add DMIC pins support for the X1000 SoC.
3.Add DMIC pins support for the X1500 SoC.
4.Add DMIC pins support for the X1830 SoC.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v6:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 22
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Rob Herring
---
Notes:
v2:
New patch.
v2->v3:
No change.
v3->v4:
1.Add a descript
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition section.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2-&g
register pairs which have
2 bits for each GPIO pin.
Tested-by: H. Nikolaus Schaller # on Letux400
Co-developed-by: Paul Boddie
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v3:
New patch.
v3->v4:
1.Use "lcd-special" and "lcd-generic"
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v3:
New patch.
v3->v4:
1.Split LCD pins into several groups.
2.Drop "lcd
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v3:
New patch.
v3->v4:
1.Split LCD pins into several groups.
2.Drop "lcd
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v3:
New patch.
v3->v4:
1.Split LCD pins into several groups.
2.Drop "lcd
Hi
On 2021/4/19 下午12:56, Huang Pei wrote:
On Sat, Apr 17, 2021 at 12:45:59AM +0800, Zhou Yanjie wrote:
On 2021/4/16 下午5:20, 黄沛 wrote:
Is there any log about the panic?
Yes, below is the log:
[ 195.436017] CPU 0 Unable to handle kernel paging request at virtual
address 77eb8000, epc
v1->v2:
1.Split [1/3] in v1 to [1/6] [2/6] [3/6] [4/6] in v2.
2.Fix the uninitialized warning.
v2->v3:
Split [6/6] in v2 to [6/10] [7/10] [8/10] [9/10] [10/10] in v3.
周琰杰 (Zhou Yanjie) (10):
pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.
pinctrl: Ingenic: Add suppo
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and
JZ4780.")
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
v2->v3:
Add fixes tag.
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.")
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
v2->v3:
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition section.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Add Paul Cercueil&
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 137 ++
1 file changed, 137 insertions(+)
diff --git a/drivers/pinctrl
register pairs which have
2 bits for each GPIO pin.
Tested-by: H. Nikolaus Schaller # on Letux400
Co-developed-by: Paul Boddie
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
v2->v3:
No change.
.../bindings/pinctrl/ingenic,pinctrl.yaml |
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 132 ++
1 file changed, 132 insertions(+)
diff --git a/drivers/pinctrl
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Add Paul Cercueil's Reviewed-by.
drivers/pinctrl/pinctrl-i
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 502 +-
1 file changed, 493 insertions(+), 9 deletions(-)
diff --git a
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v3:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 259 ++
1 file changed, 259 insertions(+)
diff --git a/drivers/pinctrl
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Add the CGU code and the compatible string to the TCU driver to support
the JZ4760 SoC.
Signed-off-by: Paul Cercueil
---
drivers/clk/ingenic/Kconfig| 10 +
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/jz
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and
JZ4780.")
Cc:
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
ointless.
4.Improve the structure of some functions.
5.Adjust function names to avoid confusion.
6.Use "lcd-special" and "lcd-generic" instead "lcd-xxbit-tft".
7.Replace "lcd-rgb-xxx" with "lcd-tft-xxx" to avoid confusion.
周琰杰 (Zhou Yanjie) (
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.")
Cc:
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
e two interfaces supported by X1830 are respectively referred to as
"TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced
with "lcd-tft-xxx" to avoid confusion.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v4:
New patch.
drivers/pi
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2->v3:
Add Paul Cercueil's Reviewed-by.
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition section.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
Reviewed-by: Paul Cercueil
---
Notes:
v2:
New patch.
v2-&g
Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft"
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Rob Herring
---
Notes:
v2:
New patch.
v2->v3:
No change.
v3->v4:
1.Add a descript
register pairs which have
2 bits for each GPIO pin.
Tested-by: H. Nikolaus Schaller # on Letux400
Co-developed-by: Paul Boddie
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch
Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointle
Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointle
Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Andy Shevchenko
---
Notes:
v3:
New patch.
v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is poi
Hi Paul,
On 2020/12/3 上午6:18, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie)
a écrit :
Add CIM, AIC, DMIC clocks for the X1000 SoC, and CIM, AIC, DMIC, I2S
clocks for the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/clk/ingenic/x1000
Hi Paul,
On 2020/12/3 上午6:09, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie)
a écrit :
1.Fill unused bits in parents in jz4780-cgu.c, x1000-cgu.c,
and x1830-cgu.c, these bits should be filled with -1.
2.Reformat code, add missing blank lines, remove
u.c, these bits should be filled with -1.
4.Reformat code, add missing blank lines, remove unnecessary tabs,
and align code.
周琰杰 (Zhou Yanjie) (4):
clk: JZ4780: Add function for disable the second core.
dt-bindings: clock: Add missing clocks for Ingenic SoCs.
clk: Ingenic: Add missing clocks f
Add CIM, AIC, DMIC clocks bindings for the X1000 SoC, and CIM, AIC,
DMIC, I2S clocks for the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
include/dt-bindings/clock/x1000-cgu.h | 3 +++
include/dt-bindings/clock/x1830-cgu.h | 4
2 files changed, 7 insertions(+)
diff --git a
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/clk/ingenic/jz4780-cgu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/c
Add CIM, AIC, DMIC clocks for the X1000 SoC, and CIM, AIC, DMIC, I2S
clocks for the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/clk/ingenic/x1000-cgu.c | 19
drivers/clk/ingenic/x1830-cgu.c | 189 +++-
2 files changed, 207
1.Fill unused bits in parents in jz4780-cgu.c, x1000-cgu.c,
and x1830-cgu.c, these bits should be filled with -1.
2.Reformat code, add missing blank lines, remove unnecessary
tabs, and align code.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/clk/ingenic/jz4780-cgu.c | 12 +++---
drivers/clk
on JZ4780, X1000, and X1830.
Tested-by: 周琰杰 (Zhou Yanjie)
Thanks and best regards!
diff --git a/drivers/clocksource/ingenic-timer.c
b/drivers/clocksource/ingenic-timer.c
index 58fd9189fab7..905fd6b163a8 100644
--- a/drivers/clocksource/ingenic-timer.c
+++ b/drivers/clocksource/ingenic-timer.c
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
drivers/clk/inge
X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.
Signed-off-by: 周琰杰 (Zhou
or Ingenic X1830")
Signed-off-by: Christophe JAILLET
---
drivers/char/hw_random/ingenic-trng.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Thanks for fixing it, and apologize for my carelessness.
Tested-by: 周琰杰 (Zhou Yanjie)
diff --git a/drivers/char/hw_random/
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 0fce2e02a29ca5420472f03d3f2858eedded3fe7
Gitweb:
https://git.kernel.org/tip/0fce2e02a29ca5420472f03d3f2858eedded3fe7
Author:周琰杰 (Zhou Yanjie)
AuthorDate:Mon, 26 Oct 2020 23:58:42 +08:00
Hi Paul,
On 2021/3/12 下午9:05, Paul Cercueil wrote:
Hi,
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Signed-off-by: 周琰杰 (Zhou Yanjie)
No Fixes: tag?
And if the bug wasn't introduc
Hi Paul,
On 2021/3/12 下午9:31, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Signed-off-by: 周琰杰 (Zhou Yanjie)
This is a fix, so
Hi,
On 2021/3/12 下午9:42, Paul Cercueil wrote:
Hi Zhou,
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
a écrit :
Add support for probing the pinctrl-ingenic driver on the JZ4730 SoC,
the JZ4750 SoC, the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from
Ingenic.
The driver of JZ4730 is
Hi Andy,
On 2021/3/10 下午10:03, Andy Shevchenko wrote:
On Tue, Mar 9, 2021 at 6:42 PM 周琰杰 (Zhou Yanjie)
wrote:
1.Add tabs before values to align the code in the macro definition section.
2.Fix bugs related to the MAC of JZ4770, add missing pins to the MII group.
3.Adjust the sequence of X1830
Hi Paul,
On 2021/3/10 下午10:19, Paul Cercueil wrote:
Le mer. 10 mars 2021 à 16:03, Andy Shevchenko
a écrit :
On Tue, Mar 9, 2021 at 6:42 PM 周琰杰 (Zhou Yanjie)
wrote:
1.Add tabs before values to align the code in the macro definition
section.
2.Fix bugs related to the MAC of JZ4770, add
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Hi,
Here are a set of patches to add support for the Ingenic JZ4760(B) SoCs.
One thing to note is that the ingenic,jz4760-tcu is undocumented for now,
as I will update the TCU documentation in a different patchset.
Zhou: the CGU code now supp
| 3 +++
2 files changed, 30 insertions(+), 13 deletions(-)
Tested-by: 周琰杰 (Zhou Yanjie) # on CU1000-neo/X1000E
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 58f7ab5cf0fe..266c7595d330 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic
v1->v2:
1.Split [1/3] in v1 to [1/6] [2/6] [3/6] [4/6] in v2.
2.Fix the uninitialized warning.
周琰杰 (Zhou Yanjie) (6):
pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.
pinctrl: Ingenic: Add support for read the pin configuration of X1830.
pinctrl: Ingenic: Adjust the seque
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pi
1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition section.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
drivers/pinctrl/pinctrl-inge
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
No change.
.../bindings/pinctrl/ingenic,pinctrl.yaml | 23 ++
1 file changed,
add code to handle the jz4730 specific register offsets and some
register pairs have 2 bits for each GPIO pin.
Tested-by: H. Nikolaus Schaller # on Letux400/JZ4730
Signed-off-by: Paul Boddie # for JZ4730
Signed-off-by: H. Nikolaus Schaller # for JZ4730
Signed-off-by: 周琰杰 (Zhou Yanjie
Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v2:
New patch.
drivers/pinctrl/pinctrl-ingenic.c | 76 +--
1 file changed, 57 inserti
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Hi,
Here are a set of patches to add support for the Ingenic JZ4760(B) SoCs.
One thing to note is that the ingenic,jz4760-tcu is undocumented for now,
as I will update the TCU documentation in a different patchset.
Zhou: the CGU code now supp
Hi Paul,
On 2021/3/7 下午10:17, Paul Cercueil wrote:
Hi,
Here are a set of patches to add support for the Ingenic JZ4760(B) SoCs.
One thing to note is that the ingenic,jz4760-tcu is undocumented for now,
as I will update the TCU documentation in a different patchset.
Zhou: the CGU code now supp
", so that it can read the configuration
of X1830 SoC correctly.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
drivers/pinctrl/pinctrl-ingenic.c | 161 +++---
1 file changed, 100 insertions(+), 61 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c
b/
SoC, the JZ4775 SoC and the X2000 SoC from
Ingenic.
周琰杰 (Zhou Yanjie) (3):
pinctrl: Ingenic: Fix bug and reformat the code.
dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
pinctrl: Ingenic: Add support for new Ingenic SoCs.
.../bindings/pinctrl/ingenic,pinctrl.yaml |
Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
.../bindings/pinctrl/ingenic,pinctrl.yaml | 23 ++
1 file changed, 19 insertions(+), 4 deletions(-)
diff
add code to handle the jz4730 specific register offsets and some
register pairs have 2 bits for each GPIO pin.
Tested-by: H. Nikolaus Schaller # on Letux400/JZ4730
Signed-off-by: Paul Boddie # for JZ4730
Signed-off-by: H. Nikolaus Schaller # for JZ4730
Signed-off-by: 周琰杰 (Zhou Yanjie
v1->v2:
1.Add Paul Cercueil's Reviewed-by for [1/5] & [2/5],
add Rob Herring's Acked-by for [2/5].
2.Add MACPHY and I2S for X1000, add MACPHY for X1830,
and fix bugs in MAC clock.
3.Clean up code, remove unnecessary -1 and commas and
tabs from all the -cgu.c files.
周琰杰
Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC
and the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Acked-by: Rob Herring
---
Notes:
v1->v2:
1.Add MACPHY and I2S for X1000, and add MACPHY for X1830.
2.Add Paul Cercuei
.c files.
2.Reformat code, add missing blank lines, remove unnecessary
commas and tabs, and align code.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Remove unnecessary -1 and commas.
drivers/clk/ingenic/jz4725b-cgu.c | 50 +++---
drivers/clk/inge
Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add I2S clock for X1000.
drivers/clk/ingenic/x1000-cgu.c | 187 +++
drivers/clk/ingenic/x1830-cgu.c |
X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.
Signed-off-by: 周琰杰 (Zhou
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
drivers/clk/ingenic/jz4780-cgu.c | 21 +++
->v3:
Correct the comment in x1000-cgu.c, change it from
"Custom (SoC-specific) OTG PHY" to "Custom (SoC-specific)",
since there is more than just the "OTG PHY" clock.
周琰杰 (Zhou Yanjie) (5):
clk: JZ4780: Add function for disable the second core.
dt-bindings:
Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add I2S clock for X1000.
v2->v3:
Correct the comment in x1000-cgu.c, change it from
"Custom (SoC-specific) OTG PHY"
Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC
and the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Acked-by: Rob Herring
---
Notes:
v1->v2:
1.Add MACPHY and I2S for X1000, and add MACPHY for X1830.
2.Add Paul Cercuei
.c files.
2.Reformat code, add missing blank lines, remove unnecessary
commas and tabs, and align code.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Remove unnecessary -1 and commas.
v2->v3:
No change.
drivers/clk/ingenic/jz4725b-cgu.c | 50 +++---
I just noticed that I mistakenly wrote a capital 'W' in the original
version.
with that fixed:
Reviewed-by: 周琰杰 (Zhou Yanjie)
BTW: Are you planning to add support for JZ4760 recently? I am currently
writing the CGU driver for JZ4775 and X2000. If you plan to add support
for
Hi Paul,
On 2020/12/14 上午3:57, Paul Cercueil wrote:
Hi Zhou,
Le lun. 14 déc. 2020 à 3:12, Zhou Yanjie a
écrit :
Hi Paul,
On 2020/12/12 上午8:03, Paul Cercueil wrote:
The JZ4760 has the HPTLB as well, but has a XBurst CPU with a D0 CPUID.
Disable the HPTLB for all XBurst CPUs with a D0
Hi PrasannaKumar
I am also trying to add a series of Ingenic's processors.
I tested your code with the X1000 development board and
it will get stuck in "Run /linuxrc as init process."
As you speculate, last year the sold more than 500Ks of
X1000/X1000E, and customers have big companies like
Hone
Hi PrasannaKumar
I am also trying to add a series of Ingenic's processors.
I tested your code with the X1000 development board and
it will get stuck in "Run /linuxrc as init process."
As you speculate, last year the sold more than 500Ks of
X1000/X1000E, and customers have big companies like
Hone
1.adjust the macro definition name to match the corresponding
register name in the datasheet.
2.add support for 8bit mode, now supports 1bit/4bit/8bit modes.
3.add support for probing mmc driver on the JZ4760 Soc from Ingenic.
4.add support for Low Power Mode of Ingenic's MMC/SD Controller.
Adjust the macro definition name to match the corresponding
register name in the datasheet.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host
Add support for 8bit mode, now supports 1bit/4bit/8bit modes.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
index 1b1fcb7..d6811a7
1.add support for probing mmc driver on the JZ4760 Soc from Ingenic.
2.add support for Low Power Mode of Ingenic's MMC/SD Controller.
Signed-off-by: Zhou Yanjie
---
drivers/mmc/host/jz4740_mmc.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/mmc/host/jz4740_
Add the MMC bindings for the JZ4760 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/mmc/jz4740.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/jz4740.txt
b/Documentation/devicetree/bindings/mmc/jz4740.txt
index
Hi Ezequiel,
On 2019年09月13日 23:32, Ezequiel Garcia wrote:
Hi Zhou,
Thanks for your interest in this driver, I'm glad
so see it's more used.
On Thu, 2019-09-05 at 15:38 +0800, Zhou Yanjie wrote:
Adjust the macro definition name to match the corresponding
register name in the datashe
From: Paul Cercueil
The same behaviour can be obtained by using the IRQCHIP_MASK_ON_SUSPEND
flag on the IRQ chip.
Signed-off-by: Paul Cercueil
---
drivers/irqchip/irq-ingenic.c | 24 +---
include/linux/irqchip/ingenic.h | 14 --
2 files changed, 1 insertion(+)
Rebase on top of Paul Cercueil's patches and drop unneeded changes as
Paul Cercueil's advice.
From: Paul Cercueil
By creating the generic chips from the IRQ domain, we don't rely on the
JZ4740_IRQ_BASE macro. It also makes the code a bit cleaner.
Signed-off-by: Paul Cercueil
---
drivers/irqchip/irq-ingenic.c | 30 +-
1 file changed, 17 insertions(+), 13 dele
From: Paul Cercueil
If we cannot create the IRQ domain, the driver should fail to probe
instead of succeeding with just a warning message.
Signed-off-by: Paul Cercueil
---
drivers/irqchip/irq-ingenic.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers
From: Paul Cercueil
Get the virq number from the IRQ domain instead of calculating it from
the hardcoded irq base.
Signed-off-by: Paul Cercueil
---
drivers/irqchip/irq-ingenic.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/ir
are still unresponsive interrupts after processing the lowest
setted bit interrupt. If there are any, the processing will be
processed according to the bit in JZ_REG_INTC_PENDING, and the
interrupt dispatch function will be exited until all processing
is completed.
Signed-off-by: Zhou Yanjie
Hi Uffe,
On 2019年10月03日 18:00, Ulf Hansson wrote:
On Thu, 5 Sep 2019 at 09:40, Zhou Yanjie wrote:
1.add support for probing mmc driver on the JZ4760 Soc from Ingenic.
2.add support for Low Power Mode of Ingenic's MMC/SD Controller.
Normally we try to make "one" change per patc
Hi Pual,
On 2019年10月06日 08:13, Paul Cercueil wrote:
Hi Zhou,
Le mer., oct. 2, 2019 at 19:25, Zhou Yanjie a
écrit :
From: Paul Cercueil
The same behaviour can be obtained by using the IRQCHIP_MASK_ON_SUSPEND
flag on the IRQ chip.
Signed-off-by: Paul Cercueil
If you sumbit a patchset
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