pwm driver add MT2712/MT7622 support, fix clock control issue.
dtsi file will be upload latter, after the clock define is ready.
Zhi Mao (4):
pwm: kconfig: modify mediatek information
pwm: mediatek: fix clk issue
pwm: bindings: add MT2712/MT7622 information
pwm: mediatek: add MT2712
add MT2712/MT7622 pwm information
Signed-off-by: Zhi Mao
---
.../devicetree/bindings/pwm/pwm-mediatek.txt |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
b/Documentation/devicetree/bindings/pwm/pwm
support multiple chip(MT2712, MT7622, MT7623)
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 63 +++-
1 file changed, 51 insertions(+), 12 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index c803ff6..d520356
modify mediatek information
Signed-off-by: Zhi Mao
---
drivers/pwm/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 313c107..45cdf2a 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -300,7 +300,7
clock selection
- in original code, the pwm output frequency is not correct
when set bit<3>=1 to PWMCON register.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 69 +++-
1 file changed, 43 insertions(+), 26 deletions(-)
diff --git a/drive
On Wed, 2017-06-21 at 20:07 +0800, John Crispin wrote:
> Hi
>
> comments inline
>
>
> > +static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device
> > *pwm)
> > +{
> > + ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> > + if (ret < 0) {
> > + clk_dis
Add support to MT2712 and MT7622.
Due to register offset address of pwm7 for MT2712 is not fixed 0x40,
add mtk_pwm_reg_offset array for pwm register offset.
Add NULL pointer checking for "data",
and remove "struct mtk_pwm_platform_data" member from "mtk_pwm_chip&q
Hi Claudiu,
Thanks for your comments.
I updated this file, according to your suggestions.
Please have a review.
Regards
Zhi
On Tue, 2017-10-24 at 16:25 +0300, m18063 wrote:
> Hi Zhi,
>
> Please see my answer below.
>
> On 23.10.2017 14:13, Zhi Mao wrote:
> > Hi Claudiu
Add support to MT2712 and MT7622.
Due to register offset address of pwm7 for MT2712 is not fixed 0x40,
add mtk_pwm_reg_offset array for pwm register offset.
Reviewed-by: Claudiu Beznea
Reviewed-by: Matthias Brugger
Signed-off-by: Zhi Mao
---
changee in v7:
- adjust the commit message
Changes
Hi Thierry,
Just have a ping for this patch.
Regards
Zhi
On Wed, 2017-10-25 at 18:11 +0800, Zhi Mao wrote:
> Add support to MT2712 and MT7622.
> Due to register offset address of pwm7 for MT2712 is not fixed 0x40,
> add mtk_pwm_reg_offset array for pwm register offset.
>
&
On Mon, 2017-06-26 at 11:43 +0300, m18063 wrote:
>
> On 23.06.2017 08:08, Zhi Mao wrote:
> > Replace "7" with "PWM_CLK_DIV_MAX" in function:mtk_pwm_config()
> > to improve the code readablity.
> >
> > Signed-off-by: Zhi Mao
> > ---
&
change in v3:
1. add pwm clk disable in function:mtk_pwm_config()
for error parameter checking case
Zhi Mao (6):
pwm: kconfig: modify mediatek information
pwm: mediatek: fix pwm source clock selection
pwm: mediatek: fix clock control issue
pwm: bindings: add MT2712/MT7622 information
1. Replace "7" with "PWM_CLK_DIV_MAX" in function:mtk_pwm_config()
to improve the code readablity.
2. add pwm clk disable in function:mtk_pwm_config()
for error parameter checking case.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c |7 ++-
1 file changed
In original code, the pwm output frequency is not correct
when set bit<3>=1 to PWMCON register.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5
1. support multiple chip(MT2712, MT7622, MT7623)
2. add mtk_pwm_com_reg for match the registers of MT2712 pwm8
the register offset address of pwm8 for MT2712 is not fixed 0x40
and they are not the same as pwm0~6.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 55
add MT2712/MT7622 pwm information
Acked-by: Rob Herring
Signed-off-by: Zhi Mao
---
.../devicetree/bindings/pwm/pwm-mediatek.txt |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
b/Documentation/devicetree
modify mediatek information
Signed-off-by: Zhi Mao
---
drivers/pwm/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 313c107..45cdf2a 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -300,7 +300,7
e" in function:mtk_pwm_remove(),
as framework should disable all the pwms, before remove them.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 69 ++--
1 file changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drive
On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
>
> On 06/30/2017 08:05 AM, Zhi Mao wrote:
> > In original code, the pwm output frequency is not correct
> > when set bit<3>=1 to PWMCON register.
> >
> > Signed-off-by: Zhi Mao
> > ---
> >
On Thu, 2017-07-06 at 14:16 +0800, Zhi Mao wrote:
> On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
> >
> > On 06/30/2017 08:05 AM, Zhi Mao wrote:
> > > In original code, the pwm output frequency is not correct
> > > when set bit<3>=1 to PWMCON re
Hi John, Matthais & PWM Maintainers
Just a Gentle ping on this issue :)
Is there anything should be modified?
Regards,
Zhi
On Fri, 2017-06-30 at 14:05 +0800, Zhi Mao wrote:
> change in v3:
> 1. add pwm clk disable in function:mtk_pwm_config()
>for error parameter checking case
Hi Thierry,
Thanks for your review code.
I will modify the code as you comment in the next release.
Regards
Zhi
On Mon, 2017-08-21 at 10:05 +0200, Thierry Reding wrote:
> On Fri, Jun 30, 2017 at 02:05:21PM +0800, Zhi Mao wrote:
> > 1. support multiple chip(MT2712, MT7622, MT7623)
&
change in v4:
modify some coding style and naming of variable to make code readable.
Zhi Mao (1):
pwm: mediatek: add MT2712/MT7622 support
drivers/pwm/pwm-mediatek.c | 51
1 file changed, 42 insertions(+), 9 deletions(-)
Add support to MT2712 and MT7622.
Due to register offset address of pwm7 for MT2712 is not fixed 0x40,
add mtk_pwm_reg_offset array for pwm register offset.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 51
1 file changed, 42 insertions
Replace "7" with "PWM_CLK_DIV_MAX" in function:mtk_pwm_config()
to improve the code readablity.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-medi
1. support multiple chip(MT2712, MT7622, MT7623)
2. add mtk_pwm_com_reg for match the registers of MT2712 pwm8
the register offset address of pwm8 for MT2712 is not fixed 0x40
and they are not the same as pwm0~6.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 55
In original code, the pwm output frequency is not correct
when set bit<3>=1 to PWMCON register.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5
change in v2:
1. add error check for enable colock control flow
2. use "goto err_clk(main/top)" coding style, for preparing clk error case
3. remove comments inline /*===*/
4. move "PWM_CLK_DIV_MAX" modification to its own patch
5. move pwm source clock selection to its o
e" in function:mtk_pwm_remove(),
as framework should disable all the pwms, before remove them.
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-mediatek.c | 69 ++--
1 file changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drive
modify mediatek information
Signed-off-by: Zhi Mao
---
drivers/pwm/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 313c107..45cdf2a 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -300,7 +300,7
add MT2712/MT7622 pwm information
Signed-off-by: Zhi Mao
---
.../devicetree/bindings/pwm/pwm-mediatek.txt |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
b/Documentation/devicetree/bindings/pwm/pwm
Hi Thierry,
Just a gentle ping on this issue.
Would you please have a review to this patch?
Regards,
Zhi
On Tue, 2017-08-22 at 10:09 +0800, Zhi Mao wrote:
> Add support to MT2712 and MT7622.
> Due to register offset address of pwm7 for MT2712 is not fixed 0x40,
> add mtk_pwm_reg_off
Thanks John's reply.
Hi Thierry & Matthais,
What's your opinion?
On Wed, 2017-08-02 at 16:42 +0800, John Crispin wrote:
>
> On 02/08/17 09:19, Zhi Mao wrote:
> > Hi John, Matthais & Thierry,
> >> Just a gentle ping on this issue again.
> >> Do
Hi John, Matthais & Thierry,
>
> Just a gentle ping on this issue again.
> Do you have any update?
>
> Regards,
> Zhi
On Mon, 2017-07-17 at 11:16 +0800, Zhi Mao wrote:
> Hi John, Matthais & PWM Maintainers
>
> Just a Gentle ping on this issue :)
>
Hi Thierry,
Just have a ping on this issue.
Regards,
Zhi
On Wed, 2017-09-20 at 16:48 +0800, Zhi Mao wrote:
> Hi Thierry,
>
> Just a gentle ping on this issue.
> Would you please have a review to this patch?
>
> Regards,
> Zhi
>
>
> On Tue, 2017-08-22 at 10:09
Hi Claudiu
please check the comments as below.
Regards
Zhi
On Mon, 2017-10-23 at 11:22 +0300, m18063 wrote:
> Hi Zhi,
>
> I have few comments regarding your patch. Please see them below.
>
> Thanks,
> Claudiu
>
> On 22.08.2017 05:09, Zhi Mao wrote:
> > Ad
Add support to MT2712 and MT7622.
Due to register offset address of pwm7 for MT2712 is not fixed 0x40,
add mtk_pwm_reg_offset array for pwm register offset.
Add NULL pointer checking for "pc->data".
Signed-off-by: Zhi Mao
---
drivers/pwm/pwm-medi
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