Hi Rob,
Thanks a lot for the ack!
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: 2017年11月2日 8:14
> To: Z.q. Hou
> Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; linux-...@vge
Hi Cyrille,
> -Original Message-
> From: Cyrille Pitchen [mailto:cyrille.pitc...@wedev4u.fr]
> Sent: 2017年10月31日 8:43
> To: Mark Brown ; Yuan Yao ; Z.q.
> Hou ; Rob Herring ; Shawn Guo
> ; Philipp Puschmann
> Cc: linux-arm-ker...@lists.infradead.org; Linux-Next M
Hi Lorenzo,
Thanks a lot for your comments!
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: 2018年11月22日 19:17
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; ji
Hi Lorenzo,
Thanks a lot for your comments!
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: 2018年11月22日 19:28
> To: Z.q. Hou
> Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-...@vger.k
From: Hou Zhiqiang
This patch set is aim to refactor the Mobiveil driver and add
PCIe support for NXP Layerscape series SoCs integrated Mobiveil's
PCIe Gen4 controller.
Hou Zhiqiang (25):
PCI: mobiveil: uniform the register accessors
PCI: mobiveil: format the code without function change
P
From: Hou Zhiqiang
It's confused that R/W some registers by csr_readl()/csr_writel(),
while others by read_paged_register()/write_paged_register().
Actually the low 3KB of 4KB PCIe configure space can be accessed
directly and high 1KB is paging area. So this patch uniformed the
register accessors
From: Hou Zhiqiang
Outbound window routine:
- Removed unused var definition and register read operations.
- Added the upper 32-bit cpu address setup of the window.
- Instead of blindly write, only change the fields specified.
- Masked the lower bits of window size in case override the
cont
From: Hou Zhiqiang
The inbound windows have different register set with outbound windows.
This patch change the MEM inbound window to the first one.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
From: Hou Zhiqiang
Fix up the Class Code to PCI bridge, do not change the Revision ID.
And move the fixup to mobiveil_host_init function.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
IP driver")
Signed-off-by: Hou Zhiqiang
---
V2:
- Added fixes entry.
drivers/pci/contro
From: Hou Zhiqiang
As it won't delete any node in this iteration, replaced
the function resource_list_for_each_entry_safe() with
the resource_list_for_each_entry().
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 4 ++--
1 file changed, 2 insertions(+
From: Hou Zhiqiang
It should get PCI base address from the DT node property 'ranges'
to setup MEM/IO outbound windows instead of always zero.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
IP driver")
Signed-off-by: Hou Zhiqiang
---
V2:
- Added fixes entry.
drivers/pci/co
From: Hou Zhiqiang
Just format the code without functionality change.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 261 +
1 file changed, 137 insertions(+), 124 deletions(-)
diff --git a/drivers/pci/controller/pcie-mobiveil
From: Hou Zhiqiang
In the loop block, there is not code change the loop key,
this patch updated the loop key by re-read the INTx status
register.
This patch also change to clear the handled INTx status.
Note: Need MV to test this fix.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
From: Hou Zhiqiang
As the .map_bus() use the WIN_NUM_0 for CFG transactions,
it's better passing WIN_NUM_0 explicitly when initialize
the CFG outbound window.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 5 ++---
1 file changed, 2 insertions(+), 3
From: Hou Zhiqiang
Host initial sequence does not depend on PCIe link up, so move it
to the place just before the enumeration.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --
From: Hou Zhiqiang
The current code does not support multiple MSIs, so remove
the corresponding flag from the msi_domain_info structure.
Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
Signed-off-by: Hou Zhiqiang
---
V2:
- Added fixes entry.
drivers/pci/controller/pcie-mobiveil.c | 2
From: Hou Zhiqiang
This patch corrected the returned error number by convention,
and removed a unnecessary error check.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/p
From: Hou Zhiqiang
Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some
platforms.
Signed-off-by: Hou Zhiqiang
Acked-by: Subrahmanya Lingappa
Acked-by: Rob Herring
---
V2:
- no change
Documentation/devicetree/bin
From: Hou Zhiqiang
Sometimes there is not a PCIe Endpoint in the PCIe slot, so do
not exit when the PCIe link is not up. And degrade the print
level of link up info.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 1 -
drivers/pci/contro
From: Hou Zhiqiang
As the Mobiveil PCIe controller support RC&EP DAUL mode, and to
make platforms which integrated the Mobiveil PCIe IP more easy
to add their drivers, this patch moved the Mobiveil driver to
a new directory 'drivers/pci/controller/mobiveil' and refactored
it according to the abst
From: Hou Zhiqiang
The reset value is all zero, so set a workable value for Primary,
Secondary and Subordinate bus numbers.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/
From: Hou Zhiqiang
Move irq_set_chained_handler_and_data() out of DT parse function.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
drivers/pci/controller/pcie-mobiveil.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-mobiveil.c
b/driver
From: Hou Zhiqiang
Avoid to issue CFG transactions to link partner when the PCIe
link is not up. And allow CFG transactions to all functions of
Endpoint implemented multiple functions.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
Bridge IP driver")
Signed-off-by: Hou Zhiqiang
---
From: Hou Zhiqiang
Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
.../controller/mobiveil/pcie-mobiveil-host.c | 7 +++
.../pci/controller/mobiveil/
From: Hou Zhiqiang
Make the mobiveil_host_init function can be used to re-init
host controller's PAB and GPEX CSR register block, as NXP
integrated Mobiveil IP has to reset and then re-init the PAB
and GPEX CSR registers upon Hot-reset.
Signed-off-by: Hou Zhiqiang
---
V2:
- Reset the statistic
From: Hou Zhiqiang
As there are some Byte and Half-Work width registers in PCIe
configuration space, add Byte and Half-Word width register
accessors.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
.../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++
1 file changed, 20 ins
From: Hou Zhiqiang
Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
Signed-off-by: Hou Zhiqiang
---
V2:
- Change to use the layerscape-pci.txt for PCIe Gen4 controller
dt-bindings
.../bindings/pci/layerscape-pci.txt | 57 +++
MAINTAINERS
From: Hou Zhiqiang
This PCIe controller is based on the Mobiveil GPEX IP, which is
compatible with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang
---
V2:
- Changed the name of functions and data structures in this driver.
- Moved the reset operations to bottle
From: Hou Zhiqiang
Enable the PCIe Gen4 controller driver for Layerscape SoCs.
Signed-off-by: Hou Zhiqiang
---
V2:
- New patch
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ad92daeac585..6b43
From: Hou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang
---
V2:
- Change the default status of PCIe DT nodes to disabled.
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/
Hi Gustavo,
Thanks a lot for your testing and ACK!
Regards,
Zhiqiang
> -Original Message-
> From: Gustavo Pimentel
> Sent: 2018年11月22日 1:37
> To: Z.q. Hou ; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; bhelg...@google.com;
> lorenzo.pieral...@arm.com; ji
Hi Subrahmanya,
Thanks a lot for your ACK!
Regards,
Zhiqiang
> -Original Message-
> From: Subrahmanya Lingappa
> Sent: 2018年11月14日 17:33
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kern
Hi Leo,
> -Original Message-
> From: Leo Li
> Sent: 2018年11月15日 2:52
> To: Z.q. Hou ; linux-...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; bhelg...@google.com; robh...@kernel.org;
> mark.rutl..
Hi Subrahmanya,
As NXP does not integrate Mobiveil's INTx and MSI interrupt controller, I am
unable to test this fix.
Can you help to test this fix?
Thanks,
Zhiqiang
> -Original Message-
> From: Z.q. Hou
> Sent: 2018年11月6日 21:20
> To: linux-...@vger.kernel.o
Hi Leo,
Thanks a lot for your comments!
> -Original Message-
> From: Leo Li
> Sent: 2018年11月9日 5:29
> To: Z.q. Hou ; linux-...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; bhelg...@google.com;
Hi Rob,
Thanks a lot for your ACK!
> -Original Message-
> From: Rob Herring
> Sent: 2018年11月13日 2:13
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@
Hi Lorenzo,
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2018年12月5日 23:40
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; jingooh...@gmail.com;
> gustavo.pimen...@synopsys.com; Roy Zang ; Mingkai Hu
>
Hi Lorenzo,
Thanks a lot for your comments!
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2018年12月6日 0:02
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; jingooh...@gmail.com;
> gustavo.pimen...@s
From: Hou Zhiqiang
This patchset adds 2 workarounds for NXP Layerscape Gen4 PCIe controller
driver.
Hou Zhiqiang (2):
PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
depends on patchset:
https://patchwork.ozlabs.org/project/linu
From: Hou Zhiqiang
When LX2 PCIe controller is sending multiple split completions and
ACK latency expires indicating that ACK should be send at priority.
But because of large number of split completions and FC update DLLP,
the controller does not give priority to ACK transmission. This
results in
From: Hou Zhiqiang
PCIe configuration access to non-existent function triggered
SERROR interrupt exception.
Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.
This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.
Signed-off-b
From: Hou Zhiqiang
This patchset adds 2 workarounds for NXP Layerscape Gen4 PCIe controller
driver.
Hou Zhiqiang (2):
PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
depends on patchset:
https://patchwork.ozlabs.org/project/linu
From: Hou Zhiqiang
PCIe configuration access to non-existent function triggered
SERROR interrupt exception.
Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.
This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.
Signed-off-b
From: Hou Zhiqiang
When LX2 PCIe controller is sending multiple split completions and
ACK latency expires indicating that ACK should be send at priority.
But because of large number of split completions and FC update DLLP,
the controller does not give priority to ACK transmission. This
results in
From: Hou Zhiqiang
This patch set is to add prefetchable memory range support, patch 5/5.
Patch 1/5 and 2/5 are to initialize the number of viewport for
layerscape PCIe.
BTW, fix 2 bugs, see patch 3/5 and 4/5.
Hou Zhiqiang (5):
ARM: dts: ls1021a: add num-viewport property for PCIe DT nodes
a
From: Hou Zhiqiang
Add num-viewport property for PCIe DT nodes to specify how many
viewports are implemented.
Signed-off-by: Hou Zhiqiang
---
V3:
- New patch
arch/arm/boot/dts/ls1021a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/d
From: Hou Zhiqiang
To avoid memory leak on error return of the adjacent function
devm_of_pci_get_host_bridge_resources(), change to use
devm_pci_alloc_host_bridge() to allocate host bridge structure,
then it will be managed automatically.
Fixes: 295aeb98a322 ("PCI: designware: Convert PCI scan A
From: Hou Zhiqiang
The current type of mem_size is 'u32', so when resource_size()
return 4G it will be truncated to zero. This patch fix it by
changing its type to 'u64'.
Fixes: 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos")
Signed-off-by: Hou Zhiqiang
Acked-by: Gustavo Pimentel
---
From: Hou Zhiqiang
Add num-viewport property for PCIe DT nodes to specify how many
viewports are implemented.
Signed-off-by: Hou Zhiqiang
---
V3:
- New patch
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/fre
From: Hou Zhiqiang
The current code only support non-prefetchable memory range,
as the non-prefetchable memory range must not be greater than
4GiB, one viewport can cover it, which supports upto 4GiB.
To support prefetchable memory range, which is upto 64-bit
memory space and can be greater than
Hi Rob,
Thanks a lot for your comments!
> -Original Message-
> From: Rob Herring
> Sent: 2018年12月6日 6:39
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@
Hi Lorenzo,
Thanks a lot for your comments!
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2018年11月29日 2:00
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; jingooh...@gmail.com;
> gustavo.pimen...@s
From: Hou Zhiqiang
This patch set is aim to refactor the Mobiveil driver and add
PCIe support for NXP LX series SoCs.
Hou Zhiqiang (23):
PCI: mobiveil: uniform the register accessors
PCI: mobiveil: format the code without function change
PCI: mobiveil: correct the returned error number
P
From: Hou Zhiqiang
The current code does not support multiple MSIs, so remove
the corresponding flag from the msi_domain_info structure.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/contro
From: Hou Zhiqiang
It should get PCI base address from the DT node property 'ranges'
to setup MEM/IO outbound windows instead of always zero.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/
From: Hou Zhiqiang
This patch corrected the returned error number by convention,
and removed a unnecessary error check.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/pcie
From: Hou Zhiqiang
It's confused that R/W some registers by csr_readl()/csr_writel(),
while others by read_paged_register()/write_paged_register().
Actually the low 3KB of 4KB PCIe configure space can be accessed
directly and high 1KB is paging area. So this patch uniformed the
register accessors
From: Hou Zhiqiang
Just format the code without functionality change.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 261 +
1 file changed, 137 insertions(+), 124 deletions(-)
diff --git a/drivers/pci/controller/pcie-mobiveil.c
b/drivers/pci/
From: Hou Zhiqiang
As it won't delete any node in this iteration, replaced
the function resource_list_for_each_entry_safe() with
the resource_list_for_each_entry().
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Hou Zhiqiang
As the .map_bus() use the WIN_NUM_0 for CFG transactions,
it's better passing WIN_NUM_0 explicitly when initialize
the CFG outbound window.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
From: Hou Zhiqiang
Fixup the Class Code to PCI bridge, do not change the Revision ID.
And move the fixup to *_host_init function.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/cont
From: Hou Zhiqiang
The inbound windows have different register set with outbound windows.
This patch change the MEM inbound window to the first one.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
From: Hou Zhiqiang
Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some
platorms.
Signed-off-by: Hou Zhiqiang
---
Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++
1 file changed, 2 insertions(+)
diff
From: Hou Zhiqiang
Outbound window routine:
- Removed unused var definition and register read operations.
- Added the upper 32-bit cpu address setup of the window.
- Instead of blindly write, only change the fields specified.
- Masked the lower bits of window size in case override the
cont
From: Hou Zhiqiang
Move irq_set_chained_handler_and_data() out of DT parse function.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-mobiveil.c
b/drivers/pci/controller/p
From: Hou Zhiqiang
The reset value is all zero, so set a workable value for Primary,
Secondary and Subordinate bus numbers.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/pcie-mobiveil.c
b
From: Hou Zhiqiang
Host initial sequence does not depend on PCIe link up, so move it
to the place just before the enumeration.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/pcie-mobiveil.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/
From: Hou Zhiqiang
Sometimes there is not a PCIe Endpoint in the PCIe slot, so do
not exit when the PCIe link is not up. And degrade the print
level of link up info.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 1 -
drivers/pci/controller/mobiveil/pcie
From: Hou Zhiqiang
As the Mobiveil PCIe controller support RC&EP DAUL mode, and to
make Platforms which integrated the Mobiveil PCIe IP more easy
to add their drivers, this patch moved the Mobiveil driver to
a new directory 'drivers/pci/controller/mobiveil' and refactored
it to different file acc
From: Hou Zhiqiang
In the loop block, there is not code change the loop key,
this patch updated the loop key by re-read the INTx status
register.
This patch also change to clear the handled INTx status.
Note: Need MV to test this change.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller
From: Hou Zhiqiang
As there are some Byte and Half-Work width registers in PCIe
configuration space, add Byte and Half-Word width register
accessors.
Signed-off-by: Hou Zhiqiang
---
.../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++
1 file changed, 20 insertions(+)
diff -
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 157 ++
1 file changed, 157 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 6ba722e373ee..49dfaaf
From: Hou Zhiqiang
This PCIe controller is based on the Mobiveil GPEX IP, which is
compatible with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/mobiveil/Kconfig | 10 +
drivers/pci/controller/mobiveil/Makefile | 1 +
dr
From: Hou Zhiqiang
Add PCIe controller DT bindings of NXP LX series SoCs.
Signed-off-by: Hou Zhiqiang
---
.../devicetree/bindings/pci/lx-pci.txt| 52 +++
MAINTAINERS | 8 +++
2 files changed, 60 insertions(+)
create mode 100644 Docume
From: Hou Zhiqiang
Add a parameter 'bool reinit' to identify re-initializing the
host controller, and export it.
Signed-off-by: Hou Zhiqiang
---
.../pci/controller/mobiveil/pcie-mobiveil-host.c | 16 +---
drivers/pci/controller/mobiveil/pcie-mobiveil.h | 1 +
2 files changed, 10
From: Hou Zhiqiang
Disabled all inbound and outbound windows before set up the windows
in kernel, in case transactions match the window set by bootloader.
Signed-off-by: Hou Zhiqiang
---
.../controller/mobiveil/pcie-mobiveil-host.c | 7 +++
.../pci/controller/mobiveil/pcie-mobiveil.c
Hi Leo,
Thanks a lot for your comments!
> -Original Message-
> From: Li Yang
> Sent: 2018年10月27日 4:58
> To: Z.q. Hou
> Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> ; lkml ;
> linux-...@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED
> DE
Hi Leo,
Thanks a lot for your comments!
> -Original Message-
> From: Li Yang
> Sent: 2018年10月27日 5:01
> To: Z.q. Hou
> Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> ; lkml ;
> linux-...@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED
> DE
Hi Bjorn,
Thanks a lot for your guide!
I'll tag it for stable in v2.
Thanks,
Zhiqiang
> -Original Message-
> From: Bjorn Helgaas
> Sent: 2018年10月30日 0:31
> To: Z.q. Hou
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelg...@google.com; lorenzo
From: Hou Zhiqiang
The order of parameters is not correct when invoking the outbound
window disable routine.
Fixes: commit 4a2745d760fac ("PCI: layerscape: Disable outbound
windows configured by bootloader").
Cc: sta...@vger.kernel.org
Signed-off-by: Hou Zhiqiang
---
V2:
- Tagged this patch f
From: Hou Zhiqiang
Removed the compatible string "snps,dw-pcie", it is for the reference
platform driver for PCI RC IP Protoyping Kits based on the ARC SDP,
so it is not suitable for all platform with designware PCIe controller,
and platform vendors have themselves' drivers.
The compatible strin
From: Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang
---
V3:
- Reworded the subject.
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.
From: Hou Zhiqiang
Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci compatible
string list.
Hou Zhiqiang (4):
dt-bindings: pci: layerscape-pci: add compatible strings
"fsl,ls1043a-pcie"
dt-bindings: pci: layerscape-pci: removed compatible string
"snps,dw-pcie"
A
From: Hou Zhiqiang
The PCIe compatible string for LS1043A was lost, so add it.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
---
V3:
- no change
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindi
From: Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang
---
V3:
- Reworded the subject.
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
arch/arm64/bo
From: Hou Zhiqiang
Free the allocated pci_host_bridge struct when failed to get
host bridge resources, and free the resource windows before
free the bridge.
Signed-off-by: Hou Zhiqiang
Acked-by: Gustavo Pimentel
---
V2:
- Reworded the subject.
drivers/pci/controller/dwc/pcie-designware-host
From: Hou Zhiqiang
This patch set is to add prefetchable memory range support, patch 4/4.
Patch 3/4 is to initialize the number of viewport for layerscape PCIe.
BTW, fix 2 bugs, see patch 1/4 and 2/4.
Hou Zhiqiang (4):
PCI: dwc: fix potential memory leak
PCI: dwc: fix 4GiB outbound window si
From: Hou Zhiqiang
FSL implements 6 viewports on Layerscape series SoCs PCIe
controllers.
Signed-off-by: Hou Zhiqiang
---
V2:
- Reworded the subject and commit description.
drivers/pci/controller/dwc/pci-layerscape.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controll
From: Hou Zhiqiang
The current code only support non-prefetchable memory range,
as the non-prefetchable memory range must not be greater than
4GiB, one viewport can cover it, which supports upto 4GiB.
To support prefetchable memory range, which is upto 64-bit
memory space and can be greater than
From: Hou Zhiqiang
The current type of mem_size is 'u32', so when resource_size()
return 4G it will be truncated to zero. This patch fix it by
changing its type to 'u64'.
Signed-off-by: Hou Zhiqiang
Acked-by: Gustavo Pimentel
---
V2:
- Reworded the subject.
drivers/pci/controller/dwc/pcie-d
From: Hou Zhiqiang
This issue is introduced by commit 4a2745d760fac ("PCI: layerscape: Disable
outbound windows configured by bootloader").
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pci-layerscape.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pc
From: Hou Zhiqiang
Free the allocated pci_host_bridge struct when failed to get
host bridge resources, and free the resource windows before
free the bridge.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
From: Hou Zhiqiang
The current type of mem_size is 'u32', so when resource_size()
return 4G it will be truncated to zero. This patch fix it by
changing its type to 'u64'.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
drivers/pci/controller/dwc/pcie-desi
From: Hou Zhiqiang
As each viewport support upto 4GiB, to support greater than 4GiB range
we need multiple viewport for MEM windows. And this patch explicitly
assigned the last (if there are only 2 viewports) or last 2 viewports
for CFG and IO windows and the rests for MEM windows.
Signed-off-by
From: Hou Zhiqiang
This patch set is to add greater than 4GiB range support, patch 4/4.
Patch 3/4 is to initialize the number of viewport.
BTW, fix 2 bugs, see patch 1/4 and 2/4.
Hou Zhiqiang (4):
PCI/dwc: fix potential memory leak
PCI/dwc: Fix the 4GiB outbound window size truncated to zero
From: Hou Zhiqiang
FSL implements 6 viewports on Layerscape series SoCs.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pci-layerscape.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c
b/drivers/pci/controller/dwc/pci-layerscape.c
Hi Rob,
Thanks a lot for your comments!
> -Original Message-
> From: Rob Herring
> Sent: 2018年10月17日 21:52
> To: Z.q. Hou
> Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; Leo Li
>
Thanks Rob!
> -Original Message-
> From: Rob Herring
> Sent: 2018年10月17日 21:53
> To: Z.q. Hou
> Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; Leo Li
> ; shawn...@kernel.org; mark.rut
From: Hou Zhiqiang
Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci compatible
string list.
Hou Zhiqiang (4):
dt-bindings: pci: layerscape-pci: add compatible strings
"fsl,ls1043a-pcie"
dt-bindings: pci: layerscape-pci: removed compatible string
"snps,dw-pcie"
d
From: Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang
---
V2:
- no change
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/
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