From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
.../bindings/sound/rockchip,rk3399-gru-sound.txt |6 ++
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename dmic-delay to dmic-wakeup-delay-ms
.../bin
Hi Mark,
On 2016年09月19日 22:44, Mark Rutland wrote:
On Mon, Sep 19, 2016 at 10:29:39PM +0800, Xing Zheng wrote:
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-o
Hi,
These patchset fix some clocks bugs, and improve clock configuration
for i2s/spdif/MAC on RK322x SoCs.
Thanks.
Xing Zheng (5):
clk: rockchip: rk3228: fix incorrect clock node names
clk: rockchip: rk3228: include downstream muxes into fractional
dividers
clk: rockchip: rk3228
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c | 79 -
1 file changed, 51 insertions(+), 28
Due to copy and paste carelessly, RK3288_CLKxxx nodes are incorrect,
we need to fix them.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk
This patch exports related i2s/spdif clocks for dts reference.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c |8
include/dt-bindings/clock/rk3228-cru.h |4
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk
The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock clearly.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk
This patch exports related MAC clocks for dts reference.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c | 22 +++---
include/dt-bindings/clock/rk3228-cru.h | 11 +++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/clk
Add constants and callback functions for the dwmac on rk322x socs.
As can be seen, the base structure is the same, only registers and
the bits in them moved slightly.
Signed-off-by: Xing Zheng
---
.../devicetree/bindings/net/rockchip-dwmac.txt |3 +-
drivers/net/ethernet/stmicro/stmmac
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
2 files changed, 91 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3229
This patch add the i2s dt nodes for rk3228 SoCs.
Signed-off-by: Xing Zheng
---
arch/arm/boot/dts/rk3228.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index e23a22e..e224147
This patch add the GMAC dt nodes for rk3228 SoCs.
Signed-off-by: Xing Zheng
---
arch/arm/boot/dts/rk3228.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index e224147..4c0223c
Hi,
These patchset add i2s/gmac dts nodes for RK322x SoCs,
and add the new dts file of the rk3229 evb board.
Thanks.
Xing Zheng (3):
ARM: dts: rockchip: add i2s nodes for RK3228 SoCs
ARM: dts: rockchip: add GMAC nodes for RK3228 SoCs
ARM: dts: rockchip: add support rk3229 evb board
elow,
just add a second compatible).
OK, I try to just use "rockchip,rk3228-gmac" to point to "rk322x_ops"
which is the same structure in MAC driver,
and both rk3228 and rk3229 use it.
Thanks
--
- Xing Zheng
Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.
Signed-off-by: Xing Zheng
---
Changes in v2:
- the "rk322x" is not clear to SoC decription, rename it
Hi Heiko,
On 2016年06月22日 07:07, Heiko Stuebner wrote:
Am Dienstag, 21. Juni 2016, 12:53:26 schrieb Xing Zheng:
Hi,
These patchset fix some clocks bugs, and improve clock configuration
for i2s/spdif/MAC on RK322x SoCs.
applied to my clock-branch with the following changes:
- fixed the
This patch add the i2s dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
arch/arm/boot/dts/rk3229
This patch add the GMAC dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
RK322x SoCs,
and add the new dts file of the rk3229 evb board.
Thanks.
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
Xing Zheng (4):
ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
ARM: dts: rockchip: add i2s nodes for RK322x SoCs
ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
This patch add the i2s dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
arch/arm/boot/dts/rk3229
RK322x SoCs,
and add the new dts file of the rk3229 evb board.
Thanks.
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
Xing Zheng (4):
ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
ARM: dts: rockchip: add i2s nodes for RK322x SoCs
ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
This patch add the GMAC dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 21 -
1
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 21 -
1
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (6):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect parent for rk3399's {c,
g}pll_aclk_perihp_src
clk: r
There was a typo, swapping 'c' <--> 'g'.
And sorry to refer incorrect clock diagram, we double check it that
the bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Signed-off-by:
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 del
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
Changes in v2: None
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v2:
- add the patch "fix incorrect parent for rk3399
There was a typo, swapping 'c' <--> 'g'.
(This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
Signed-off-by: Xing Zheng
Signed-off-by: Brian Norris
Reviewed-by: Douglas Anderson
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
Changes in v2: None
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
GATE bits for {c, g}pll_aclk_perihp_src"
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (7):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3
Sorry to refer incorrect clock diagram, we double check it that the
bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c
.
On 2016年05月16日 23:49, Doug Anderson wrote:
Hi,
On Fri, May 13, 2016 at 8:36 PM, Xing Zheng wrote:
Hi Doug,
On 2016年05月14日 04:10, Doug Anderson wrote:
Hi,
On Fri, May 13, 2016 at 11:42 AM, Brian Norris
wrote:
From: Xing Zheng
There was a typo, swapping 'c' <--> 'g&#
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 del
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v2:
- add the patch "fix incorrect parent for rk3399
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk
From: Hsin-Yu Chao
On some platform da7219 codec has persistent power across reboot
so it doesn't reset and cause abnormal jack detection.
Workaround this issue by doing software reset at probe.
Signed-off-by: Hsin-Yu Chao
Signed-off-by: Xing Zheng
---
sound/soc/codecs/da7219.
From: Hsin-Yu Chao
Da7219 does not trigger interrupt to report jack status
when system boots from warm reset because its power
remains on during warm reset.
Doing software reset at probe to handle this.
Signed-off-by: Hsin-Yu Chao
Signed-off-by: Xing Zheng
---
Changes in v2:
- change the
),
RK3399_CPUCLKB_RATE(18, 1, 8, 8),
It looks good to me.
Reviewed-by: Xing Zheng
Thanks.
--
- Xing Zheng
Hi Heiko,
On 2016年08月05日 03:19, Heiko Stübner wrote:
Hi Xing,
Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs
Hi Heiko,
On 2016年08月05日 16:48, Heiko Stübner wrote:
Hi Xing,
Am Freitag, 5. August 2016, 10:26:57 schrieb Xing Zheng:
On 2016年08月05日 03:19, Heiko Stübner wrote:
Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
We need to support various display resolutions for external
display
mprovement
significantly when tesing SPI transfer etc.
default single mode
[ 88.292550] spi write 65536*1 cost 32402us speed:2022KB/S
After applied with burst mode(len 16)
[ 17.625296] spi write 65536*1 cost 17830us speed:3675KB/S
Cc: Huibin Hong
Cc: Xing Zheng
Signed-off-by: Shawn Lin
---
TPB 12
f004102e:DMAFLUSHP 12
f0041030:DMALPENDA_1 bjmpto_7
f0041032:DMASEV 0
f0041034:DMAEND
Signed-off-by: Shawn Lin
Tested-by: Xing Zheng
Thanks.
--
- Xing Zheng
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts
Hi Shawn,
On 2016年08月26日 17:41, Shawn Lin wrote:
On 2016/8/26 14:22, Xing Zheng wrote:
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software
ll update the TRM to fix it.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename node name "watchdog" to "watchdog0" explicitly
arch/arm64/boot/dts/rockchip/rk3399.dtsi |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/roc
Many parts of pinctrl rk3036 are similar to rk2928's.
Signed-off-by: Xing Zheng
---
Changes in v1: None
drivers/pinctrl/pinctrl-rockchip.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
Hi,
We need to support rk3036 soc platform via upstream, there are
3 parts for the initial release of minimum system: dts, pinctrl,
and clock tree for rk3036, startup and run to init processs.
Thanks.
Changes in v1:
Signed-off-by: Xing Zheng
Xing Zheng (3):
ARM: dts: rockchip: add core
Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume should be done
in clk-rk3036.c
---
Changes in v1:
Signed-off-by: Xing Zheng
drivers/clk/rockchip
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
---
Changes in v1: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-sdk.dts | 362 ++
2 files changed, 363 insertions(+)
create mode 100644
HI Heiko,
Thank you for your reply. I will improve them as quickly as possible.
Thanks. :)
On 2015年08月28日 17:59, Heiko Stuebner wrote:
Hi,
Am Freitag, 28. August 2015, 13:46:45 schrieb Xing Zheng:
We need to support rk3036 soc platform via upstream, there are
3 parts for the initial release
) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add new pll-type for rk3036 and similar socs
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v4:
Signed-off-by: Xin
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
include/dt-bindings/clock/rk3036-cru.h | 195
1 file
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Ch
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c | 500 +
drivers/clk/rockchip/clk.h
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56
1 file changed, 56
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/arm/boot/dts/rk3036.dtsi| 536
powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner
Tested-by: Xing Zheng
Signed-off-by: Xing Zheng
---
Changes in v4: None
Documentation/devicetree/bindings/arm
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v4:
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
arch/arm/mach-rockchip/rockchip.c | 44 +++--
1 file
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56
1 file changed, 56
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Ch
mentation of rk3036 clock controller
Changes in v5:
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
Heiko Stuebner (1):
ARM: rockchip: add support smp for rk3036
Xing Zheng (7):
dt-bindings: add documentation of rk3036 clock controller
clk: rockchip: add dt-binding header for rk3036
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c | 500 +
drivers/clk/rockchip/clk.h
Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
include/dt-bindings/clock/rk3036-cru.h | 195
1 file
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/arm/boot/dts/rk3036.dtsi| 536
powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner
Tested-by: Xing Zheng
Signed-off-by: Xing Zheng
---
Changes in v5: None
Documentation/devicetree/bindings/arm
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v5:
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
arch/arm/mach-rockchip/rockchip.c | 44 +++--
1 file
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v1:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc
Hi,
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
Thanks.
Changes in v1:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
Xing Zheng (1):
ASoC: rockchip: fix a misjudgement by return
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1
Hi,
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
Thanks.
Changes in v1:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
Xing Zheng (1):
ASoC: rockchip: fix a misjudgement by return
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v1:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v2:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc
data(pdev);
+
+ snd_soc_unregister_card(soc_card);
+
+ return 0;
+}
+
+static const struct of_device_id rockchip_rt5645_of_match[] = {
+ { .compatible = "rockchip,rockchip-audio-rt5645", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_rt5645_of_match);
+
+static st
From: zhengxing
Hi,
The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.
- use ts3a227e for ext ja
From: zhengxing
The driver is used for rockchip board using a max98090.
Reviewed-by: Dylan Reid
Signed-off-by: zhengxing
---
Changes in v2: None
.../bindings/sound/rockchip-max98090.txt | 19 ++
sound/soc/rockchip/Kconfig | 10 +
sound/soc/rockchip/Make
1 - 100 of 336 matches
Mail list logo
