Dear Heiko,
On 06/20/2016 10:44 PM, Heiko Stübner wrote:
Hi William,
Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
This patch adds the devicetree documentation required for
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.
Signed-off-by: William Wu
---
.../devicetree/bindings/usb/rockchip,dwc3.txt
This series add support for usb3 controller on RK3328 SoCs.
This series don't include usb3 phy patches, and I will try
to submit usb3 phy patches individually later.
Tested on RK3328 evaluation board.
William Wu (2):
arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs
arm64
Rockchip's RK3328 evaluation board has one USB 3.0 OTG controller,
we enable it and set it act as static xHCI host controller to
support USB 3.0 HOST on RK3328 evaluation board.
Signed-off-by: William Wu
---
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 9 +
1 file changed, 9 inser
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.
Signed-off-by: William Wu
---
Changes in v2:
- Modify the dwc3 quirk "snps,tx-ipgap
Rockchip's RK3328 evaluation board has one USB 3.0 OTG controller,
we enable it and set it act as static xHCI host controller to
support USB 3.0 HOST on RK3328 evaluation board.
Signed-off-by: William Wu
---
Changes in v2:
- None
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 9 +++
This series add support for usb3 controller on RK3328 SoCs.
This series don't include usb3 phy patches, and I will try
to submit usb3 phy patches individually later.
Tested on RK3328 evaluation board.
William Wu (2):
arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs
arm64
heck-quirk" to
disable the u2mac linestate check to decrease the SSPLIT token
to SETUP token inter-packet delay from 566ns to 466ns.
Signed-off-by: William Wu
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk33
: William Wu
---
drivers/usb/dwc2/hcd.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 740c7e8..cc84f97 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1975,11 +1975,13 @@ void
Let's update the urb actual_length if the isoc frame
is valid.
Signed-off-by: William Wu
---
drivers/usb/dwc2/hcd_intr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 28a8210..01b1e13 100644
--- a/drivers/usb/dwc2/hcd_in
GUID register after powering on the PHYs.
Signed-off-by: William Wu
---
drivers/usb/dwc3/core.c | 46 ++
1 file changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index c32d2b9..4f5573f 100644
This series adds USB3 OTG controller reset for rk3399 Type-C PHY, and use the
reset to hold the whole USB3 OTG controller in reset state to keep the PIPE
power state in P2 before initializing Type-C PHY, it's useful to avoid waiting
for PHY PMA and PIPE ready timeout.
William Wu (3):
igned-off-by: William Wu
---
drivers/phy/rockchip/phy-rockchip-typec.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c
b/drivers/phy/rockchip/phy-rockchip-typec.c
index ee85fa0..68a5840 100644
--- a/driver
Add USB3 OTG reset for Type-C PHY. It can be used to hold the USB3
OTG controller in reset state before initializing the Type-C PHY.
Signed-off-by: William Wu
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64
This patch adds USB3 OTG reset property for rk3399 Type-C PHY
to hold the USB3 controller in reset state.
Signed-off-by: William Wu
---
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation
igned DMA for isoc split in.
Signed-off-by: William Wu
---
Changes in v2:
- None
drivers/usb/dwc2/hcd.c | 63 +---
drivers/usb/dwc2/hcd.h | 10 +++
drivers/usb/dwc2/hcd_intr.c | 8 ++
drivers/usb/dwc2/hcd_queue.c | 8 +-
4 files c
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
SPLIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu
---
Changes in v2:
- Modify the commit message
drive
Signed-off-by: William Wu
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-simple.c
index 9743353..1f3665b 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
drivers/usb/dwc3
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (4):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy interface
t set to the corresponding value according to the usb2
phy interface.
Signed-off-by: William Wu
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/core.c| 13 +
drivers/usb/dwc3/core.h| 8
drivers/usb
Signed-off-by: William Wu
---
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e15e307..f268869 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -86,6
On 05/09/2016 08:10 PM, Felipe Balbi wrote:
William Wu writes:
Thanks Felipe Balbi and Greg KH. I'm really sorry that I forgot to
add changelog.
Signed-off-by: William Wu
no changelog = no commit, sorry. Why do you want to dump GUCTL1?
Because GUCTL1 can be written by user
On 05/09/2016 08:18 PM, Felipe Balbi wrote:
Hi,
William Wu writes:
Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
this needs a quirk_ prefix...
Yes, maybe a quirk is more proper. As you mentioned,
the PHYIf can be configured during coreconsultant.
But for some
Dear Felipe & Doug,
Thanks for your proposal. It's a good idea to sort the list.
I'll fix it next patch version.
On 05/10/2016 03:14 PM, Felipe Balbi wrote:
Hi,
Doug Anderson writes:
William,
On Mon, May 9, 2016 at 4:46 AM, William Wu wrote:
Signed-off-
rtunate as me to have been CC'd on your
patch directly.
Actually, I don't know the linux-rockc...@lists.infradead.org before.
I'll add the list in CC next patch version.
Thanks~
On Mon, May 09, 2016 at 07:46:14PM +0800, William Wu wrote:
Signed-off-by: William Wu
---
drivers/
Dear Felipe,
On 05/10/2016 04:11 PM, Felipe Balbi wrote:
Hi William,
William Wu writes:
Dear Felipe & Doug,
Thanks for your proposal. It's a good idea to sort the list.
I'll fix it next patch version.
cool, thanks.
ps: top-posting is frowned upon here. P
Hi Felipe,
On 05/24/2016 05:32 PM, Felipe Balbi wrote:
Hi,
William Wu writes:
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed
Hi Felipe & Rob,
On 05/25/2016 04:04 PM, Felipe Balbi wrote:
Hi,
William Wu writes:
Hi Felipe,
On 05/24/2016 05:32 PM, Felipe Balbi wrote:
Hi,
William Wu writes:
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Changes in v3:
- None
Changes in v2:
- None
Documentation/devicetree
PHYIf
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu
---
Changes in v3:
- None
Changes in v2:
- add a quir
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu
---
Changes in v3:
- None
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Changes in v3:
- None
Changes in v2:
- None
Documentation/devicetree
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: William Wu
---
Changes in v3:
- add dwc3 address (Felipe)
Changes in v2
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3
PHYIf
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu
---
Changes in v2:
- add a quirk for phyif_utmi (F
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Changes in v2:
- None
Documentation/devicetree/bindings/usb/dwc3.txt | 2
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Changes in v2:
- None
Documentation/devicetree/bindings/usb/dwc3.txt | 3
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu
---
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion
Dear Felipe,
On 05/13/2016 05:37 PM, Felipe Balbi wrote:
Hi,
William Wu writes:
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: William Wu
---
Changes in v2:
- add rockchip,dwc3.txt to Documentation
reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu
---
Changes in v2:
- add commit log
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b
On 05/13/2016 06:05 PM, William Wu wrote:
GUCTL1 reg has some useful functions which can be
written by user. For rockchip platform, we set
GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK (bit26, applicable
for the core is programmed to operate in 2.0 device
only) to 1 in bootrom, and after start the kernel
reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu
---
Changes in v2:
- add commit log
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b
request correctly.
Signed-off-by: William Wu
---
drivers/usb/gadget/composite.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index d67de0d..eb64848 100644
--- a/drivers/usb/gadget/composite.c
this patch, I can easily meet a Kernel panic issue
if connect a low-speed USB mouse with the max port of FE2.1
multi-tt hub (1a40:0201) on rk3288 platform.
Signed-off-by: William Wu
---
drivers/usb/dwc2/hcd_queue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc2
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
SPLIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu
---
drivers/usb/dwc2/hcd_intr.c | 2 +-
1 file changed,
igned DMA for isoc split in.
Signed-off-by: William Wu
---
drivers/usb/dwc2/hcd.c | 63 +---
drivers/usb/dwc2/hcd.h | 10 +++
drivers/usb/dwc2/hcd_intr.c | 8 ++
drivers/usb/dwc2/hcd_queue.c | 8 +-
4 files changed, 85 insertio
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
Note that according to usb 2.0 spec, the
maximum data payload size is 1023 bytes for each fs isoc ep,
and the maximum allowable interrupt data payload size is 64 bytes
or less for fs interrupt ep. So we set the size of object to be
1024 bytes in the kmem cache.
Signed-off-by: William Wu
---
Chan
SPLIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu
---
Changes in v4:
- None
Changes in v3:
-
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
Note that according to usb 2.0 spec, the
maximum data payload size is 1023 bytes for each fs isoc ep,
and the maximum allowable interrupt data payload size is 64 bytes
or less for fs interrupt ep. So we set the size of object to be
1024 bytes in the kmem cache.
Signed-off-by: William Wu
Re
SPLIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu
---
Changes in v5:
- None
Changes in v4:
- None
Ch
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
Note that according to usb 2.0 spec, the
maximum data payload size is 1023 bytes for each fs isoc ep,
and the maximum allowable interrupt data payload size is 64 bytes
or less for fs interrupt ep. So we set the size of object to be
1024 bytes in the kmem cache.
Signed-off-by: William Wu
---
Changes
SPLIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu
---
Changes in v3:
- Remove "qtd->isoc_split_of
From: William wu
On some platforms(e.g. rk3399 board), we can call hcd_add/remove
consecutively without calling usb_put_hcd/usb_create_hcd in between,
so hcd->flags can be stale.
If the HC dies due to whatever reason then without this patch we get
the below error on next hcd_add.
[173.296
From: William wu
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because xHCI
driver sets hcc_params in xhci_gen_setup() called from
usb_add_hcd().
This patch checks the Maximum Prim
From: William wu
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because xHCI
driver sets hcc_params in xhci_gen_setup() called from
usb_add_hcd().
This patch checks the Maximum Prim
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Changes in v6:
- use '-' instead of '_' in dts (Rob Her
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu
---
Changes in v6:
- None
Changes in v5:
- change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3" (H
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Changes in v6:
- use '-' instead of '_' in dts (Rob Her
PHYIf
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu
---
Changes in v6:
- use '-' instead of '_&
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu
---
Changes in v6:
- rename bus_clk, and
, the
default PHYIF configuration value is fault, so we need to
reconfigure it by software.
And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to the
UTMI+ PHY interface.
Signed-off-by: William Wu
---
Changes in v7:
- remove quirk and use onl
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Changes in v7:
- None
Changes in v6:
- use '-' instead of '
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu
---
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- change compatible from "rockchip,dwc3" to "rockc
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Changes in v7:
- None
Changes in v6:
- use '-' instead of '
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu
Acked-by: Rob Herring
---
Changes in v7
Dear Heiko,
On 06/30/2016 08:15 PM, Heiko Stuebner wrote:
Hi William,
Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could
Dear Rob,
On 07/01/2016 10:32 AM, Rob Herring wrote:
On Thu, Jun 30, 2016 at 07:12:53PM +0800, William Wu wrote:
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is
Dear Rob,
On 07/01/2016 10:38 AM, Rob Herring wrote:
On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3
integrated in DWC3 IP core,
and we don't need to add xhci node separately, but just add dwc3
node like this:
usbdrd3_0: usb@fe80 {
compatible = "rockchip,rk3399-dwc3";
..
ranges;
status = "disabled";
usbdrd_dwc3_0: dwc3@fe80 {
compatible = "sn
Dear Sergei,
On 05/27/2016 07:54 PM, Sergei Shtylyov wrote:
Hello.
On 5/27/2016 2:31 PM, William Wu wrote:
This patch documents the device tree documentation required for
Documents the documentation? :-)
Ah, my commit log seems a little weird. I'll corrcet it next patch.
T
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu
---
Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu
---
Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu
---
Changes in v4:
- modify commit log, and
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/usb/dwc3/dwc3-of
PHYIf
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu
---
Changes in v4:
- rebase on top of balbi testing/next, r
the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
clk_ops callback") used prepare callbacks instead of enable
callbacks to support gate a clk if the operation may sleep. So
we can switch from delay to sleep functions.
Signed-off-by: William Wu
---
Changes in v2:
- use us
latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Signed-off-by: William Wu
---
drivers/phy/phy-rockchip-inno-usb2.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/p
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock gate more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2
latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Signed-off-by: William Wu
---
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/phy-rockchip-inno-usb2.c | 12 ++--
1 file changed, 6 i
the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
clk_ops callback") used prepare callbacks instead of enable
callbacks to support gate a clk if the operation may sleep. So
we can switch from delay to sleep functions.
Signed-off-by: William Wu
---
Changes in v3:
- fix kbuild test
;waiting".
Signed-off-by: William Wu
Reviewed-by: Douglas Anderson
---
Changes in v4:
- add Reviewed-by and fix a spelling error
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/phy-rockchip-inno-usb2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/p
latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Signed-off-by: William Wu
Reviewed-by: Douglas Anderson
---
Changes in v4:
- add Reviewed-by
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/ph
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock gate more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2
of USB2 PHY was
unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a critical value for 480 output
clock stable time, so we try changing the delay time to 1.2
millisecond to avoid this issue.
Signed-off-by: William Wu
---
drivers/phy/phy-rockchip-inno-usb2.c
This series add support for rk3399 USB2 PHY0 and PHY1 OTG port.
rk3399 has two USB2 PHYs, and each USB2 PHY is comprised of one
Host port and one OTG port. We have supported Host port before,
and try to support OTG port now.
Test on rk3399-evb board.
William Wu (2):
phy: rockchip-inno-usb2
Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can
be used for USB2.0 part of USB3.0 OTG controller.
Signed-off-by: William Wu
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399
Dear Heiko,
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Hi William,
Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate
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