g the need to duplicate the
> logic for warnings.
>
> There should be no functional change as a result of this patch.
>
> Signed-off-by: Mark Rutland
> Acked-by: Kees Cook
> Reviewed-by: David Sterba
> Cc: Boqun Feng
> Cc: Ingo Molnar
> Cc: Peter Zijlstra
Hi Alan,
On Thu, Jul 12, 2018 at 01:04:27PM -0400, Alan Stern wrote:
> On Thu, 12 Jul 2018, Peter Zijlstra wrote:
> > But as you (and Will) point out, we don't so much care about rmw-acquire
> > semantics as much as that we care about unlock+lock behaviour. Another
> > way to look at this is to de
On Fri, Jul 13, 2018 at 11:07:11AM +0200, Andrea Parri wrote:
> On Thu, Jul 12, 2018 at 07:05:39PM -0700, Daniel Lustig wrote:
> > On 7/12/2018 11:10 AM, Linus Torvalds wrote:
> > > On Thu, Jul 12, 2018 at 11:05 AM Peter Zijlstra
> > > wrote:
> > >>
> > >> The locking pattern is fairly simple and
On Tue, Jul 10, 2018 at 02:31:30PM -0400, Waiman Long wrote:
> It was found that a constant stream of readers might cause the count to
> go negative most of the time after an initial trigger by a writer even
> if no writer was present afterward. As a result, most of the readers
> would have to go t
Hi Linus,
Catalin's out enjoying the sunshine, so I'm sending the fixes for a couple
of weeks (although there hopefully won't be any more!). Summary is in the
tag, but we've got a revert of a previous fix because it broke the build
with some distro toolchains and a preemption fix when detemining w
Hi Olof,
On Fri, Jul 13, 2018 at 07:59:10AM -0700, Olof Johansson wrote:
> On Tue, Jul 10, 2018 at 10:36:16AM +0100, Will Deacon wrote:
> > On Tue, Jul 10, 2018 at 11:30:39AM +0200, Paul Kocialkowski wrote:
> > > On Tue, 2018-07-10 at 10:01 +0100, Will Deacon wrote:
>
Hi Agustin,
On Thu, Jul 05, 2018 at 04:23:17PM -0400, Agustin Vega-Frias wrote:
> This series is a complete re-design of V1 of the QCOM Falkor extensions [1],
> it introduces a probe table based on the HID of a device nested under the CPU
> device to allow variant detection and arm_pmu customizati
On Mon, Jan 22, 2018 at 02:00:59PM -0500, Jon Masters wrote:
> On 01/22/2018 06:33 AM, Will Deacon wrote:
> > On Fri, Jan 19, 2018 at 04:22:47AM -0800, Jayachandran C wrote:
> >> Use PSCI based mitigation for speculative execution attacks targeting
> >> the branch
On Tue, Jan 23, 2018 at 04:28:45PM +0800, Yisheng Xie wrote:
> On 2017/12/6 20:35, Will Deacon wrote:
> > +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
> > +static int __init map_entry_trampoline(void)
> > +{
> > + extern char __entry_tramp_text_start[];
> > +
>
On Wed, Jan 24, 2018 at 12:05:16PM +0300, Yury Norov wrote:
> This series adds API for 128-bit memory IO access and enables it for ARM64.
> The original motivation for 128-bit API came from new Cavium network device
> driver. The hardware requires 128-bit access to make things work. See
> descripti
Hi Paul,
On Tue, Jan 23, 2018 at 04:00:14PM -0800, Paul E. McKenney wrote:
> On Fri, Jan 19, 2018 at 09:12:11AM -0800, Paul E. McKenney wrote:
> > On Thu, Jan 18, 2018 at 07:58:55PM -0800, Paul E. McKenney wrote:
> > > Hello!
> > >
> > > There is some reason to believe that Documentation/memory-b
On Wed, Jan 24, 2018 at 11:35:03AM -0500, Mark Salter wrote:
> On Wed, 2018-01-24 at 10:58 +, Marc Zyngier wrote:
> > Khuong,
> >
> > On 24/01/18 02:13, Khuong Dinh wrote:
> > > Aliasing attacks against CPU branch predictors can allow an attacker to
> > > redirect speculative control flow on s
d, 2 insertions(+), 2 deletions(-)
Acked-by: Will Deacon
I guess Catalin can just pick this one up via arm64.
Will
> diff --git a/arch/arm64/kernel/probes/kprobes.c
> b/arch/arm64/kernel/probes/kprobes.c
> index d849d9804011..34f78d07a068 100644
> --- a/arch/arm64/kernel/probes/kprobes.c
On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote:
> On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> > From: Linu Cherian
> >
> > Add SMMUv3 model definition for ThunderX2.
> >
> > Signed-off-by: Linu Cherian
> > Signed-off-by: Geetha Sowjanya
>
> This is an AC
On Thu, May 11, 2017 at 04:40:51PM +0200, Rafael J. Wysocki wrote:
> On Thursday, May 11, 2017 09:45:25 AM Will Deacon wrote:
> > On Thu, May 11, 2017 at 02:26:02AM +0200, Rafael J. Wysocki wrote:
> > > On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> >
rs added in
> commit d54bb72551b999dd ("arm64/cpufeature: Use
> static_branch_enable_cpuslocked()").
>
> Signed-off-by: Mark Rutland
> Cc: Catalin Marinas
> Cc: Christoffer Dall
> Cc: Marc Zyniger
> Cc: Peter Zijlstra
> Cc: Sebastian Sewior
> Cc: Suzuki P
Hi Jiri,
On Mon, May 15, 2017 at 03:07:42PM +0200, Jiri Slaby wrote:
> There is code duplicated over all architecture's headers for
> futex_atomic_op_inuser. Namely op decoding, access_ok check for uaddr,
> and comparison of the result.
>
> Remove this duplication and leave up to the arches only
On Tue, Jan 09, 2018 at 09:17:00AM -0800, Christoph Hellwig wrote:
> On Mon, Jan 08, 2018 at 05:32:27PM +0000, Will Deacon wrote:
> > Although CONFIG_UNMAP_KERNEL_AT_EL0 does make KASLR more robust, it's
> > actually more useful as a mitigation against speculation attac
| 2 --
> 5 files changed, 12 insertions(+), 7 deletions(-)
For the arm64 parts:
Acked-by: Will Deacon
Will
Hi Dmitry,
On Mon, Jan 29, 2018 at 06:26:03PM +0100, Dmitry Vyukov wrote:
> KASAN uses compiler instrumentation to intercept all memory accesses.
> But it does not see memory accesses done in assembly code.
> One notable user of assembly code is atomic operations. Frequently,
> for example, an ato
gt;next a RELEASE
operation, which also removes the reliance on dependency ordering.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
kernel/locking/qspinlock.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/kernel/locking/qspinlock.c b/kerne
r.h | 6 ++
> 1 file changed, 6 insertions(+)
Acked-by: Will Deacon
One comment below...
> diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h
> index fe297b599b0a..7a10748615ff 100644
> --- a/include/asm-generic/barrier.h
> +++ b/include/asm-generic/barr
On Wed, Jan 31, 2018 at 09:53:10AM +0100, Dmitry Vyukov wrote:
> On Wed, Jan 31, 2018 at 8:28 AM, Ingo Molnar wrote:
> > * Will Deacon wrote:
> >> e.g. for atomic[64]_read, your asm-generic header looks like:
> >>
> >> #ifndef _LINU
ink this is the right thing to do and the smp_wmb() was accidentally
pulled in here as a copy-paste from the GICv2 driver where it is sufficient
in practice.
Did you spot this by code inspection, or did the DMB actually cause
observable failures? (trying to figure out whether or not this need to go
to -stable).
Anyway:
Acked-by: Will Deacon
Cheers,
Will
On Thu, Feb 01, 2018 at 02:29:09PM +0100, Peter Zijlstra wrote:
> On Thu, Feb 01, 2018 at 09:27:50PM +0900, Stafford Horne wrote:
> > I tried to clarify some of this in the spec v1.2 [0] which help formalize
> > some of
> > the techniques we used for the SMP implementation. Its probably not
> >
-kernel.bell | 2 +-
> tools/memory-model/linux-kernel.cat | 2 +-
> 4 files changed, 10 insertions(+), 10 deletions(-)
Acked-by: Will Deacon
Will
Signed-off-by: Andrea Parri
> ---
> MAINTAINERS| 16
> tools/memory-model/MAINTAINERS | 15 ---
> 2 files changed, 16 insertions(+), 15 deletions(-)
> delete mode 100644 tools/memory-model/MAINTAINERS
Acked-by: Will Deacon
Ma
On Thu, Feb 01, 2018 at 02:53:29PM +0100, Peter Zijlstra wrote:
> On Thu, Feb 01, 2018 at 01:32:30PM +0000, Will Deacon wrote:
> > On Thu, Feb 01, 2018 at 02:29:09PM +0100, Peter Zijlstra wrote:
> > > On Thu, Feb 01, 2018 at 09:27:50PM +0900, Stafford Horne wrote:
> > >
On Thu, Jan 18, 2018 at 08:58:08AM -0800, Dan Williams wrote:
> On Thu, Jan 18, 2018 at 5:18 AM, Will Deacon wrote:
> > On Thu, Jan 11, 2018 at 05:41:08PM -0800, Dan Williams wrote:
> >> On Thu, Jan 11, 2018 at 5:19 PM, Linus Torvalds
> >> wrote:
> >> &g
On Thu, Jan 18, 2018 at 09:59:26AM -0700, Mathieu Poirier wrote:
> On 17 January 2018 at 05:31, Alexander Shishkin
> wrote:
> > On Tue, Feb 07, 2017 at 10:50:50AM -0700, Mathieu Poirier wrote:
> >> > index 39106ae61b..d7a11faac1 100644
> >> > --- a/kernel/events/core.c
> >> > +++ b/kernel/events/c
On Fri, Jan 19, 2018 at 11:37:24AM +0800, Li Kun wrote:
> 在 2018/1/17 18:07, Will Deacon 写道:
> >On Wed, Jan 17, 2018 at 12:10:33PM +0800, Yisheng Xie wrote:
> >>On 2018/1/5 21:12, Will Deacon wrote:
> >>>diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/con
On Fri, Jan 19, 2018 at 10:12:47AM -0800, Dan Williams wrote:
> [ adding Alexei back to the cc ]
>
> On Fri, Jan 19, 2018 at 9:48 AM, Adam Sampson wrote:
> > Jann Horn writes:
> >
> >>> +/*
> >>> + * If idx is negative or if idx > size then bit 63 is set in the mask,
> >>> + * and the value of ~
ONS(MIDR_CAVIUM_THUNDERX2),
> + .enable = enable_psci_bp_hardening,
> + },
> #endif
Thanks.
Acked-by: Will Deacon
Will
ID_AA64PFR0_CSV3_SHIFT);
We'll need to re-jig this to work properly with big/little because this is
only called once, but that's ok for now:
Acked-by: Will Deacon
Suzuki has a series reworking much of the cpufeatures code so that we can
do this properly for 4.17.
Will
On Mon, Jan 22, 2018 at 11:47:13AM +, Robin Murphy wrote:
> On 20/01/18 14:36, SF Markus Elfring wrote:
> >From: Markus Elfring
> >Date: Sat, 20 Jan 2018 15:30:17 +0100
> >
> >Omit extra messages for a memory allocation failure in these functions.
>
> Why?
Don't worry -- I was ignoring this
On Mon, Jan 22, 2018 at 11:51:34AM +, Ard Biesheuvel wrote:
> On 22 January 2018 at 11:41, Will Deacon wrote:
> > On Fri, Jan 19, 2018 at 04:22:48AM -0800, Jayachandran C wrote:
> >> Whitelist Broadcom Vulcan/Cavium ThunderX2 processors in
> >> unmap_kernel_a
ere are multiple matching criteria for a single
> capability. Changing the prototype is quite an invasive change and
> will be part of a future series. For now, add a comment to clarify
> what is expected.
>
> Suggested-by: Dave Martin
> Cc: Will Deacon
> Cc: Robin Murphy
&
Hi Ard,
On Thu, Jan 04, 2018 at 04:24:22PM +, Ard Biesheuvel wrote:
> On 4 January 2018 at 15:08, Will Deacon wrote:
> > Speculation attacks against the entry trampoline can potentially resteer
> > the speculative instruction stream through the indirect branch and into
> &
instruction loads an entry into
the stack, so that the predicted program flow of the subsequent RET
instruction is to a branch-to-self instruction which is finally resolved
as a branch to the kernel vectors with speculation suppressed.
Signed-off-by: Will Deacon
---
arch/arm64/kernel/entry.S | 10
RT so that it is on by default for the majority of users.
Signed-off-by: Will Deacon
---
arch/arm64/Kconfig | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3af1657fcac3..efaaa3a66b95 100644
--- a/arch/arm64/Kconfig
+++ b
Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they
will soon need MIDR matches for hardening the branch predictor.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cputype.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch
From: Marc Zyngier
Now that we have per-CPU vectors, let's plug then in the KVM/arm64 code.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 10 ++
arch/arm64/include/asm/kvm_mmu.h | 38 ++
arch/
against these attacks for
CPUs that are affected.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/Kconfig | 17 +
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/mmu.h | 37
arch/arm64/include/asm/sysreg.h | 1
entries from affecting other victim contexts.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/kernel/bpi.S| 24
arch/arm64/kernel/cpu_errata.c | 42 ++
2 files changed, 66 insertions(+)
diff --git a
ake PSCI_VERSION a fast path
Will Deacon (8):
arm64: use RET instruction for exiting the trampoline
arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry
arm64: Take into account ID_AA64PFR0_EL1.CSV3
arm64: cpufeature: Pass capability structure to ->enable callback
drivers/firmware:
From: Marc Zyngier
For those CPUs that require PSCI to perform a BP invalidation,
going all the way to the PSCI code for not much is a waste of
precious cycles. Let's terminate that call as early as possible.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/kv
For non-KASLR kernels where the KPTI behaviour has not been overridden
on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whether
or not we should unmap the kernel whilst running at EL0.
Reviewed-by: Suzuki K Poulose
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/sysreg.h
y: Lorenzo Pieralisi
Signed-off-by: Will Deacon
---
drivers/firmware/psci.c | 2 ++
include/linux/psci.h| 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index d687ca3d5049..8b25d31e8401 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmw
ed-off-by: Will Deacon
---
arch/arm64/kernel/cpufeature.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d723fc071f39..55712ab4e3bf 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpu
From: Marc Zyngier
We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/assembler.h | 13
Hi James,
Thanks for having a look.
On Mon, Jan 08, 2018 at 12:16:28PM +, James Morse wrote:
> On 05/01/18 13:12, Will Deacon wrote:
> > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
> > index 22168cd0dde7..5203b6040cb6 100644
> > --- a/arch/arm64/mm/fault.c
On Sat, Jan 06, 2018 at 01:13:23PM +, Ard Biesheuvel wrote:
> On 5 January 2018 at 13:12, Will Deacon wrote:
> > Speculation attacks against the entry trampoline can potentially resteer
> > the speculative instruction stream through the indirect branch and into
> > arb
On Mon, Jan 08, 2018 at 02:38:00PM +, Ard Biesheuvel wrote:
> On 8 January 2018 at 14:33, Will Deacon wrote:
> > On Sat, Jan 06, 2018 at 01:13:23PM +, Ard Biesheuvel wrote:
> >> On 5 January 2018 at 13:12, Will Deacon wrote:
> >> > Speculation attacks ag
On Mon, Jan 08, 2018 at 02:56:24PM +, Suzuki K Poulose wrote:
> On 08/01/18 12:48, Arnd Bergmann wrote:
> >The bitmap_from_u32array() interface got replaced in a global
> >change, but the arm_dsu_pmu driver adds another instance,
> >resulting in a build failure:
> >
> >drivers/perf/arm_dsu_pmu.
On Mon, Jan 08, 2018 at 06:32:25PM +0300, Yury Norov wrote:
> On Mon, Jan 08, 2018 at 03:15:47PM +0000, Will Deacon wrote:
> > On Mon, Jan 08, 2018 at 02:56:24PM +, Suzuki K Poulose wrote:
> > > On 08/01/18 12:48, Arnd Bergmann wrote:
> > > >The bitmap_from_u32arr
On Sun, Jan 07, 2018 at 10:53:36PM -0800, Jayachandran C wrote:
> Use PSCI based mitigation for speculative execution attacks targeting
> the branch predictor. The approach is similar to the one used for
> Cortex-A CPUs, but in case of ThunderX2 we add another SMC call to
> test if the firmware sup
On Sun, Jan 07, 2018 at 11:24:02PM -0800, Jayachandran C wrote:
> On Fri, Jan 05, 2018 at 01:12:33PM +0000, Will Deacon wrote:
> > For non-KASLR kernels where the KPTI behaviour has not been overridden
> > on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whethe
On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote:
> Falkor is susceptible to branch predictor aliasing and can
> theoretically be attacked by malicious code. This patch
> implements a mitigation for these attacks, preventing any
> malicious entries from affecting other victim cont
On Fri, Jan 26, 2018 at 12:05:42PM +0300, Yury Norov wrote:
> On Wed, Jan 24, 2018 at 10:22:13AM +0000, Will Deacon wrote:
> > On Wed, Jan 24, 2018 at 12:05:16PM +0300, Yury Norov wrote:
> > > This series adds API for 128-bit memory IO access and enables it for
> > >
INE...
> >> to be per-arch? I wonder how much would that "go through pt_regs" hurt
> >> on something like sparc...
> >
> > No, but I just talked to Will Deacon about register clearing on entry,
> > and so I suspect that arm64 might want something similar
On Wed, Jan 17, 2018 at 12:10:33PM +0800, Yisheng Xie wrote:
> Hi Will,
>
> On 2018/1/5 21:12, Will Deacon wrote:
> > diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
> > index 5f7097d0cd12..d99b36555a16 100644
> > --- a/arch/arm64/mm/context.c
> &
to dump the efi page
> tables results in a NULL pointer dereference in the ptdump code:
Acked-by: Will Deacon
Ard -- please can you pick this one up?
Cheers,
Will
Hi Dan, Linus,
On Thu, Jan 11, 2018 at 05:41:08PM -0800, Dan Williams wrote:
> On Thu, Jan 11, 2018 at 5:19 PM, Linus Torvalds
> wrote:
> > On Thu, Jan 11, 2018 at 4:46 PM, Dan Williams
> > wrote:
> >>
> >> This series incorporates Mark Rutland's latest ARM changes and adds
> >> the x86 specifi
Hi JC,
On Tue, Jan 16, 2018 at 03:45:54PM -0800, Jayachandran C wrote:
> On Tue, Jan 16, 2018 at 04:52:53PM -0500, Jon Masters wrote:
> > On 01/09/2018 07:47 AM, Jayachandran C wrote:
> >
> > > Use PSCI based mitigation for speculative execution attacks targeting
> > > the branch predictor. The a
On Wed, Jan 17, 2018 at 02:28:08PM +0100, Joerg Roedel wrote:
> On Wed, Jan 03, 2018 at 02:09:20PM +0800, Jeffy Chen wrote:
> > The for_each_matching_node_and_match() would return every matching
> > nodes including unavailable ones.
> >
> > It's pointless to init unavailable IOMMUs, so add a sanit
On Mon, Jan 08, 2018 at 09:19:43AM -0800, Jayachandran C wrote:
> On Mon, Jan 08, 2018 at 04:46:52PM +0000, Will Deacon wrote:
> > On Sun, Jan 07, 2018 at 10:53:36PM -0800, Jayachandran C wrote:
> > > Use PSCI based mitigation for speculative execution attacks targeting
> >
ed-off-by: Will Deacon
---
arch/arm64/kernel/cpufeature.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d723fc071f39..55712ab4e3bf 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpu
For non-KASLR kernels where the KPTI behaviour has not been overridden
on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whether
or not we should unmap the kernel whilst running at EL0.
Reviewed-by: Suzuki K Poulose
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/sysreg.h
RT so that it is on by default for the majority of users.
Signed-off-by: Will Deacon
---
arch/arm64/Kconfig | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3af1657fcac3..efaaa3a66b95 100644
--- a/arch/arm64/Kconfig
+++ b
instruction loads an entry into
the stack, so that the predicted program flow of the subsequent RET
instruction is to a branch-to-self instruction which is finally resolved
as a branch to the kernel vectors with speculation suppressed.
Signed-off-by: Will Deacon
---
arch/arm64/kernel/entry.S | 10
(3):
arm64: Move post_ttbr_update_workaround to C code
arm64: KVM: Use per-CPU vector when BP hardening is enabled
arm64: KVM: Make PSCI_VERSION a fast path
Shanker Donthineni (1):
arm64: Implement branch predictor hardening for Falkor
Will Deacon (8):
arm64: use RET instruction for exit
From: Marc Zyngier
Now that we have per-CPU vectors, let's plug then in the KVM/arm64 code.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 10 ++
arch/arm64/include/asm/kvm_mmu.h | 38 ++
arch/
From: Marc Zyngier
We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/assembler.h | 13
against these attacks for
CPUs that are affected.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/Kconfig | 17 +
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/mmu.h | 37
arch/arm64/include/asm/sysreg.h | 1
Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they
will soon need MIDR matches for hardening the branch predictor.
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cputype.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch
entries from affecting other victim contexts.
Co-developed-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/kernel/bpi.S| 24
arch/arm64/kernel/cpu_errata.c | 42 ++
2 files changed, 66 insertions(+)
diff --git a
From: Marc Zyngier
For those CPUs that require PSCI to perform a BP invalidation,
going all the way to the PSCI code for not much is a waste of
precious cycles. Let's terminate that call as early as possible.
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
---
arch/arm64/kv
From: Jayachandran C
Add the older Broadcom ID as well as the new Cavium ID for ThunderX2
CPUs.
Signed-off-by: Jayachandran C
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cputype.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64
: fix label name when !CONFIG_KVM]
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/kvm_asm.h | 2 ++
arch/arm64/kernel/bpi.S | 8 +++
arch/arm64/kernel/cpu_errata.c | 49 ++--
arch/arm64/kvm/hyp
y: Lorenzo Pieralisi
Signed-off-by: Will Deacon
---
drivers/firmware/psci.c | 2 ++
include/linux/psci.h| 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index d687ca3d5049..8b25d31e8401 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmw
On Mon, Jan 08, 2018 at 09:40:17AM -0800, Jayachandran C wrote:
> On Mon, Jan 08, 2018 at 09:20:09AM +, Marc Zyngier wrote:
> > On 08/01/18 07:24, Jayachandran C wrote:
> > > diff --git a/arch/arm64/kernel/cpufeature.c
> > > b/arch/arm64/kernel/cpufeature.c
> > > index 19ed09b..202b037 100644
On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote:
> On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote:
> > Falkor is susceptible to branch predictor aliasing and can
> > theoretically be attacked by malicious code. This patch
> > implements a
thineni wrote:
> > Hi Will,
> >
> > On 01/08/2018 12:44 PM, Will Deacon wrote:
> >> On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote:
> >>> On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote:
> >>>> Falkor is susc
On Mon, Jan 08, 2018 at 06:26:20PM -0800, Jayachandran C wrote:
> On Mon, Jan 08, 2018 at 05:23:41PM +0000, Will Deacon wrote:
> > On Mon, Jan 08, 2018 at 09:19:43AM -0800, Jayachandran C wrote:
> > > On Mon, Jan 08, 2018 at 04:46:52PM +, Will Deacon wrote:
> > > &
On Mon, Jan 08, 2018 at 08:06:27PM -0800, Jayachandran C wrote:
> On Mon, Jan 08, 2018 at 05:51:00PM +0000, Will Deacon wrote:
> > On Mon, Jan 08, 2018 at 09:40:17AM -0800, Jayachandran C wrote:
> > > On Mon, Jan 08, 2018 at 09:20:09AM +, Marc Zyngier wrote:
> &g
On Mon, Jan 08, 2018 at 03:31:08PM -0600, Shanker Donthineni wrote:
> Falkor is susceptible to branch predictor aliasing and can
> theoretically be attacked by malicious code. This patch
> implements a mitigation for these attacks, preventing any
> malicious entries from affecting other victim cont
Hi Shanker,
On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote:
> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
> the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
> of Silico
On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote:
> Hi Will,
>
> On 03/05/2018 09:56 AM, Will Deacon wrote:
> > Hi Shanker,
> >
> > On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote:
> >> The function SMCCC_ARCH_WORKAR
Hi Shanker,
On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote:
> The DCache clean & ICache invalidation requirements for instructions
> to be data coherence are discoverable through new fields in CTR_EL0.
> The following two control bits DIC and IDC were defined for this
> purpose
Hi Shanker,
On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote:
> On 03/06/2018 07:44 AM, Will Deacon wrote:
> > I think this is a slight asymmetry with the code for the I-side. On the
> > I-side, you hook into invalidate_icache_by_line, whereas on the D-side you
&g
On Mon, Mar 05, 2018 at 12:03:33PM -0600, Shanker Donthineni wrote:
> On 03/05/2018 11:15 AM, Will Deacon wrote:
> > On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote:
> >> On 03/05/2018 09:56 AM, Will Deacon wrote:
> >>> On Fri, Mar 02, 201
since any subsequent
masked comparison with i_dir_seq will fail anyway.
Cc: Peter Zijlstra
Cc: Al Viro
Reported-by: Naresh Madhusudana
Acked-by: Peter Zijlstra (Intel)
Reviewed-by: Matthew Wilcox
Signed-off-by: Will Deacon
---
fs/dcache.c | 8 +++-
1 file changed, 7 insertions(+), 1 d
merged if possible.
Thanks,
Will
--->8
Will Deacon (2):
fs: dcache: Avoid livelock between d_alloc_parallel and __d_add
fs: dcache: Use READ_ONCE when accessing i_dir_seq
fs/dcache.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
--
2.1.4
i_dir_seq is subject to concurrent modification by a cmpxchg or
store-release operation, so ensure that the relaxed access in
d_alloc_parallel uses READ_ONCE.
Reported-by: Peter Zijlstra
Signed-off-by: Will Deacon
---
fs/dcache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Tue, Mar 06, 2018 at 01:33:00PM -0600, Shanker Donthineni wrote:
> > I also confirmed with Thomas Speier, we can skip __flush_icache_all() if
> > DIC=1.
Thanks,
> Planning to patch __flush_icache_all() itself instead of changing the
> callers. This
> way we can avoid "ic ialluis" completely.
On Mon, Mar 26, 2018 at 12:37:21PM +0200, Andrea Parri wrote:
> Commit 38b850a73034f ("arm64: spinlock: order spin_{is_locked,unlock_wait}
> against local locks") added an smp_mb() to arch_spin_is_locked(), in order
> "to ensure that the lock value is always loaded after any other locks have
> been
Hi Suzuki,
On Tue, Mar 13, 2018 at 11:50:58AM +, Suzuki K Poulose wrote:
> This series reworks the arm64 CPU capabilities handling (which
> manages the system features and errata). The current infrastructure
> doesn't allow fine control for handling different features or errata.
> There is one
On Sun, Mar 25, 2018 at 08:50:04PM +0300, Yury Norov wrote:
> kick_all_cpus_sync() forces all CPUs to sync caches by sending broadcast IPI.
> If CPU is in extended quiescent state (idle task or nohz_full userspace), this
> work may be done at the exit of this state. Delaying synchronization helps t
Cc: Arnd Bergmann
Cc: Jason Gunthorpe
Cc: "Paul E. McKenney"
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Jonathan Corbet
Reported-by: Sinan Kaya
Signed-off-by: Will Deacon
---
Documentation/memory-barriers.txt | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
di
On Thu, Apr 05, 2018 at 07:19:12PM +0200, Peter Zijlstra wrote:
> On Thu, Apr 05, 2018 at 05:59:00PM +0100, Will Deacon wrote:
> > +
> > + /* In the PV case we might already have _Q_LOCKED_VAL set */
> > + if ((val & _Q_TAIL_MASK) == tail) {
> >
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