On Wed, Jan 09, 2013 at 02:58:16AM +, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the tegra tree got a conflict in
> arch/arm/mach-tegra/headsmp.S between commit bc4f1bdabc89 ("ARM:
> coresight: common definition for (OS) Lock Access Register key value")
> from the arm-pe
On Tue, Jul 19, 2016 at 01:22:09PM -0700, Duc Dang wrote:
> On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang wrote:
> > On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
> >> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
> >> > On Mon, Jul 11, 2016 at 12:0
On Fri, Jul 15, 2016 at 11:46:20AM +0900, Kwangwoo Lee wrote:
> Ensure D-cache lines are cleaned to the PoC(Point of Coherency).
>
> This function is called by arch_wb_cache_pmem() to clean the cache lines
> and remain the data in cache for the next access.
>
> Signed-off-by: Kwangwoo Lee
> ---
ess of a queue rwlock
> + * @lock : Pointer to queue rwlock structure
> + * Return: the write byte address of a queue rwlock
> + */
> +static inline u8 *__qrwlock_write_byte(struct qrwlock *lock)
> +{
> + return (u8 *)lock + 3 * IS_BUILTIN(CONFIG_CPU_BIG_ENDIAN);
> +}
Might be worth a comment here, saying that IS_BUILTIN expands to 1 or 0.
Either way, the patch looks correct to me:
Acked-by: Will Deacon
Will
erted over to the new attribute.
>
> Jordan and Jeremy can provide more info on the use case if needed, but the
> high level is that it's a security feature to prevent attacks such as [1].
This all looks good to me:
Acked-by: Will Deacon
It looks pretty fiddly to merge, however. How are you planning to get
this upstream?
Will
On Mon, Sep 19, 2016 at 03:07:19PM +0100, Mark Rutland wrote:
> [adding LAKML, arm64 maintainers]
I've also looped in Euler ThunderTown, since (a) he's at Huawei and is
assumedly testing this stuff and (b) he has a fairly big NUMA patch
series doing the rounds (some of which I've queued).
> On Mo
Hi Yisheng,
On Tue, Sep 20, 2016 at 11:29:24AM +0800, Yisheng Xie wrote:
> On 2016/9/19 22:07, Mark Rutland wrote:
> > On Mon, Sep 19, 2016 at 09:05:26PM +0800, Yisheng Xie wrote:
> > Can you modify the warning in cpumask.h to dump the bad CPU number? That
> > would make it fairly clear if that's
c: Matt Fleming
> Signed-off-by: Ard Biesheuvel
> ---
> MAINTAINERS | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
I don't know if "congratulations" is the right word to use, but:
Acked-by: Will Deacon
Will
atalin Marinas
> Cc: Will Deacon
> Cc: Russell King
> Signed-off-by: Ard Biesheuvel
> ---
> MAINTAINERS | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 224518556a84..cc8b36699f94 100644
> --- a/MAIN
On Wed, Sep 21, 2016 at 03:25:04PM -0700, Laura Abbott wrote:
>
> virt_addr_valid is supposed to return true if and only if virt_to_page
> returns a valid page structure. The current macro does math on whatever
> address is given and passes that to pfn_valid to verify. vmalloc and
> module address
On Sat, Jun 18, 2016 at 04:46:20PM +0800, Boqun Feng wrote:
> On Fri, Jun 17, 2016 at 02:17:27PM -0400, Waiman Long wrote:
> > keep the xchg() function as it is or use smp_store_release(&next->locked,
> > 1). So which one is a better alternative for ARM or PPC?
> >
>
> For PPC, I think xchg_relea
On Tue, Jun 21, 2016 at 11:32:17AM +0100, Catalin Marinas wrote:
> On Tue, Jun 21, 2016 at 10:44:00AM +0900, Masahiro Yamada wrote:
> > I fixed boot image dependencies for arch/arm in commit 3939f3345050
> > ("ARM: 8418/1: add boot image dependencies to not generate invalid
> > images").
> >
> > I
and commit log ]
> Signed-off-by: Punit Agrawal
> Reviewed-by: Will Deacon
> ---
> arch/arm64/include/asm/tlbflush.h | 34 ++
> 1 file changed, 26 insertions(+), 8 deletions(-)
Given that this series seems to have stalled, I'm inclined to pick th
On Tue, Jul 26, 2016 at 09:11:49AM -0500, Timur Tabi wrote:
> Will Deacon wrote:
> >The kernel really needs to support both of those platforms :/
> >
> >For the memory-mapped counter registers, the architecture says:
> >
> > `If the implementation supports
hat we take all of this through your tree since it's touching multiple
> subsystems [3]. Can you please take a look? Thanks!
You forgot to add my ack to the patches, so if you need it again:
Acked-by: Will Deacon
Will
d, 0) ? : mm->brk;
> + return randomize_addr(mm->brk, 0x4000);
Looks fine to me, once the core code has settled down:
Acked-by: Will Deacon
Will
On Tue, Sep 06, 2016 at 01:17:53PM +0200, Peter Zijlstra wrote:
> On Mon, Sep 05, 2016 at 11:10:22AM +0100, Will Deacon wrote:
>
> > > The second issue I wondered about is spinlock transitivity. All except
> > > powerpc have RCsc locks, and since Power already does a ful
On Mon, Sep 05, 2016 at 08:57:19PM +0200, Manfred Spraul wrote:
> On 09/02/2016 09:22 PM, Peter Zijlstra wrote:
> Anyone around with a ppc or arm? How slow is the loop of the
> spin_unlock_wait() calls?
> Single CPU is sufficient.
>
> Question 1: How large is the difference between:
> #./sem-scale
On Mon, Sep 05, 2016 at 06:25:47PM +0100, Catalin Marinas wrote:
> The static key API is currently designed around single variable
> definitions. There are cases where an array of static keys is desirable,
> so extend the API to allow this rather than using the internal static
> key implementation
On Tue, Sep 06, 2016 at 07:04:37PM +0200, Sebastian Andrzej Siewior wrote:
> Install the callbacks via the state machine.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Sebastian Andrzej Siewior
> ---
> arch/ar
e pre-processor is
> used to handle these two cases with different assembly blocks.
>
> The existing tlbflush.h code is moved over to use the helper.
>
> Signed-off-by: Mark Rutland
> Cc: Catalin Marinas
> Cc: Marc Zyngier
> Cc: Will Deacon
> [ rename helper to _
. Since both these traps share the EC, refactor
> the handler a little bit to make it a bit more reader friendly.
>
> Cc: Andre Przywara
> Cc: Mark Rutland
> Cc: Will Deacon
> Cc: Catalin Marinas
> Signed-off-by: Suzuki K Poulose
> ---
On Wed, Sep 07, 2016 at 03:23:54PM +0200, Peter Zijlstra wrote:
> On Wed, Sep 07, 2016 at 10:17:26PM +1000, Nicholas Piggin wrote:
> > It seems okay, but why not make it a special sched-only function name
> > to prevent it being used in generic code?
> >
> > I would not mind seeing responsibility
On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote:
> While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
> stumbled upon this line:
>
> # r10 is the current cache level
> 127: addr2, r10, r10, lsr #1 @ work out 3x current cache level
>
> If we want r2 to be
Hi Arnd,
On Thu, Sep 01, 2016 at 09:33:38AM +0200, Arnd Bergmann wrote:
> On Thursday, September 1, 2016 12:51:09 PM CEST Leo Yan wrote:
> > Enable common modules for power management; one is to enable
> > CPUFREQ_DT driver; the driver is used by many platforms by passing OPP
> > table from device
On Thu, Sep 08, 2016 at 11:21:45AM +0100, Mark Rutland wrote:
> I'm trying to make the perf tool play better with PMUs in heterogeneous
> systems
> (e.g. big.LITTLE), where there are several logical PMUs, each covering a
> subset
> of CPUs.
>
> Currently perf-record doesn't work for these PMUs,
On Thu, Sep 01, 2016 at 02:54:51PM +0800, Zhen Lei wrote:
> v7 -> v8:
> Updated patches according to Will Deacon's review comments, thanks.
>
> The changed patches is: 3, 5, 8, 9, 10, 11, 12, 13, 15
> Patch 3 requires an ack from Rob Herring.
> Patch 10 requires an ack from linux-mm.
>
> Hi, Will
On Wed, Sep 07, 2016 at 12:30:19PM +0300, Aleksey Makarov wrote:
>
> On 09/05/2016 03:36 PM, Aleksey Makarov wrote:
> > SBBR mentions SPCR as a mandatory ACPI table. So enable it for ARM64
> >
> > Earlycon should be set up as early as possible. ACPI boot tables are
> > mapped in arch/arm64/kern
the DT/ACPI decision is done. Initialize DT earlycon
> > if ACPI is disabled.
>
> Hi Will, Catalin,
>
> Can you review this patch and consider ACKing it please?
Since the ACPI folks seem happy with the series, then:
Acked-by: Will Deacon
for this patch.
Will
On Thu, Sep 08, 2016 at 08:16:57PM +0200, Peter Zijlstra wrote:
> On Thu, Sep 08, 2016 at 01:25:02PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Thu, Sep 08, 2016 at 11:21:45AM +0100, Mark Rutland escreveu:
> > > Hi,
> > >
> > > I'm trying to make the perf tool play better with PMUs in heterogen
> Signed-off-by: Yonghui Yang
> Signed-off-by: Chunyan Zhang
> ---
> arch/arm64/include/asm/percpu.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Looks good to me:
Acked-by: Will Deacon
However, don't you need to make a similar change to asm-generic/percpu.h
for other architectures (e.g. arch/arm/)?
Will
userspace with the information
> it needs, this patch exposes a differently-named file (cpus) under
> sysfs. New tools can look for this and operate correctly, while older
> tools will not be adversely affected by its presence.
>
> Signed-off-by: Mark Rutland
> Cc: Will Deacon
ove backends over to using these, before adding
> common fields.
>
> Signed-off-by: Mark Rutland
> Cc: Will Deacon
> ---
> drivers/perf/arm_pmu.c | 3 +++
> include/linux/perf/arm_pmu.h | 9 -
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
>
Hi Laura,
On Mon, Sep 12, 2016 at 02:32:56PM -0700, Laura Abbott wrote:
>
> arm64 may need to guarantee the caches are synced. Implement versions of
> the kernel_force_cache API to allow this.
>
> Signed-off-by: Laura Abbott
> ---
> v3: Switch to calling cache operations directly instead of rel
On Tue, Sep 13, 2016 at 08:02:20AM -0700, Laura Abbott wrote:
> On 09/13/2016 02:19 AM, Will Deacon wrote:
> >On Mon, Sep 12, 2016 at 02:32:56PM -0700, Laura Abbott wrote:
> >>
> >>arm64 may need to guarantee the caches are synced. Implement versions of
> >>the
Hi Akashi,
On Tue, Apr 21, 2015 at 02:13:13AM +0100, AKASHI Takahiro wrote:
> Could you please review my patch below?
> See also arm64 maintainer's comment:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313712.html
-ETIMEDOUT waiting for the kdgb folk to comment. Ppeople ha
On Thu, Sep 15, 2016 at 09:45:09PM +0530, Pratyush Anand wrote:
> On Wed, Aug 24, 2016 at 3:36 PM, Pratyush Anand wrote:
> > On 23/08/2016:04:33:08 PM, Sandeepa Prabhu wrote:
> >> Thanks for the fix, feel free to add my ACK as well. Has it been tested on
> >> guest kernel?
> >
> > have not tested
On Tue, Aug 30, 2016 at 03:16:42PM -0500, Andy Gross wrote:
> On Tue, Aug 23, 2016 at 11:38:41AM +0100, Lorenzo Pieralisi wrote:
> > On Mon, Aug 22, 2016 at 05:38:31PM -0700, Stephen Boyd wrote:
> >
> > [...]
> >
> > > This all comes about because the firmware generates a session id
> > > for the
On Tue, Aug 30, 2016 at 06:32:25PM +0100, Mark Rutland wrote:
> On Fri, Aug 26, 2016 at 10:48:00AM +0100, Will Deacon wrote:
> > On Fri, Aug 19, 2016 at 03:25:14PM +0100, Mark Rutland wrote:
> > > On Thu, Aug 18, 2016 at 01:24:38PM -0700, Yabin Cui wrote:
> > > >
On Wed, Aug 31, 2016 at 05:40:49PM +0200, Peter Zijlstra wrote:
> On Wed, Aug 31, 2016 at 06:59:07AM +0200, Manfred Spraul wrote:
>
> > The barrier must ensure that taking the spinlock (as observed by another cpu
> > with spin_unlock_wait()) and a following read are ordered.
> >
> > start conditi
On Thu, Sep 01, 2016 at 01:04:26PM +0200, Manfred Spraul wrote:
> If I understand it right, the rules are:
> 1. spin_unlock_wait() must behave like spin_lock();spin_unlock();
> 2. spin_is_locked() must behave like spin_trylock() ? spin_unlock(),TRUE :
> FALSE
I don't think spin_is_locked is as str
On Fri, Aug 26, 2016 at 10:37:08AM +0100, Punit Agrawal wrote:
> > Will Deacon writes:
> >> The easiest thing to do is just TLBI VMALLE1IS for all trapped operations,
> >> but you might want to see how that performs.
> >
> > That sounds reasonable for correct
On Thu, Sep 01, 2016 at 05:27:52PM +0200, Manfred Spraul wrote:
> Since spin_unlock_wait() is defined as equivalent to spin_lock();
> spin_unlock(), the memory barrier before spin_unlock_wait() is
> also not required.
>
> Not for stable!
>
> Signed-off-by: Manfred Spraul
> Cc: Pablo Neira Ayuso
On Fri, Sep 02, 2016 at 06:18:39PM +0800, Xie Yisheng wrote:
> From: Yisheng Xie
>
> There's an early memmap leak in efi_init error path, fix it.
>
> Signed-off-by: Yisheng Xie
> ---
> drivers/firmware/efi/arm-init.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Adding linux-efi,
Hi Linus,
Please pull these arm64 fixes for -rc1. The branch is based on the
for-next/core tag you pulled from Catalin last week. He's on holiday
once again, so I'm handling the fixes until he's back.
Details in the tag.
Cheers,
Will
--->8
The following changes since commit fd6380b75065fd2ff5
Hi Alex,
On Tue, Aug 23, 2016 at 08:08:23PM +0300, Alexander Shishkin wrote:
> Will Deacon writes:
> > On Fri, Aug 12, 2016 at 08:54:49PM +0300, Alexander Shishkin wrote:
> >> Yes, I tracked to a race between unmapping and set_output, trying to
> >> come up with a go
On Tue, Aug 23, 2016 at 02:46:18PM +0200, Peter Zijlstra wrote:
> There's a number of iffy in mutex because mutex::count and
> mutex::owner are two different fields; this too is the reason
> MUTEX_SPIN_ON_OWNER and DEBUG_MUTEX are mutually exclusive.
>
> Cure this by folding them into a single ato
On Wed, Aug 24, 2016 at 05:47:11PM +0200, Oleg Nesterov wrote:
> On 08/24, Pratyush Anand wrote:
> >
> > > I don't think we want user_{enable,disable{_single_step in the long term,
> > > please look at 9bd1190a11c9d2 "uprobes/x86: Do not (ab)use TIF_SINGLESTEP
> > > /user_*_single_step() for single
On Wed, Aug 24, 2016 at 06:52:44PM +0200, Peter Zijlstra wrote:
> On Wed, Aug 24, 2016 at 05:34:12PM +0200, Peter Zijlstra wrote:
> > On Wed, Aug 24, 2016 at 10:56:59AM +0100, Will Deacon wrote:
> > > > + owner = atomic_long_read(&lock->
chg_inatomic() is able to return the old value
> without a write (if it differs from "oldval") but it doesn't look like
> such value could leak to user space.
If this was an issue, couldn't we add a dummy LDTR before the LDXR, and
have the fixup handler return -EFAULT?
Either way, this series looks technically fine to me:
Reviewed-by: Will Deacon
but it would be good for some security-focussed person (Hi, Kees!) to
comment on whether or not this is useful, given the caveats you've
described. If it is, I can queue it for 4.9.
Will
On Wed, Aug 17, 2016 at 01:50:25PM +0100, James Morse wrote:
> disable_nonboot_cpus() assumes that the lowest numbered online CPU is
> the boot CPU, and that this is the correct CPU to run any power
> management code on.
>
> On x86 this is always correct, as CPU0 cannot (easily) by taken offline.
Mark,
On Fri, Aug 19, 2016 at 03:25:14PM +0100, Mark Rutland wrote:
> On Thu, Aug 18, 2016 at 01:24:38PM -0700, Yabin Cui wrote:
> >If the cpu pmu is using a percpu irq:
> >
> >1. When a cpu is down, we should disable pmu irq on
On Fri, Aug 26, 2016 at 12:09:38PM +0200, Thomas Gleixner wrote:
> On Fri, 26 Aug 2016, Will Deacon wrote:
> > On Wed, Aug 17, 2016 at 01:50:25PM +0100, James Morse wrote:
> > > disable_nonboot_cpus() assumes that the lowest numbered online CPU is
> > > the boot CPU, a
On Mon, Aug 22, 2016 at 09:20:02PM +0800, Xie Yisheng wrote:
> Arm64 supports different size of gigantic page which can be seen from:
> commit 084bd29810a5 ("ARM64: mm: HugeTLB support.")
> commit 66b3923a1a0f ("arm64: hugetlb: add support for PTE contiguous bit")
>
> So I tried to use this functi
On Wed, Aug 24, 2016 at 03:44:42PM +0800, Zhen Lei wrote:
> Use the same tactic to cpu and numa-distance nodes.
>
> Signed-off-by: Zhen Lei
> ---
> drivers/of/of_numa.c | 5 +
> 1 file changed, 5 insertions(+)
The subject has arm64/numa, but this is clearly core OF code and
requires an ack
On Wed, Aug 24, 2016 at 03:44:44PM +0800, Zhen Lei wrote:
> numa_init(of_numa_init) may returned error because of numa configuration
> error. So "No NUMA configuration found" is inaccurate. In fact, specific
> configuration error information should be immediately printed by the
> testing branch.
>
On Wed, Aug 24, 2016 at 03:44:47PM +0800, Zhen Lei wrote:
> From: Kefeng Wang
>
> Use pr_fmt to prefix kernel output, and remove duplicated msg
> of NUMA turned off.
>
> Signed-off-by: Kefeng Wang
> ---
> arch/arm64/mm/numa.c | 40
> 1 file changed, 20
On Wed, Aug 24, 2016 at 03:44:48PM +0800, Zhen Lei wrote:
> To make each percpu area allocated from its local numa node. Without this
> patch, all percpu areas will be allocated from the node which cpu0 belongs
> to.
>
> Signed-off-by: Zhen Lei
> ---
> arch/arm64/Kconfig | 8
> arch/
On Wed, Aug 24, 2016 at 03:44:49PM +0800, Zhen Lei wrote:
> 1. MAX_NUMNODES is base on CONFIG_NODES_SHIFT, the default value of the
>latter is very small now.
> 2. Suppose the default value of MAX_NUMNODES is enlarged to 64, so the
>size of numa_distance is 4K, it's still acceptable if run
On Wed, Aug 24, 2016 at 03:44:53PM +0800, Zhen Lei wrote:
> Update documentation. This limit is unneccessary.
>
> Signed-off-by: Zhen Lei
> Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/numa.txt | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/Documentation/devicetree/
On Wed, Aug 24, 2016 at 03:44:50PM +0800, Zhen Lei wrote:
> Some numa nodes may have no memory. For example:
> 1. cpu0 on node0
> 2. cpu1 on node1
> 3. device0 access the momory from node0 and node1 take the same time.
>
> So, we can not simply classify device0 to node0 or node1, but we can
> defi
On Wed, Aug 24, 2016 at 03:44:51PM +0800, Zhen Lei wrote:
> 1. Currently only cpu0 set on cpu_possible_mask and percpu areas have not
>been initialized.
> 2. No reason to limit cpu0 must belongs to node0.
Whilst I suspect you're using enumerated lists in order to try to make
things clearer, I'
On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote:
> On 26/08/16 14:04, Suzuki K Poulose wrote:
> >On 26/08/16 12:03, Ard Biesheuvel wrote:
> >>IMO, this is a pattern that we should avoid: you are introducing one
> >>instance now, which will make it hard to say no to the next one in
On Wed, Aug 16, 2017 at 11:13:03AM +0200, Thomas Gleixner wrote:
> On Tue, 15 Aug 2017, Theodore Ts'o wrote:
> > If we really want to do this, I'd much rather *not* have code calling
> > tsc_early_random(). We're better off having the code call
> > get_random_bytes() and/or get_random_u32(), and h
On Wed, Aug 16, 2017 at 10:53:38AM +0100, Mark Rutland wrote:
> On Wed, Aug 16, 2017 at 10:31:12AM +0100, Ard Biesheuvel wrote:
> > (+ Mark, Will)
> >
> > On 15 August 2017 at 22:46, Andy Lutomirski wrote:
> > > On Tue, Aug 15, 2017 at 12:18 PM, Sai Praneeth Prakhya
> > > wrote:
> > >> +/*
> > >
avoid
using the local_* API where it isn't needed.
Cc: Mark Rutland
Cc: Alexander Shishkin
Cc: Peter Zijlstra
Signed-off-by: Will Deacon
---
kernel/events/internal.h| 4 ++--
kernel/events/ring_buffer.c | 31 ++-
2 files changed, 16 insertions(+), 19 dele
eported-by: Mark Rutland
Signed-off-by: Will Deacon
---
kernel/events/internal.h| 2 +-
kernel/events/ring_buffer.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/kernel/events/internal.h b/kernel/events/internal.h
index 2941b868353c..5377c591c57a 100644
--- a/kerne
On Tue, Aug 15, 2017 at 11:35:41PM +0100, Mark Rutland wrote:
> On Wed, Aug 16, 2017 at 09:14:41AM -0700, Andy Lutomirski wrote:
> > On Wed, Aug 16, 2017 at 5:57 AM, Matt Fleming
> > wrote:
> > > On Wed, 16 Aug, at 12:03:22PM, Mark Rutland wrote:
> > >>
> > >> I'd expect we'd abort at a higher le
Thunder, Nate, Robin,
On Mon, Jun 26, 2017 at 09:38:45PM +0800, Zhen Lei wrote:
> I described the optimization more detail in patch 1 and 2, and patch 3-5 are
> the implementation on arm-smmu/arm-smmu-v3 of patch 2.
>
> Patch 1 is v2. In v1, I directly replaced writel with writel_relaxed in
> que
mu_map_sg(), and iommu_unmap()
> functions. They will be used by current users of the
> IOMMU-API, before they are optimized to the unsynchronized
> versions.
>
> Cc: Alex Williamson
> Cc: Will Deacon
> Cc: Robin Murphy
> Signed-off-by: Joerg Roedel
> ---
> driv
On Fri, Aug 11, 2017 at 03:45:28PM +0200, Eric Auger wrote:
> When running a virtual SMMU on a guest we sometimes need to trap
> all changes to the translation structures. This is especially useful
> to integrate with VFIO. This patch adds a new option that forces
> the IO_PGTABLE_QUIRK_TLBI_ON_MAP
Hi Joerg,
On Thu, Aug 17, 2017 at 06:50:40PM +0200, Joerg Roedel wrote:
> On Thu, Aug 17, 2017 at 05:32:35PM +0100, Will Deacon wrote:
> > I really like the idea of this, but I have a couple of questions and
> > comments below.
>
> Great, this together with the common iova
On Fri, Aug 18, 2017 at 11:19:00AM +0800, Leizhen (ThunderTown) wrote:
>
>
> On 2017/8/17 22:36, Will Deacon wrote:
> > Thunder, Nate, Robin,
> >
> > On Mon, Jun 26, 2017 at 09:38:45PM +0800, Zhen Lei wrote:
> >> I described the optimization more detail in pa
On Mon, Jun 19, 2017 at 12:41:38PM -0600, Baicar, Tyler wrote:
> On 6/19/2017 4:22 AM, Will Deacon wrote:
> >On Mon, Jun 19, 2017 at 01:06:30PM +0300, Andy Shevchenko wrote:
> >>On Mon, 2017-06-19 at 10:19 +0100, Will Deacon wrote:
> >>>Hi Stephen, Christoph, Tyler,
&
Hi Robert,
On Tue, Jun 20, 2017 at 08:34:39AM +0200, Robert Richter wrote:
> On 07.06.17 12:50:12, Will Deacon wrote:
>
> > Thanks, I've pushed this out as:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
> > for-next/ras-apei
> >
On Tue, Jun 20, 2017 at 02:54:15PM +0100, Marc Zyngier wrote:
> On 20/06/17 14:30, Stefan Traby wrote:
> > This is really trivial; there is a dup
> > (1 << 16) in the code
> >
> > Signed-off-by: Stefan Traby
> > ---
> > arch/arm64/include/asm/sysreg.h | 4 ++--
> > 1 file changed, 2 insertions(+
On Tue, Jun 20, 2017 at 03:05:39PM +0100, Will Deacon wrote:
> On Tue, Jun 20, 2017 at 02:54:15PM +0100, Marc Zyngier wrote:
> > On 20/06/17 14:30, Stefan Traby wrote:
> > > This is really trivial; there is a dup
> > > (1 << 16) in the code
> &g
On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote:
> From: Geetha Sowjanya
>
> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
> lines for gerror, eventq and cmdq-sync.
>
> SHARED_IRQ option is set as a errata workaround, which allows to share the irq
> l
On Tue, Jun 20, 2017 at 07:47:37PM +0530, Geetha sowjanya wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 implementation doesn't support second page in SMMU
> register space. Hence, resource size is set as 64k for this model.
>
> Signed-off-by: Linu Cherian
> Signed-off-by: Geetha Sowjanya
>
On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option is enabled as an errata workaround.
> This option when turned on, replaces all page 1 offsets used for
On Tue, Jun 20, 2017 at 12:13:13PM -0600, Baicar, Tyler wrote:
> I have sent you the rebased patches. I took Christoph's uuid-types tree and
> added this patch onto it:
>
> 7bf130e4a065 ("ACPI/APEI: Handle GSIV and GPIO notification types")
>
> And then added my patches onto that. This will hopef
On Wed, Jun 21, 2017 at 09:28:23AM +0800, Leizhen (ThunderTown) wrote:
> On 2017/6/20 19:35, Robin Murphy wrote:
> > On 20/06/17 12:04, Zhen Lei wrote:
> >> This function is protected by spinlock, and the latter will do memory
> >> barrier implicitly. So that we can safely use writel_relaxed. In fa
On Tue, Jun 20, 2017 at 01:31:14PM -0700, Thomas Garnier wrote:
> On Tue, Jun 20, 2017 at 1:18 PM, Kees Cook wrote:
> > On Wed, Jun 14, 2017 at 6:12 PM, Thomas Garnier wrote:
> >> diff --git a/arch/arm/kernel/entry-common.S
> >> b/arch/arm/kernel/entry-common.S
> >> index eb5cd77bf1d8..e33c32d56
Hi Geetha,
On Wed, Jun 21, 2017 at 12:09:45PM +0530, Geetha Akula wrote:
> On Tue, Jun 20, 2017 at 11:30 PM, Will Deacon wrote:
> > On Tue, Jun 20, 2017 at 07:47:39PM +0530, Geetha sowjanya wrote:
> >> From: Geetha Sowjanya
> >>
> >> Cavium ThunderX2 SMMU
Hi Tyler,
On Tue, Jun 20, 2017 at 12:26:01PM -0600, Baicar, Tyler wrote:
> On 6/20/2017 12:20 PM, Will Deacon wrote:
> >On Tue, Jun 20, 2017 at 12:13:13PM -0600, Baicar, Tyler wrote:
> >>I have sent you the rebased patches. I took Christoph's uuid-types tree and
>
> Cc: Thomas Gleixner
> Cc: Ingo Molnar
> Cc: Miroslav Lichvar
> Cc: Richard Cochran
> Cc: Prarit Bhargava
> Cc: Stephen Boyd
> Cc: Kevin Brodsky
> Cc: Will Deacon
> Cc: Daniel Mentz
> Tested-by: Daniel Mentz
> Signed-off-by: John Stultz
> ---
> arc
On Thu, Jun 15, 2017 at 10:57:35AM -0500, Kim Phillips wrote:
> On Mon, 12 Jun 2017 11:20:48 -0500
> Kim Phillips wrote:
>
> > On Mon, 12 Jun 2017 12:08:23 +0100
> > Mark Rutland wrote:
> >
> > > On Mon, Jun 05, 2017 at 04:22:52PM +0100, Will Deacon wrote:
Hi Mark,
Thanks for the extensive review. Replies inline.
On Thu, Jun 15, 2017 at 03:57:29PM +0100, Mark Rutland wrote:
> On Mon, Jun 05, 2017 at 04:22:56PM +0100, Will Deacon wrote:
> > +/* ID registers */
> > +#define PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
>
>
On Mon, Oct 16, 2017 at 12:27:17PM +0800, chengjian (D) wrote:
> Hi
> I write demo use ptrace/SINGLESTEP to count the number of instructions
> executed by the process
> The parent process fork+exec a child process, and trace(SINGLESTEP) it,
>
> It works fine under the x86_64 architecture but has a
On Tue, Oct 17, 2017 at 10:58:53AM +0800, Tan Xiaojun wrote:
> I'm not sure if this is the problem on arm64 numa. What do you think ?
> By the way, this testcase can be successful in any case on x86.
To be honest, this isn't a particularly helpful bug report. I appreciate
that a test is reporting
On Tue, Oct 17, 2017 at 10:04:00AM +0800, chengjian (D) wrote:
> On 2017/10/16 23:30, Will Deacon wrote:
> >Can you jump the PC once the child appears to be "stuck"?
> >
> >IIRC, GDB has special heuristics to step through LDXR/STXR critical
> >sections.
&g
this (and other similar issues) by opting out of all compiler
> instrumentation. We can opt-in to specific instrumentation in future if
> we want to.
>
> Signed-off-by: Mark Rutland
> Cc: Catalin Marinas
> Cc: Will Deacon
> ---
> arch/arm64/lib/Makefile | 1 +
> 1
for certain files or directories.
> This can also be overridden on a per-file or per-directory basis, to
> allow opting in to some instrumentation.
>
> Signed-off-by: Mark Rutland
> Cc: Andrey Konovalov
> Cc: Andrey Ryabinin
> Cc: Dmitry Vyukov
> Cc: Masahiro Yamad
On Tue, Oct 17, 2017 at 11:54:54AM +0100, Mark Rutland wrote:
> On Tue, Oct 17, 2017 at 11:03:15AM +0100, Will Deacon wrote:
> > On Mon, Oct 16, 2017 at 02:24:38PM +0100, Mark Rutland wrote:
> > > While we build the LL/SC atomics as a C object file, this does not
> > >
363 ("mm: convert page_mkclean_one() to use
page_vma_mapped_walk()")
Cc: # 4.13
[will: backport to 4.13.y]
Signed-off-by: Will Deacon
---
mm/page_vma_mapped.c | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/mm/page_vma_mapped.c b/mm/page_
On Tue, Oct 17, 2017 at 12:10:33PM +0100, Mark Rutland wrote:
> On Tue, Oct 17, 2017 at 11:58:58AM +0100, Will Deacon wrote:
> > On Tue, Oct 17, 2017 at 11:54:54AM +0100, Mark Rutland wrote:
> > > On Tue, Oct 17, 2017 at 11:03:15AM +0100, Will Deacon wrote:
> > > >
on Cavium's patch-v9 (Add support for
> ThunderX2 pmu events using json files), Link:
> https://www.spinics.net/lists/arm-kernel/msg611895.html
>
> Signed-off-by: Shaokun Zhang
> Cc: Peter Zijlstra
> Cc: Ingo Molnar
> Cc: Arnaldo Carvalho de Melo
> Cc: Alexander Shis
On Wed, Aug 30, 2017 at 07:46:33PM +0800, Miles Chen wrote:
> After the kernel ASLR, the module virtual address is moved to
> [module_alloc_base, module_alloc_base + MODULES_VSIZE).
> However, the MODULES_VADDR is still defined as a constant and functions
> like is_vmalloc_or_module_addr() or dump
in Marinas
> > Cc: Leo Yan
> > Cc: Will Deacon
> > Cc: Mark Rutland
> > Signed-off-by: Suzuki K Poulose
>
> This looks sane to me, but it will need an ack from Will or Catalin.
>
> FWIW:
>
> Acked-by: Mark Rutland
>
> Thanks,
> Mark.
Hi Paul,
It looks like the breakage below is from a version of the patches that
existed before I split compiler.h in half. What's the plan with these
patches? I'd be happier for you to take them, but you'll want to take the
most recent version in that case.
Cheers,
Will
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