On Fri, May 15, 2015 at 12:00:02AM +0100, Laurent Pinchart wrote:
> The arch_setup_dma_ops() function is in charge of setting dma_ops with a
> call to set_dma_ops(). set_dma_ops() is also called from
>
> - highbank and mvebu bus notifiers
> - dmabounce (to be replaced with swiotlb)
> - arm_iommu_a
at
> situation will change when moving DMA configuration to device probe
> time.
>
> Signed-off-by: Laurent Pinchart
> ---
> drivers/of/address.c | 20 ++--
> drivers/of/device.c | 15 ---
> 2 files changed, 18 insertions(+), 17 deletions(-)
Look
On Thu, May 28, 2015 at 07:08:42AM +0100, Li Bin wrote:
> On 2015/4/24 17:27, Jiri Kosina wrote:
> > On Fri, 24 Apr 2015, AKASHI Takahiro wrote:
> >
> >> This patchset enables livepatch support on arm64.
> >>
> >> Livepatch was merged in v4.0, and allows replacying a function dynamically
> >> base
ed, 15 insertions(+), 5 deletions(-)
Acked-by: Will Deacon
Cheers,
Will
> diff --git a/drivers/of/device.c b/drivers/of/device.c
> index 530aa1ed3e1b..f1b84f464fe1 100644
> --- a/drivers/of/device.c
> +++ b/drivers/of/device.c
> @@ -135,6 +135,18 @@ void of_dma_configu
On Fri, May 15, 2015 at 12:00:06AM +0100, Laurent Pinchart wrote:
> The of_configure_dma() function configures both the DMA masks and ops.
> Moving DMA ops configuration to probe time would thus also delay
> configuration of the DMA masks, which might not be safe. To avoid issues
> split the config
On Fri, May 15, 2015 at 12:00:08AM +0100, Laurent Pinchart wrote:
> The function isn't trivial, document its behaviour.
>
> Signed-off-by: Laurent Pinchart
> ---
> drivers/iommu/of_iommu.c | 13 +
> 1 file changed, 13 insertions(+)
Thanks for doing this.
common
DMA domain, we may get -ENOSPC-style failures due to limited resources on
the IOMMU. In this case, we'd probably want to fall-back to non-IOMMU DMA
ops, but that in-turn could have consequences on things like dma-coherent.
It's all a bit murky, so I'd be glad to hear any tho
On Fri, May 29, 2015 at 02:14:32AM +0100, Stephen Rothwell wrote:
> Today's linux-next merge of the arm-perf tree got a conflict in
> arch/arm/kernel/perf_event_cpu.c between commit 338d9dd3e2ae ("ARM:
> 8351/1: perf: don't warn about missing interrupt-affinity property for
> PPIs") from Linus' tre
On Thu, Jun 11, 2015 at 01:13:28PM +0100, Vineet Gupta wrote:
> On Wednesday 10 June 2015 06:31 PM, Will Deacon wrote:
> > On Wed, Jun 10, 2015 at 11:58:40AM +0100, Peter Zijlstra wrote:
> >> On Wed, Jun 10, 2015 at 09:34:18AM +, Vineet Gupta wrote:
> >>> On
Hi Waiman,
On Tue, Jun 09, 2015 at 04:19:12PM +0100, Waiman Long wrote:
> The qrwlock is fair in the process context, but becoming unfair when
> in the interrupt context to support use cases like the tasklist_lock.
> However, the unfair code in the interrupt context has problem that
> may cause de
On Thu, Jun 11, 2015 at 11:39:58AM +0100, Maninder Singh wrote:
> Header is not needed in hw_breakpoint.c
> for arm as well as arm64.
> Removing the same.
>
> Signed-off-by: Maninder Singh
> Reviewed-by: Vaneet Narang
> ---
> arch/arm/kernel/hw_breakpoint.c |1 -
> arch/arm64/kernel/hw_
Hi Laurent,
On Fri, May 15, 2015 at 12:00:01AM +0100, Laurent Pinchart wrote:
> This patch series attempts to implement support for deferring probe of both
> IOMMU drivers and bus master drivers.
Have you had a chance to look at any of the feedback you've received on
this?
Will
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Hi Waiman,
On Mon, Jun 15, 2015 at 11:24:02PM +0100, Waiman Long wrote:
> The qrwlock is fair in the process context, but becoming unfair when
> in the interrupt context to support use cases like the tasklist_lock.
>
> The current code isn't that well-documented on what happens when
> in the inte
On Tue, Jun 16, 2015 at 03:35:41PM +0100, Daniel Kurtz wrote:
> The cros-ec-keyboard.dtsi snippet is useful for both arm and arm64 boards.
> Create a link between the two.
>
> This may not be the most scalable solution, so consider it temporary until
> we find a more central repository for such sh
nel/ptrace.c | 39 +-
> include/linux/ptrace.h | 51
> kernel/ptrace.c| 38 ++
> 16 files changed, 116 insertions(+), 363 deletions(-)
Nice cleanup! The ARMy bits all look fine to me.
On Mon, Jun 15, 2015 at 11:24:03PM +0100, Waiman Long wrote:
> The current cmpxchg() loop in setting the _QW_WAITING flag for writers
> in queue_write_lock_slowpath() will contend with incoming readers
> causing possibly extra cmpxchg() operations that are wasteful. This
> patch changes the code to
On Fri, Jun 19, 2015 at 11:08:54PM +0100, Timur Tabi wrote:
> From: Abhimanyu Kapur
>
> Add support for debug communications channel based
> hvc console for arm64 cpus.
I still think we should be disabling userspace access to the DCC if the
kernel is using it as its console.
> Signed-off-by: Ab
On Fri, Jun 19, 2015 at 02:13:02PM +0100, Vineet Gupta wrote:
> On Thursday 11 June 2015 07:09 PM, Will Deacon wrote:
> > On Thu, Jun 11, 2015 at 01:13:28PM +0100, Vineet Gupta wrote:
> >> On Wednesday 10 June 2015 06:31 PM, Will Deacon wrote:
> >>> You also nee
previous writer to go away.
>*/
> for (;;) {
> - cnts = atomic_read(&lock->cnts);
> - if (!(cnts & _QW_WMASK) &&
> - (atomic_cmpxchg(&lock->cnts, cnts,
> - cnts | _QW_WAITING) == cnts))
>
On Tue, Jun 23, 2015 at 03:57:48AM +0100, Waiman Long wrote:
> On 06/22/2015 12:21 PM, Will Deacon wrote:
> > On Fri, Jun 19, 2015 at 04:50:02PM +0100, Waiman Long wrote:
> >> The current cmpxchg() loop in setting the _QW_WAITING flag for writers
> >> in queue_write_l
mb() as well as *mb() APIs
>
> Also hookup barriers into MMIO accessors to avoid ordering issues in IO
>
> Cc: Peter Zijlstra (Intel)
> Cc: Will Deacon
> Signed-off-by: Vineet Gupta
> ---
> Changes since v1
> * Better changelog and comments
> * local/mandatory b
On Tue, Jun 23, 2015 at 10:03:25AM +0100, Vineet Gupta wrote:
> On Tuesday 23 June 2015 02:19 PM, Will Deacon wrote:
> >> +/*
> >> > + * MMIO can also get buffered/optimized in micro-arch, so barriers
> >> > needed
> >> >
l as *mb() APIs
>
> Also hookup barriers into MMIO accessors to avoid ordering issues in IO
>
> Cc: Peter Zijlstra (Intel)
> Cc: Will Deacon
> Signed-off-by: Vineet Gupta
> ---
> Changes since v2
> * lkml discussion link points to lkml redirector (PeterZ)
> * Upda
Reported-by: Kristina Martsenko
Signed-off-by: Will Deacon
---
Not sure why I've just started seeing this, but it appears to affect
both x86 and arm64. Also, if I revert the patch above then the issue
it supposedly fixed doesn't resurface. Maybe it was just masking another
bug that has
Hello,
Thanks for the patch, it's good to see another user of the generic
IO page-table code. However, I have quite a lot of comments on the code.
On Fri, May 15, 2015 at 10:43:26AM +0100, Yong Wu wrote:
> This patch is for ARM Short Descriptor Format.It has 2-levels
> pagetable and the allocator
On Fri, May 15, 2015 at 10:43:28AM +0100, Yong Wu wrote:
> This patch adds support for mediatek m4u (MultiMedia Memory Management Unit).
After looking at the page table code, I thought I'd come and check your
TLB invalidate code here.
> +static void mtk_iommu_tlb_flush_all(void *cookie)
> +{
> +
Hi Joerg,
On Thu, May 28, 2015 at 05:41:33PM +0100, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Add two new functions to the IOMMU-API to allow the IOMMU
> drivers to export the requirements for direct mapped regions
> per device.
> This is useful for exporting the information in Intel VT-d's
>
Hi Joerg,
On Thu, May 28, 2015 at 05:41:23PM +0100, Joerg Roedel wrote:
> here is the second version of my patch-set to introduce
> default domains into the iommu core. This time it has a lot
> more patches, mostly because I added a proof of concept
> implementation by converting the AMD IOMMU dri
Hi Stephen,
On Wed, Jun 03, 2015 at 09:53:37PM +0100, Stephen Boyd wrote:
> It's possible, albeit unlikely, that using the of_node here will
> reference freed memory. Call of_node_put() after printing the
> name to be safe.
>
> Signed-off-by: Stephen Boyd
> ---
> arch/arm64/kernel/perf_event.c
On Mon, Feb 23, 2015 at 05:23:58PM +, Pekka Enberg wrote:
> On 2/18/15 5:50 PM, Will Deacon wrote:
> > Thanks for doing this. Since it looks unlikely that kvmtool will ever be
> > merged back into the kernel tree, it makes sense to cut the dependency
> > in my opinion.
&
Hi all,
Thanks to a tonne of help (and friendly nagging!) from Andre, I'm
pleased to announce a stand-alone repository for kvmtool:
git://git.kernel.org/pub/scm/linux/kernel/git/will/kvmtool.git
This is a follow-up from a previous thread[1] where we concluded that
this was the right way to go.
Hi Alex,
On Fri, May 29, 2015 at 10:30:26AM +0100, Alex Bennée wrote:
> This adds support for userspace to control the HW debug registers for
> guest debug. In the debug ioctl we copy the IMPDEF defined number of
> registers into a new register set called host_debug_state. There is now
> a new vcp
On Mon, Jun 01, 2015 at 01:12:53AM +0100, Stephen Rothwell wrote:
> Hi Will,
Hi Stephen,
> Today's linux-next merge of the arm-perf tree got a conflict in
> arch/arm/kernel/perf_event_cpu.c between commit 338d9dd3e2ae ("ARM:
> 8351/1: perf: don't warn about missing interrupt-affinity property fo
say cpu updating a
> > shared
> > buffer descriptor and kicking a MMIO register (which in turn could initiate
> > a DMA)
> > but I'm not sure how mb() can possibly order with DMA per se (unless
> > there's some
> > advanced form of IO-coherency)
&
On Thu, Jun 11, 2015 at 10:18:44AM +0100, Maninder Singh wrote:
> This patch fixes below checkpatch.pl warning:
> WARNING: Use #include instead of
>
> Signed-off-by: Maninder Singh
> Reviewed-by: Vaneet Narang
> ---
> arch/arm/kernel/hw_breakpoint.c |2 +-
> 1 files changed, 1 insertions(+)
eneric/qrwlock.h |4 ++--
> kernel/locking/qrwlock.c | 13 +++--
> 2 files changed, 9 insertions(+), 8 deletions(-)
LGTM:
Reviewed-by: Will Deacon
Will
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On Thu, Jun 18, 2015 at 02:33:56AM +0100, Waiman Long wrote:
> On 06/16/2015 02:02 PM, Will Deacon wrote:
> > On Mon, Jun 15, 2015 at 11:24:03PM +0100, Waiman Long wrote:
> >> The current cmpxchg() loop in setting the _QW_WAITING flag for writers
> >> in queue_write_l
> of the GICC subtable that the old macro did not; this caused failures even
> though the subtable entries are valid.
>
> Signed-off-by: Al Stone
> ---
> arch/arm64/kernel/smp.c | 2 +-
> drivers/irqchip/irq-gic.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
On Fri, Jun 19, 2015 at 10:55:26AM +0100, Vineet Gupta wrote:
> A quad core SMP build could get into hardware livelock with concurrent
> LLOCK/SCOND. Workaround that by adding a PREFETCHW which is serialized by
> SCU (System Coherency Unit). It brings the cache line in Exclusive state
> and makes o
Hi Laura,
On Tue, May 22, 2018 at 04:50:49PM -0700, Laura Abbott wrote:
> Commit 15122ee2c515 ("arm64: Enforce BBM for huge IO/VMAP mappings")
> disallowed block mappings for ioremap since that code does not honor
> break-before-make. The same APIs are also used for permission updating
> though an
Signed-off-by: Dave Martin
> Cc: Ingo Molnar
> Cc: Peter Zijlstra
> Cc: Steven Rostedt
> Cc: Oleg Nesterov
> ---
Looks sensible to me:
Acked-by: Will Deacon
Will
On Thu, Apr 19, 2018 at 11:58:45AM +0100, Dave Martin wrote:
> This patch uses the new update_thread_flag() helpers to simplify a
> couple of if () set; else clear; constructs.
>
> No functional change.
>
> Signed-off-by: Dave Martin
> Cc: Catalin Marinas
> Cc: Will Dea
Hi Prasad,
On Tue, May 22, 2018 at 12:40:05PM -0700, Sodagudi Prasad wrote:
> When following test is executed on 4.14.41 stable kernel, observed that one
> of the core is waiting for tasklist_lock for long time with IRQs disabled.
> ./stress-ng-64 --get 8 -t 3h --times --metrics-brief
>
> Every t
Hi Chintan,
[as a side note: I'm confused on the status of this patch series, as part
of it was reposted separately by Toshi. Please can you work together?]
On Mon, Apr 30, 2018 at 01:11:33PM +0530, Chintan Pandya wrote:
> Implement pud_free_pmd_page() and pmd_free_pte_page().
>
> Implementatio
y Lutomirski
> Cc: Yoshinori Sato
> Cc: Rich Felker
> Cc: Ingo Molnar
> Cc: Thomas Gleixner
> Cc: Will Deacon
> Cc: Mark Rutland
> Cc: Max Filippov
> Cc: Chris Zankel
> Cc: Catalin Marinas
> Cc: Benjamin Herrenschmidt
> Cc: Paul Mackerras
> Cc: Michael
[+Boqun]
On Wed, May 23, 2018 at 08:25:06AM -0700, Linus Torvalds wrote:
> On Wed, May 23, 2018 at 6:05 AM Will Deacon wrote:
>
> > Please use a newer kernel. We've addressed this in mainline by moving
> > arm64 over to the qrwlock implementation which (after some other
> the compiler can tear, potentially resulting in userspace seeing
> erroneous values.
>
> We can solve both of these problems by using smp_store_release to update
> data_head and aux_head, so let's do so.
>
> Signed-off-by: Mark Rutland
> Cc: Ingo Molnar
> Cc: Peter Z
Hi Laura,
On Wed, May 23, 2018 at 11:43:46AM -0700, Laura Abbott wrote:
> Commit 15122ee2c515 ("arm64: Enforce BBM for huge IO/VMAP mappings")
> disallowed block mappings for ioremap since that code does not honor
> break-before-make. The same APIs are also used for permission updating
> though an
inked to the (likewise unclear) semantics of spin_unlock_wait().
>
> Document this semantics.
>
> Signed-off-by: Andrea Parri
> Cc: Alan Stern
> Cc: Will Deacon
> Cc: Peter Zijlstra
> Cc: Boqun Feng
> Cc: Nicholas Piggin
> Cc: David Howells
> Cc: Jade Alglave
>
On Tue, Feb 27, 2018 at 09:08:31PM +0100, Andrea Parri wrote:
> [+ Will]
>
> I'm not sure how this happened; Will, you at least figure as Reported-by: ;-)
Thanks, this looks better to me. Have you build an Alpha kernel to check
that the various cmpxchg variants are producing the expected asm?
Wi
On Wed, Feb 28, 2018 at 12:24:03PM +0100, Andrea Parri wrote:
> On Wed, Feb 28, 2018 at 10:56:32AM +0000, Will Deacon wrote:
> > On Wed, Feb 28, 2018 at 11:39:32AM +0100, Andrea Parri wrote:
> > > There appeared to be a certain, recurrent uncertainty concerning the
On Thu, Mar 01, 2018 at 10:28:03AM -0600, Rob Herring wrote:
> libfdt gained a new dependency on strrchr, so make it available to the
> EFI namespace before we update libfdt.
>
> Thanks to Ard for providing this fix.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
>
On Thu, Mar 01, 2018 at 05:10:38PM +, Ard Biesheuvel wrote:
> On 1 March 2018 at 17:08, Will Deacon wrote:
> > On Thu, Mar 01, 2018 at 10:28:03AM -0600, Rob Herring wrote:
> >> libfdt gained a new dependency on strrchr, so make it available to the
> >> EFI namesp
On Sat, Mar 31, 2018 at 11:35:46AM +0200, Ingo Molnar wrote:
> * Peter Zijlstra wrote:
> > On Mon, Jan 15, 2018 at 05:00:20PM +0200, Alexander Shishkin wrote:
> > > diff --git a/include/uapi/linux/perf_event.h
> > > b/include/uapi/linux/perf_event.h
> > > index c77c9a2e..d7a981130561 100644
>
sed on a list of MIDRs
arm64: capabilities: Handle shared entries
arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35
arm64: Delay enabling hardware DBM feature
arm64: Add work around for Arm Cortex-A55 Erratum 1024718
Will Deacon (20):
arm64: signal: Make force_s
Hi Peter,
On Thu, Apr 05, 2018 at 11:37:16AM +0200, Peter Zijlstra wrote:
> Subject: locking/mutex: Optimize __mutex_trylock_fast()
> From: Peter Zijlstra
> Date: Thu Apr 5 11:05:35 CEST 2018
>
> Use try_cmpxchg to avoid the pointless TEST instruction..
> And add the (missing) atomic_long_try_c
st of the lockword.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
kernel/locking/qspinlock.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
index b75361d23ea5..cdfa7b7328a8 1
locked spinning from the slowpath and instead
queue explicitly if pending is set.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
kernel/locking/qspinlock.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
e
can replace the two RELEASE operations with a single smp_wmb() fence and
use RELAXED operations for the subsequent publishing of the node.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
kernel/locking/qspinlock.c | 32 +++-
1 file changed, 15 inse
__qspinlock into struct qspinlock and kill the extra
definition.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
arch/x86/include/asm/qspinlock.h | 2 +-
arch/x86/include/asm/qspinlock_paravirt.h | 3 +-
include/asm-generic/qspinlock_types.h | 32
A qspinlock can be unlocked simply by writing zero to the locked byte.
This can be implemented in the generic code, so do that and remove the
arch-specific override for x86 in the !PV case.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
arch/x86/include/asm/qspinlock.h | 17
(1):
locking/mcs: Use smp_cond_load_acquire() in mcs spin loop
Will Deacon (9):
locking/qspinlock: Don't spin on pending->locked transition in
slowpath
locking/qspinlock: Remove unbounded cmpxchg loop from locking slowpath
locking/qspinlock: Kill cmpxchg loop when claiming lock from head of
with its own implementation using WFE.
On x86, this can also be cheaper than spinning on
smp_load_acquire().
Signed-off-by: Jason Low
Signed-off-by: Will Deacon
---
kernel/locking/mcs_spinlock.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/kernel/locking
ter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
kernel/locking/qspinlock.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
index 291e1526d27b..c8b57d375b49 100644
--- a/kernel/locking/qspinlock.c
++
primitives
to avoid unnecessary barrier overhead on architectures such as arm64.
Signed-off-by: Will Deacon
---
include/asm-generic/barrier.h | 27 +--
include/linux/atomic.h| 2 ++
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/include/asm-generic
it when taking the lock
after reaching the head of the queue and leaving the tail entry intact
if we saw pending set, because we know that the tail is going to be
updated shortly.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
ke
Rather than dig into the counter field of the atomic_t inside the
qspinlock structure so that we can call smp_cond_load_acquire, use
atomic_cond_read_acquire instead, which operates on the atomic_t
directly.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Signed-off-by: Will Deacon
---
kernel/locking
Hi Andrea,
On Mon, Mar 26, 2018 at 04:14:36PM +0200, Andrea Parri wrote:
> On Mon, Mar 26, 2018 at 11:57:05AM +0100, Will Deacon wrote:
> > On Mon, Mar 26, 2018 at 12:37:21PM +0200, Andrea Parri wrote:
> > > Commit 38b850a73034f ("arm64: spinlock: order spin_{is_locked,unl
+= $(call cc-option,-mabi=lp64)
>
> -KBUILD_CFLAGS+= $(call cc-ifversion, -ge, 0500,
> -DCONFIG_ARCH_SUPPORTS_INT128)
> -
If this does what it claims to do, then I agree that it's much cleaner!
Acked-by: Will Deacon
Will
Hi Shanker,
On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> On 03/27/2018 06:34 AM, Robin Murphy wrote:
> > On 27/03/18 04:21, Philip Elcan wrote:
> >> Several of the bits of the TLBI register operand are RES0 per the ARM
> >> ARM, so TLBI operations should avoid writing non-
Hi Chintan,
On Tue, Mar 27, 2018 at 06:54:59PM +0530, Chintan Pandya wrote:
> Implement pud_free_pmd_page() and pmd_free_pte_page().
>
> Implementation requires,
> 1) Freeing of the un-used next level page tables
> 2) Clearing off the current pud/pmd entry
> 3) Invalidate TLB which could have
On Wed, Mar 28, 2018 at 09:46:55AM +0200, Vincent Guittot wrote:
> Arm DynamiQ system can integrate cores with different micro architecture
> or max OPP under the same DSU so we can have cores with different compute
> capacity at the LLC (which was not the case with legacy big/LITTLE
> architecture
Hi Stephen,
On Wed, Mar 28, 2018 at 04:00:34PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the kvm-arm tree got a conflict in:
>
> arch/arm64/kernel/cpu_errata.c
>
> between commit:
>
> c0cda3b8ee6b ("arm64: capabilities: Update prototype for enable call back")
On Tue, Mar 27, 2018 at 08:03:07PM -0500, Shanker Donthineni wrote:
> On 03/27/2018 12:36 PM, Will Deacon wrote:
> > On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> >>>> @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct
&g
Hi Peter,
On Thu, Apr 26, 2018 at 05:53:35PM +0200, Peter Zijlstra wrote:
> On Thu, Apr 26, 2018 at 11:34:19AM +0100, Will Deacon wrote:
> > @@ -290,58 +312,50 @@ void queued_spin_lock_slowpath(struct qspinlock
> > *lock, u32 val)
> > }
> >
> >
Hi Waiman,
On Thu, Apr 26, 2018 at 04:16:30PM -0400, Waiman Long wrote:
> On 04/26/2018 06:34 AM, Will Deacon wrote:
> > diff --git a/kernel/locking/qspinlock_paravirt.h
> > b/kernel/locking/qspinlock_paravirt.h
> > index 2711940429f5..2dbad2f25480 100644
>
On Fri, Apr 27, 2018 at 08:15:25AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 10:30:27 +0100
> Mark Rutland wrote:
> > On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote:
> > > On Wed, 25 Apr 2018 14:30:47 +0530
> > > Ganapatrao Kulkarni wrote:
> > >
> > > > +static int thunderx2
Kim,
[Ganapat: please don't let this discussion disrupt your PMU driver
development. You can safely ignore it for now :)]
On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 15:37:20 +0100
> Will Deacon wrote:
>
> > On Fri, Apr 27, 2018 at 0
Hi Linus,
Please pull these arm64 fixes for -rc3. Nothing too bad, but the spectre
updates to smatch identified a few places that may need sanitising so we've
got those covered. As per usual, details are in the tag.
It's worth noting that we had some DMARC hiccups this week which should be
resolv
On Mon, Apr 23, 2018 at 10:30:49AM +0530, Chandan Vn wrote:
> May I know when this patch would be taken for merging?
Please can you send a new version, stating in the commit message that
this only affects accountinga and debugging, rather than plugging an
actual memory leak?
Cheers,
Will
/*
> + * load_module() results in W+X mappings, which are cleaned up
> + * with call_rcu_sched(). Let's make sure that queued work is
> + * flushed so that we don't hit false positives looking for
> + * insecure pa
On Sat, Apr 28, 2018 at 02:45:37PM +0200, Peter Zijlstra wrote:
> On Thu, Apr 26, 2018 at 05:55:19PM +0100, Will Deacon wrote:
> > On Thu, Apr 26, 2018 at 05:53:35PM +0200, Peter Zijlstra wrote:
> > > On Thu, Apr 26, 2018 at 11:34:19AM +0100, Will Deacon wrote:
> > > &
Hi Kim,
On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 17:09:14 +0100
> Will Deacon wrote:
> > On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote:
> > > On Fri, 27 Apr 2018 15:37:20 +0100
> > > Will Deacon wrote:
>
On Wed, May 02, 2018 at 03:53:21PM +0800, Ganesh Mahendran wrote:
> Set ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT for arm64. This
> enables Speculative Page Fault handler.
Are there are tests for this? I'm really nervous about enabling it...
Will
>
> Signed-off-by: Ganesh Mahendran
> ---
> This pat
On Mon, May 28, 2018 at 11:33:53AM +0800, nixiaoming wrote:
> Signed-off-by: nixiaoming
Please can you write a commit message explaining what this fixes and also
give me a pointer to patches 2 and 3 from this series?
Will
> ---
> arch/arm64/mm/mmu.c | 2 ++
> 1 file changed, 2 insertions(+)
Hi Paul,
On Fri, May 25, 2018 at 12:10:20PM -0700, Paul E. McKenney wrote:
> This commit documents the scheme used to generate the names for the
> litmus tests.
>
> Signed-off-by: Paul E. McKenney
> ---
> README | 136
> -
> 1 fi
Hi Arnd, Russell, [+Nico and Robin]
On Mon, May 28, 2018 at 05:44:36PM +0200, Arnd Bergmann wrote:
> Now that the ARM CCI PMU driver can be built as a loadable module,
> we get a link failure when MCPM is enabled:
>
> ERROR: "mcpm_is_available" [drivers/perf/arm-cci.ko] undefined!
>
> The simple
Hi Russell,
On Tue, May 29, 2018 at 04:33:24PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 29, 2018 at 04:30:14PM +0100, Will Deacon wrote:
> > Hi Arnd, Russell, [+Nico and Robin]
> >
> > On Mon, May 28, 2018 at 05:44:36PM +0200, Arnd Bergmann wrote:
> >
On Tue, May 29, 2018 at 04:34:01PM +0100, Robin Murphy wrote:
> On 28/05/18 16:41, Arnd Bergmann wrote:
> >When the arm-cci driver is enabled, but both CONFIG_ARM_CCI5xx_PMU and
> >CONFIG_ARM_CCI400_PMU are not, we get a warning about how parts of
> >the driver are never used:
> >
> >drivers/perf/a
On Tue, May 29, 2018 at 09:36:15PM +0800, nixiaoming wrote:
> mark_rodata_ro is only called by the function mark_readonly when
> CONFIG_STRICT_KERNEL_RWX=y,
> if CONFIG_STRICT_KERNEL_RWX is not set
> a compile warning may be triggered: unused function
How are you achieving this configuration? In o
On Tue, May 29, 2018 at 04:42:51PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 29, 2018 at 04:41:20PM +0100, Will Deacon wrote:
> > Hi Russell,
> >
> > On Tue, May 29, 2018 at 04:33:24PM +0100, Russell King - ARM Linux wrote:
> > > On Tue, May 29, 2018 at
On Tue, May 29, 2018 at 05:11:07AM -0700, Paul E. McKenney wrote:
> On Tue, May 29, 2018 at 10:30:50AM +0100, Will Deacon wrote:
> > Hi Paul,
> >
> > On Fri, May 25, 2018 at 12:10:20PM -0700, Paul E. McKenney wrote:
> > > This commit documents the scheme used
On Mon, Jun 04, 2018 at 09:40:29AM +0200, Peter Zijlstra wrote:
> On Fri, Jun 01, 2018 at 05:06:20PM +0100, Will Deacon wrote:
> > Hi all,
> >
> > This patch series has previously been posted in RFC form here:
> >
> > RFCv1: https://www.spinics.net/lists/arm-
Hi Chintan,
On Mon, Jun 04, 2018 at 11:26:28AM +0530, Chintan Pandya wrote:
> Just curious to know, is there anything that I should be addressing
> in these patches ? For now, I don't see anything from my side that
> requires modification, unless one has some more review comments on
> this.
>
> S
On Fri, Jun 01, 2018 at 06:09:16PM +0530, Chintan Pandya wrote:
> Add helper macros to give virtual references to page
> tables. These will be used while freeing dangling
> page tables.
>
> Signed-off-by: Chintan Pandya
> ---
> arch/arm64/include/asm/pgtable.h | 3 +++
> 1 file changed, 3 insert
On Fri, Jun 01, 2018 at 06:09:17PM +0530, Chintan Pandya wrote:
> Implement pud_free_pmd_page() and pmd_free_pte_page().
>
> Implementation requires,
> 1) Clearing off the current pud/pmd entry
> 2) Invalidate TLB which could have previously
> valid but not stale entry
> 3) Freeing of the u
On Fri, Jun 01, 2018 at 06:09:18PM +0530, Chintan Pandya wrote:
> Huge mappings have had stability issues due to stale
> TLB entry and memory leak issues. Since, those are
> addressed in this series of patches, it is now safe
> to allow huge mappings.
>
> Signed-off-by: Chintan Pandya
> ---
> ar
On Mon, Jun 04, 2018 at 07:13:18PM +0530, Chintan Pandya wrote:
> On 6/4/2018 5:43 PM, Will Deacon wrote:
> >On Fri, Jun 01, 2018 at 06:09:17PM +0530, Chintan Pandya wrote:
> >>+ next = addr;
> >>+ end = addr + P
On Mon, Jun 04, 2018 at 07:13:48PM +0530, Chintan Pandya wrote:
>
>
> On 6/4/2018 5:43 PM, Will Deacon wrote:
> >On Fri, Jun 01, 2018 at 06:09:16PM +0530, Chintan Pandya wrote:
> >>Add helper macros to give virtual references to page
> >>tables. These will be use
On Tue, Jun 05, 2018 at 12:51:24AM +0900, Masami Hiramatsu wrote:
> Remove arch dependent setjump/longjump functions
> and unused fields in kprobe_ctlblk for jprobes
> from arch/arm64.
>
> Signed-off-by: Masami Hiramatsu
> Cc: Catalin Marinas
> Cc: Will Deacon
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