V3 changes:
- patch 02/04: Added SERIAL_SUNHV conditional group for
sunhv_migrate_hvcons_irq in smp_send_stop().
V2 changes:
- Added cover letter patch
Hi,
Currently Stop-A (L1A) does not make the kernel switch to OBP on panic. This
patchset addresses this issue. Also, now we can cause a
Now we can also jump to boot prom from sunhv console by sending
break twice on console for both running and panicked kernel
cases.
Signed-off-by: Vijay Kumar
---
drivers/tty/serial/sunhv.c |6 +-
kernel/panic.c |3 ++-
2 files changed, 7 insertions(+), 2 deletions
CPU needs to be marked offline before stopping it. When not marked
offline, the xcall receives HV_EWOULDBLOCK and so assumes that not all
CPUs received the message, and retries. After 1 retries, it finally
fails with fatal mondo timeout.
Signed-off-by: Vijay Kumar
---
arch/sparc/kernel
Documented the steps for sending break on sunhv console.
Signed-off-by: Vijay Kumar
---
Documentation/sparc/console.txt |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/Documentation/sparc/console.txt b/Documentation/sparc/console.txt
new file mode 100644
index
On panic, all other CPUs are stopped except the one which had
hit panic. To keep console alive, we need to migrate hvcons irq
to panicked CPU.
Signed-off-by: Vijay Kumar
---
v2->v3: Added SERIAL_SUNHV conditional group for
sunhv_migrate_hvcons_irq().
---
arch/sparc/include/asm/setu
On 2/1/2017 1:50 PM, David Miller wrote:
From: Vijay Kumar
Date: Wed, 1 Feb 2017 11:34:36 -0800
Currently Stop-A (L1A) does not make the kernel switch to OBP on panic.
This is intentional, the kernel prints a message telling the user to
press break (L1-A) if they want to drop out of the
Updated Documentation/ABI for devspec and obppath sysfs entries.
Signed-off-by: Vijay Kumar
---
Documentation/ABI/stable/sysfs-devices | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/Documentation/ABI/stable/sysfs-devices
b/Documentation/ABI/stable/sysfs
Grub finds incorrect of_node path for devices behind usb hub.
Added devspec sysfs entry for devices behind usb hub so that
right of_node path is returned during grub sysfs walk for these
devices.
Signed-off-by: Vijay Kumar
---
drivers/usb/core/sysfs.c | 15 +++
1 files changed, 15
CPU needs to be marked offline before stopping it. When not marked
offline, the xcall receives HV_EWOULDBLOCK and so assumes that not all
CPUs received the message, and retries. After 1 retries, it finally
fails with fatal mondo timeout.
Signed-off-by: Vijay Kumar
---
arch/sparc/kernel
Documented the steps for sending break on sunhv console.
Signed-off-by: Vijay Kumar
---
Documentation/sparc/console.txt |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/Documentation/sparc/console.txt b/Documentation/sparc/console.txt
new file mode 100644
index
Now we can also jump to boot prom from sunhv console by sending
break twice on console for both running and panicked kernel
cases.
Signed-off-by: Vijay Kumar
---
drivers/tty/serial/sunhv.c |6 +-
kernel/panic.c |3 ++-
2 files changed, 7 insertions(+), 2 deletions
On panic, all other CPUs are stopped except the one which had
hit panic. To keep console alive, we need to migrate hvcons irq
to panicked CPU.
Signed-off-by: Vijay Kumar
---
arch/sparc/include/asm/setup.h |1 +
arch/sparc/kernel/smp_64.c |6 +-
drivers/tty/serial/sunhv.c
Here is the cover posting for the patches. I did not send cover patch initially
as I thought that patch descriptions were self explanatory. But I agree, this
would
help in overall understanding of the patch.
Currently Stop-A (L1A) does not make the kernel switch to OBP on panic. This
patchset a
On panic, all other CPUs are stopped except the one which had
hit panic. To keep console alive, we need to migrate hvcons irq
to panicked CPU.
Signed-off-by: Vijay Kumar
---
arch/sparc/include/asm/setup.h |1 +
arch/sparc/kernel/smp_64.c |6 +-
drivers/tty/serial/sunhv.c
Documented the steps for sending break on sunhv console.
Signed-off-by: Vijay Kumar
---
Documentation/sparc/console.txt |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/Documentation/sparc/console.txt b/Documentation/sparc/console.txt
new file mode 100644
index
CPU needs to be marked offline before stopping it. When not marked
offline, the xcall receives HV_EWOULDBLOCK and so assumes that not all
CPUs received the message, and retries. After 1 retries, it finally
fails with fatal mondo timeout.
Signed-off-by: Vijay Kumar
---
arch/sparc/kernel
Currently Stop-A (L1A) does not make the kernel switch to OBP on panic. This
patchset addresses this issue. Also, now we can cause a jump to OBP by sending
'break' twice from sunhv console. On bare metal, one can send a break by
typing Esc + 'B' + Sysrq (or whatever). On LDOM, press Ctrl + ] in tel
Now we can also jump to boot prom from sunhv console by sending
break twice on console for both running and panicked kernel
cases.
Signed-off-by: Vijay Kumar
---
drivers/tty/serial/sunhv.c |6 +-
kernel/panic.c |3 ++-
2 files changed, 7 insertions(+), 2 deletions
On 11/19/2016 9:48 AM, David Miller wrote:
From: Vijay Kumar
Date: Fri, 11 Nov 2016 10:11:57 -0800
@@ -1444,8 +1444,12 @@ void smp_send_stop(void)
int cpu;
if (tlb_type == hypervisor) {
+ int this_cpu = smp_processor_id
ked.
This fix skips calling uart sysrq handler when 'NULL' is received while
sysrq is enabled.
Signed-off-by: Vijay Kumar
Acked-by: Karl Volz
---
drivers/tty/serial/sunhv.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/sunhv.c b/driver
Use cpu_poke hypervisor call to resume idle cpu if supported.
Signed-off-by: Vijay Kumar
Reviewed-by: Anthony Yznaga
---
arch/sparc/include/asm/smp_64.h |5 ++
arch/sparc/kernel/hvapi.c |2 +-
arch/sparc/kernel/process_64.c |7 +++-
arch/sparc/kernel/setup_64.c|1
This adds a new hypercall CPU_POKE for quickly waking up an idle CPU.
CPU POKE should only be sent to valid non-local CPUs.
Signed-off-by: Rob Gardner
Signed-off-by: Vijay Kumar
Reviewed-by: Anthony Yznaga
---
arch/sparc/include/asm/hypervisor.h | 18 ++
arch/sparc/kernel
0.010
10 0.0210.019
100 0.1510.148
Vijay Kumar (2):
sparc64: Add a new hypercall CPU_POKE
sparc64: Use cpu_poke to resume idle cpu
arch/sparc/include/asm/hypervisor.h | 17
arch/sparc/include/asm/smp_64.h
On 7/20/2017 2:57 PM, David Miller wrote:
From: Vijay Kumar
Date: Sat, 8 Jul 2017 14:23:42 -0600
cpu_poke is a low latency path to resume the target cpu if suspended
using cpu_yield. Use cpu poke to resume cpu if supported by hypervisor.
hackbench results (lower is better
On 7/20/2017 2:58 PM, David Miller wrote:
From: Vijay Kumar
Date: Sat, 8 Jul 2017 14:23:44 -0600
diff --git a/arch/sparc/kernel/hvapi.c b/arch/sparc/kernel/hvapi.c
index 2677312..0b070d5 100644
--- a/arch/sparc/kernel/hvapi.c
+++ b/arch/sparc/kernel/hvapi.c
@@ -189,7 +189,7 @@ void __init
On 7/20/2017 9:55 PM, David Miller wrote:
From: Vijay Kumar
Date: Thu, 20 Jul 2017 21:44:24 -0500
I had same thoughts initially but I had to go with this approach as
scheduler_ipi is wrapped with irq_enter() and irq_exit(). Whereas POKE
resumes the cpu in process context.
Comments in
On 7/20/2017 10:45 PM, David Miller wrote:
From: Vijay Kumar
Date: Thu, 20 Jul 2017 22:36:42 -0500
I can give a try :). But looks to me one thing that will go wrong is
irq accounting done in __irq_enter() and rcu_irq_enter().
Actually, the bigger problem is that scheduler_ipi() can raise a
Defined SPARC optimized fls using lzcnt opcode.
Signed-off-by: Vijay Kumar
---
arch/sparc/lib/Makefile |1 +
arch/sparc/lib/NG4fls.S | 20
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index 5380c59
For T4 and above, patch fls and __fls functions
at the boot time to use lzcnt instruction.
Signed-off-by: Vijay Kumar
---
arch/sparc/kernel/head_64.S |2 ++
arch/sparc/lib/NG4patch.S |9 +
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/kernel
__fls will now require a boot time patching on T4 and above.
Redefining it under arch/sparc/lib.
Signed-off-by: Vijay Kumar
---
arch/sparc/include/asm/bitops_64.h |2 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls64.S | 61
fls will now require a boot time patching on T4 and above.
Redefining it under arch/sparc/lib.
Signed-off-by: Vijay Kumar
---
arch/sparc/include/asm/bitops_64.h |3 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls.S | 67
ENTRY(), ENDPROC() for assembler functions.
- Removed BITS_PER_LONG from __fls.
- Using generic fls64().
- Replaced lzcnt instruction with .word directive.
v1->v2:
- Fixed delay slot issue.
Vijay Kumar (5):
sparc64: Define SPARC default fls function
sparc64: Define SPARC default __fls
Defined SPARC optimized __fls using lzcnt opcode.
Signed-off-by: Vijay Kumar
---
arch/sparc/lib/NG4fls.S | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/lib/NG4fls.S b/arch/sparc/lib/NG4fls.S
index bc17b65..2d0991e 100644
--- a/arch/sparc/lib
SPARC provides lzcnt instruction (with VIS3) which can be used to
optimize fls, fls64 and __fls functions. For the systems that supports
lzcnt instruction, we now do boot time patching to use sparc
optimized fls, fls64 and __fls functions.
Vijay Kumar (2):
sparc64: Define SPARC default fls
For T4 and above, patch fls and __fls functions
at the boot time to use lzcnt instruction.
Signed-off-by: Vijay Kumar
Reviewed-by: Babu Moger
---
arch/sparc/Makefile |1 +
arch/sparc/kernel/head_64.S |2 ++
arch/sparc/lib/Makefile |3 +++
arch/sparc/lib/NG4fls.S
fls and __fls will now require boot time patching on T4
and above. Redefining these functions under arc/sparc/lib.
Signed-off-by: Vijay Kumar
Reviewed-by: Babu Moger
---
arch/sparc/include/asm/bitops_64.h |7 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls.S
fls and __fls will now require boot time patching on T4
and above. Redefining these functions under arc/sparc/lib.
Signed-off-by: Vijay Kumar
Reviewed-by: Babu Moger
---
arch/sparc/include/asm/bitops_64.h |7 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls.S
Rob Gardner in patch 2/2.
Vijay Kumar (2):
sparc64: Define SPARC default fls and __fls
sparc64: Use lzcnt instruction for fls and __fls
arch/sparc/Makefile|1 +
arch/sparc/include/asm/bitops_64.h |7 +-
arch/sparc/kernel/head_64.S|2 +
arch/sparc/lib/Makef
For T4 and above, patch fls and __fls functions
at the boot time to use lzcnt instruction.
Signed-off-by: Vijay Kumar
Reviewed-by: Babu Moger
---
arch/sparc/Makefile |1 +
arch/sparc/kernel/head_64.S |2 ++
arch/sparc/lib/Makefile |3 +++
arch/sparc/lib/NG4fls.S
Hi Sam,
On 9/27/2017 2:56 PM, Sam Ravnborg wrote:
.size niagara4_patch_pageops,.-niagara4_patch_pageops
+
+ .globl niagara4_patch_fls
+ .type niagara4_patch_fls,#function
+niagara4_patch_fls:
+ NG_DO_PATCH(fls, NG4fls)
+ NG_DO_PATCH(__fls, __NG4fls)
+ r
fls will now require a boot time patching on T4 and above.
Redefining it under arch/sparc/lib.
Signed-off-by: Vijay Kumar
---
arch/sparc/include/asm/bitops_64.h |3 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls.S | 67
Defined SPARC optimised __fls using lzcnt opcode.
Signed-off-by: Vijay Kumar
---
arch/sparc/lib/NG4fls.S | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/lib/NG4fls.S b/arch/sparc/lib/NG4fls.S
index 5ed7da9..34ad371 100644
--- a/arch/sparc/lib
Defined SPARC optimised fls using lzcnt opcode.
Signed-off-by: Vijay Kumar
---
arch/sparc/lib/Makefile |1 +
arch/sparc/lib/NG4fls.S | 20
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index 5380c59
__fls will now require a boot time patching on T4 and above.
Redefining it under arch/sparc/lib.
Signed-off-by: Vijay Kumar
---
arch/sparc/include/asm/bitops_64.h |2 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls64.S | 61
ler functions.
- Removed BITS_PER_LONG from __fls.
- Using generic fls64().
- Replaced lzcnt instruction with .word directive.
v1->v2:
- Fixed delay slot issue.
Vijay Kumar (2):
sparc64: Define SPARC default fls and __fls
sparc64: Use lzcnt instruction for fls and __fls
arch/sparc/Ma
For T4 and above, patch fls and __fls functions
at the boot time to use lzcnt instruction.
Signed-off-by: Vijay Kumar
---
arch/sparc/kernel/head_64.S |2 ++
arch/sparc/lib/NG4patch.S |9 +
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/sparc/kernel
On 10/8/2017 11:39 PM, David Miller wrote:
From: Vijay Kumar
Date: Fri, 6 Oct 2017 10:54:51 -0600
+#define LXCNT_O0_G2\
+ .word 0x85b002e8
+
+ .text
+ .register %g2, #scratch
+ .register %g3, #scratch
+
+ENTRY(NG4fls)
+ LXCNT_O0_G2 !lzcnt
Grub finds incorrect of_node path for devices behind usb hub.
Added devspec sysfs entry for devices behind usb hub so that
right of_node path is returned during grub sysfs walk for these
devices.
Signed-off-by: Vijay Kumar
---
drivers/usb/core/sysfs.c | 15 +++
1 files changed
On 10/4/2016 2:49 PM, Greg KH wrote:
On Tue, Oct 04, 2016 at 12:04:40PM -0700, Vijay Kumar wrote:
Grub finds incorrect of_node path for devices behind usb hub.
Added devspec sysfs entry for devices behind usb hub so that
right of_node path is returned during grub sysfs walk for these
devices
This patch is to correct clcd pin group name "clcd_high_res" to
"clcd_high_res_grp" to avoid kernel boot hang as with following error message.
spear1310-pinmux e070.pinmux: invalid group "clcd_high_res" for function
"clcd".
---
arch/arm/boot/dts/spear1310-evb.dts |2 +-
1 file changed, 1
Memory split 2G/2G is enabled as needed for SPEAr1310 RevC board to boot.
Before enabling this option the boot was hanging at uncompressing linux.
---
arch/arm/configs/spear13xx_defconfig |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/configs/spear13xx_defconfig
This patch set contains following patches:
1. Enables correct kernel/user memory split required for SPEAr13xx.
2. Fix to correct SPEAr1310 device tree.
3. Fix to add ARM ABI support.
This patch set is tested on kernel V3.8-rc6.
Vijay Kumar Mishra (3):
SPEAr13xx_defconfig: Enable Memory
This Patch is to enable CONFIG_AEABI option in kernel. Which basically adds
support for latest ARMABI (EABI).
It also include support for changes the kernel syscall calling convention to
disambiguate both ABIs and allow for backward compatibility support.
Without this option the kernel crashes. C
The PXA GPIO controller has 3 interrupt outputs, this needs to be
indicated in the DTS file. Without this mainstone's CPLD interrupt 0
will not be raised to the processor.
Signed-off-by: Vijay Kumar B.
Reviewed-by: Deepak S.
---
arch/arm/boot/dts/pxa2xx.dtsi | 4 ++--
1 file chang
The PXA GPIO controller has 3 interrupt outputs, this needs to be
indicated in the DTS file. Without this mainstone's CPLD interrupt 0
will not be raised to the processor.
Signed-off-by: Vijay Kumar B.
Reviewed-by: Deepak S.
---
arch/arm/boot/dts/pxa2xx.dtsi | 4 ++--
1 file chang
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