[...]
Hi Mathieu
On 16/08/24 20:06, Mathieu Poirier wrote:
>>> +/*
>>> + * Attach to a running M4 remote processor (IPC-only mode)
>>> + *
>>> + * The remote processor is already booted, so there is no need to issue any
>>> + * TI-SCI commands to boot the M4 core. This callback is used only in
>
Hi,
On 2/12/21 8:10 PM, Vladimir Oltean wrote:
> On Fri, Feb 12, 2021 at 08:01:33PM +0530, Vignesh Raghavendra wrote:
>> Hi Vladimir,
>>
>> On 2/12/21 7:47 PM, Grygorii Strashko wrote:
>>>
>>>
>>> On 12/02/2021 03:05, Vladimir Oltean wrote:
>>
On 28/02/19 12:32 PM, Naga Sureshkumar Relli wrote:
> Add support for QSPI controller driver used by Xilinx Zynq SOC.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile| 1 +
> drivers/spi/spi-zynq-qspi.c | 780
> ++
[...]
> In function do_write_buffer(), in the for loop, there is a case
> chip_ready() returns 1 while chip_good() returns 0, so it never break
> the loop.
> To fix this, chip_good() is enough and it should timeout if it stay
> bad for a while.
>
> Fixes: dfeae1073583("m
On 01-Mar-19 11:25 PM, Tokunori Ikegami wrote:
[...]
> In function do_write_buffer(), in the for loop, there is a
> case chip_ready() returns 1 while chip_good() returns 0, so
> it never break the loop.
> To fix this, chip_good() is enough and it should timeo
Hi Tudor,
On 15/04/19 1:43 PM, tudor.amba...@microchip.com wrote:
> Hi,
>
> The general approach looks good, few comments below.
>
> On 04/09/2019 07:26 PM, Vignesh Raghavendra wrote:
>> External E-Mail
>>
>>
>> From: Boris Brezillon
>>
>> The
On 14/04/19 11:25 PM, Sergei Shtylyov wrote:
> On 04/12/2019 12:29 PM, Vignesh Raghavendra wrote:
>
>> Add binding documentation for TI's HyperBus memory controller present on
>> AM654 SoC.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> ...
Hi,
On 14/04/19 11:21 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 04/12/2019 12:29 PM, Vignesh Raghavendra wrote:
>
>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>> Bus interface between a host system master and one or more slave
>&
Hi Sergei,
On 12/04/19 2:59 PM, Vignesh Raghavendra wrote:
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for HyperFlash
mtd: Add support for HyperBus memory devices
dt-bindings: mtd: Add bindings
Each clock node will be child of the syscon node describing offset and
bit within the regmap that controls the clock output.
Vignesh Raghavendra (2):
dt-bindings: clock: Add binding documentation for TI syscon gate clock
clk: keystone: Add new driver to handle syscon based clock
.../binding
con regmap. Each clock node will be child of the
syscon node.
Signed-off-by: Vignesh Raghavendra
---
drivers/clk/keystone/Kconfig | 8 ++
drivers/clk/keystone/Makefile | 1 +
drivers/clk/keystone/syscon-clk.c | 143 ++
3 files changed, 152 insertions(+)
c
Add dt bindings for TI syscon gate clock.
Signed-off-by: Vignesh Raghavendra
---
.../bindings/clock/ti,syscon-gate-clock.txt | 35 +++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt
diff --git a
desired.
Fixes: 38dabd91ff0b ("pwm: tiehrpwm: Fix disabling of output of PWMs")
Signed-off-by: Christoph Vogtländer
[vigne...@ti.com: Improve commit message]
Signed-off-by: Vignesh Raghavendra
---
drivers/pwm/pwm-tiehrpwm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drive
Add a new compatible string "ti,am654-ehrpwm" to support EHRPWM IP on
TI AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehr
K3 devices have the same EHRPWM IP as OMAP SoCs. Enable driver to be built
for K3 devices. Also, drop reference to AM33xx in help text, as IP is
found on multiple TI SoCs.
Signed-off-by: Vignesh Raghavendra
---
drivers/pwm/Kconfig | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
This series adds support for EHRPWM IP on TI AM654 SoC
Vignesh Raghavendra (2):
dt-bindings: pwm: tiehrpwm: Add TI AM654 SoC specific compatible
pwm: Kconfig: Enable ehrpwm driver to be compiled for ARCH_K3
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 1 +
drivers/pwm/Kconfig
Hi,
On 11/03/19 10:02 AM, Naga Sureshkumar Relli wrote:
> Hi Vignesh,
>
>> -Original Message-
>> From: linux-spi-ow...@vger.kernel.org On
>> Behalf Of
>> Vignesh Raghavendra
>> Sent: Friday, March 8, 2019 10:20 AM
>> To: Naga Sureshku
On 26/03/19 8:50 PM, Liu Xiang wrote:
> At 2019-03-19 13:22:15, "Vignesh Raghavendra" wrote:
>> Hi,
>>
>> On 13/03/19 7:15 PM, Liu Xiang wrote:
>>> In some is25lp256, the DWORD1 of JEDEC Basic Flash Parameter Header
>>> is 0xfff920e5. So the DWO
Hi,
On 01/04/19 10:19 AM, Andrey Smirnov wrote:
> Spi_nor_read() already has an appropriate loop around .read() callback
> to handle the case when not all of the data requested was written in a
> signle ->read() call. Drop extra code doing the same thing in
> m25p80_read().
>
Thanks for the patc
On 25/03/19 10:54 PM, Joakim Tjernlund wrote:
> On Mon, 2019-03-25 at 22:36 +0530, Vignesh Raghavendra wrote:
>>
>> On 25/03/19 7:21 PM, Joakim Tjernlund wrote:
>>> On Mon, 2019-03-25 at 18:27 +0530, Vignesh Raghavendra wrote:
>>>> CAUTION: This email origina
Hi Rob,
On 28/03/19 6:01 PM, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 02:35:17PM +0530, Vignesh Raghavendra wrote:
>> Add dt bindings for TI syscon gate clock.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> .../bindings/clock/ti,syscon-gate-clock.txt
On 08/04/19 10:20 PM, Dinh Nguyen wrote:
> Get the reset control for the QSPI controller and bring it out of reset.
>
> Suggested-by: Tien-Fong Chee
> Signed-off-by: Dinh Nguyen
> ---
> drivers/mtd/spi-nor/cadence-quadspi.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
This is repost of patch 6 and 7 split from from Boris Brezillon's X-X-X
mode support series[1]
Background from cover letter for RFC[1]:
m25p80 is just a simple SPI NOR controller driver (a wrapper around the
SPI mem API). Not only it shouldn't be named after a specific SPI NOR
chip, but it also do
spi_mem_supports_op() when
nor->spimem != NULL.
Signed-off-by: Boris Brezillon
Signed-off-by: Vignesh Raghavendra
---
Chagnes wrt RFC:
Fix checkpatch issues
Rebase onto latest
drivers/mtd/spi-nor/spi-nor.c | 164 ++
include/linux/mtd/spi-nor.h | 14 +++
2 fi
On 08/04/19 8:09 PM, Yue Haibing wrote:
> From: YueHaibing
>
> When building with CONFIG_SPI_MEM is not set
> gc warns this:
>
> drivers/spi/spi-zynq-qspi.o: In function `zynq_qspi_supports_op':
> spi-zynq-qspi.c:(.text+0x1da): undefined reference to
> `spi_mem_default_supports_op'
>
> Fixes:
y the MTD layer.
Signed-off-by: Boris Brezillon
[vigne...@ti.com: use devm_kmalloc() for bounce buffer allocation]
Signed-off-by: Vignesh Raghavendra
---
Changes from RFC:
* Use devm_kmalloc() for bounce buffer allocation as it supports cache
line aligned buffers now
* Rebase onto latest next
On 26/02/19 11:46 PM, Sergei Shtylyov wrote:
> On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon
> ) wrote:
>
>> Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
>> interface between a host system master and one or more slave interfaces.
>> HyperBus is use
On 27/02/19 3:29 PM, Boris Brezillon wrote:
> On Wed, 27 Feb 2019 15:22:19 +0530
> Vignesh Raghavendra wrote:
>
>> On 26/02/19 11:46 PM, Sergei Shtylyov wrote:
>>> On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon
>>> ) wrote:
>>>
>
ash these when you post new version:
Sorry for not noticing earlier.
-- >8 --
>From 69f3a1ff1ea0777f5deceefdb0e79ce625e6488a Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra
Date: Fri, 12 Feb 2021 19:34:46 +0530
Subject: [PATCH 1/2] fixup! net: switchdev: propagate extack to port
attributes
Register netdevice notifiers in order to receive notification when
individual MAC ports are added to the HW bridge.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 130 ++-
drivers/net/ethernet/ti/am65-cpsw-nuss.h | 4 +
2 files changed
reconfiguration, therefore is easier to be made as part of mode change
devlink hooks. It also allows to keep user interface similar to what
was implemented for the previous generation of TI CPSW IP
(on AM33/AM43/AM57 SoCs).
Signed-off-by: Vignesh Raghavendra
---
.../devlink/am65-nuss-cpsw-switch.rst
FLAGS
- SWITCHDEV_ATTR_ID_PORT_STP_STATE
- SWITCHDEV_OBJ_ID_PORT_VLAN
- SWITCHDEV_OBJ_ID_PORT_MDB
- SWITCHDEV_OBJ_ID_HOST_MDB
Hence AM65 CPSW switchdev driver supports:
- FDB offloading
- MDB offloading
- VLAN filtering and offloading
- STP
Signed-off-by: Vignesh Raghav
J721e, J7200 and AM64 have multi port switches which can work in multi
mac mode and in switch mode. Add documentation explaining how to use
different modes.
Borrowed from:
Documentation/networking/device_drivers/ethernet/ti/cpsw_switchdev.rst
Signed-off-by: Vignesh Raghavendra
This series adds switchdev support for AM65 CPSW NUSS driver to support
multi port CPSW present on J721e and AM64 SoCs.
It adds devlink hook to switch b/w switch mode and multi mac mode.
v2:
Rebased on latest net-next
Update patch 1/4 with rationale for using devlink
Vignesh Raghavendra (4
On 30/05/20 7:20 pm, tudor.amba...@microchip.com wrote:
> Hi, Vignesh,
>
> On Tuesday, May 26, 2020 12:36:03 PM EEST Vignesh Raghavendra wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> From: Ramuthev
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/m
or: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (6):
mtd: spi-nor: cadence-quadspi: Make driver independent of flash
geometry
mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode
mtd: spi-nor: cad
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
: Vignesh Raghavendra
---
.../mtd/spi-nor/controllers/cadence-quadspi.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
index 608ca657ff7f..0570ebca135a
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor
goto probe_setup_failed;
+ }
+
+ ret = devm_spi_register_master(dev, master);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
+ goto probe_setup_failed;
+ }
+
+ return 0;
probe_setup_failed:
cqspi_controller_enable(cqspi, 0);
probe_reset_failed:
@@ -1409,17 +1318,14 @@ static int cqspi_probe(struct platform_device *pdev)
probe_clk_failed:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
+probe_master_put:
+ spi_master_put(master);
return ret;
}
static int cqspi_remove(struct platform_device *pdev)
{
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
- if (cqspi->f_pdata[i].registered)
- mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
cqspi_controller_enable(cqspi, 0);
@@ -1462,17 +1368,15 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#endif
static const struct cqspi_driver_platdata cdns_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
static const struct cqspi_driver_platdata k2g_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
static const struct cqspi_driver_platdata am654_ospi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
@@ -1511,3 +1415,5 @@ MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" CQSPI_NAME);
MODULE_AUTHOR("Ley Foon Tan ");
MODULE_AUTHOR("Graham Moore ");
+MODULE_AUTHOR("Vadivel Murugan R ");
+MODULE_AUTHOR("Vignesh Raghavendra ");
--
2.26.2
his is in preparation to move to spi-mem framework
where flash geometry cannot be known.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-
Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
of sending WREN command before sending erase command.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/mtd/spi-nor
sending WREN, there
is no need to configure these fields either.
Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
.../mtd/spi-nor/controllers
sending WREN, there
is no need to configure these fields either.
Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
.../mtd/spi-nor/controllers
Make sure to undo the prior changes done by the driver when exiting due
to failure to acquire reset lines.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
var Vadivel Murugan (2):
mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (6):
mtd: spi-nor: cadence-quadspi: Make driver independent of flash
geometry
mtd: spi-nor: cadence-quadspi: Provide a way to d
: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
.../mtd/spi-nor/controllers/cadence-quadspi.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
index
Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care
of sending WREN command before sending erase command.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 5 deletions(-)
diff
his is in preparation to move to spi-mem framework
where flash geometry cannot be known.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-
If driver fails to acquire DMA channel then don't initialize
rx_dma_complete struct as it won't be used.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/controllers/cadence-quadspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/m
et == -EPROBE_DEFER)
+ goto probe_setup_failed;
+ }
+
+ ret = devm_spi_register_master(dev, master);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
+ goto probe_setup_failed;
+ }
+
+ return 0;
probe_setup_failed:
cqspi_controller_enable(cqspi, 0);
probe_reset_failed:
@@ -1409,17 +1318,14 @@ static int cqspi_probe(struct platform_device *pdev)
probe_clk_failed:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
+probe_master_put:
+ spi_master_put(master);
return ret;
}
static int cqspi_remove(struct platform_device *pdev)
{
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
- if (cqspi->f_pdata[i].registered)
- mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
cqspi_controller_enable(cqspi, 0);
@@ -1462,17 +1368,15 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#endif
static const struct cqspi_driver_platdata cdns_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
static const struct cqspi_driver_platdata k2g_qspi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
static const struct cqspi_driver_platdata am654_ospi = {
- .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
.quirks = CQSPI_NEEDS_WR_DELAY,
};
@@ -1511,3 +1415,5 @@ MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" CQSPI_NAME);
MODULE_AUTHOR("Ley Foon Tan ");
MODULE_AUTHOR("Graham Moore ");
+MODULE_AUTHOR("Vadivel Murugan R ");
+MODULE_AUTHOR("Vignesh Raghavendra ");
--
2.26.2
From: Ramuthevar Vadivel Murugan
Now that cadence-quadspi has been converted to use spi-mem framework,
move it under drivers/spi/
Update license header to match SPI subsystem style
Signed-off-by: Ramuthevar Vadivel Murugan
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
On 01/06/20 12:30 pm, tudor.amba...@microchip.com wrote:
> Hi, Mark,
>
> On Monday, June 1, 2020 8:47:25 AM EEST Vignesh Raghavendra wrote:
>> From: Ramuthevar Vadivel Murugan
>>
>>
>> Now that cadence-quadspi has been converted to use spi-mem framew
J7200 has 7 I2Cs main domain, 2 I2Cs in MCU and one in wakeup domain.
Add DT nodes of the same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 77 +++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33
2 files changed, 110
Add I2C and I2C IO expanders nodes for J7200
Based on top of
https://lore.kernel.org/linux-arm-kernel/20200723084628.19241-1-lokeshvu...@ti.com/
Vignesh Raghavendra (2):
arm64: dts: ti: j7200: Add I2C nodes
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
.../dts/ti/k3
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-off-by: Vignesh Raghavendra
---
.../dts/ti/k3-j7200-common-proc-board.dts | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64
J7200 SoM has a HyperFlash connected to HyperBus memory controller. But
HyperBus is muxed with OSPI, therefore keep HyperBus node disabled.
Bootloader will detect the mux and enable the node as required.
Signed-off-by: Vignesh Raghavendra
---
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36
This series adds HyperBus and HyperFlash nodes for TI's J7200 SoC
Based on top of
https://lore.kernel.org/linux-arm-kernel/20200723084628.19241-1-lokeshvu...@ti.com/
And earlier I2C DT patches:
https://lore.kernel.org/linux-arm-kernel/20200730192600.1872-1-vigne...@ti.com/
Vignesh Raghav
J7200 has a Flash SubSystem that has one OSPI and one HyperBus.. Add
DT nodes for HyperBus controller for now.
Signed-off-by: Vignesh Raghavendra
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 27 +++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 8 --
2 files
ed, 157 insertions(+), 44 deletions(-)
>
For the series:
Reviewed-by: Vignesh Raghavendra
Regards
Vignesh
On 1/7/21 10:09 PM, Aswath Govindraju wrote:
> Fix module autoprobe by correcting module alias to match the string from
> /sys/class/.../spi1.0/modalias content.
>
> Fixes: 06b4501e88ad ("misc/eeprom: add driver for microwire 93xx46 EEPROMs")
> Signed-off-by: Aswath Govindraju
> ---
> drivers
m/lit/er/sprz360i/sprz360i.pdf
> Fixes: 61929cf0169d ("tty: serial: Add 8250-core based omap driver")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Alexander Sverdlin
Thanks for the fix.
Reviewed-by: Vignesh Raghavendra
> ---
> drivers/tty/serial/8250/8250_omap.c | 5 -
her
parameter tables are parsed.
Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table")
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi-nor/sfdp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c
Hi Xiaoming,
On 12/7/20 4:23 PM, Miquel Raynal wrote:
> Hi Xiaoming,
>
> Xiaoming Ni wrote on Mon, 7 Dec 2020 18:48:33
> +0800:
>
>> ping
>>
>> On 2020/11/27 21:07, Xiaoming Ni wrote:
>>> When CONFIG_MTD_XIP=y, local_irq_disable() is called in xip_disable().
>>> To avoid sleep in interrupt cont
On Mon, 30 Nov 2020 16:24:15 +0100, Jonathan Neuschäfer wrote:
> There are a few typos in comments in the SPI NOR framework; fix them.
Addressed Tudor's comments locally.
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git
spi-nor/next, thanks!
[1/1] mtd: spi-nor: Fix multip
Hi Pratyush,
On 12/1/20 3:57 PM, Pratyush Yadav wrote:
> Some flashes like the Cypress S28 family use ECC. Under this ECC scheme,
> multi-pass writes to an ECC block is not allowed. In other words, once
> data is programmed to an ECC block, it can't be programmed again without
> erasing it first.
On 12/1/20 3:57 PM, Pratyush Yadav wrote:
> The S28 flash family uses 2-bit ECC by default with each ECC block being
> 16 bytes. Under this scheme multi-pass programming to an ECC block is
> not allowed. Set the writesize to make sure multi-pass programming is
> not attempted on the flash.
>
>
annel TPL
handling")
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 298460438bb4..a1af59d901be 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
D-8D-8D mode should be at least twice as fast as
> 1S-1S-8S mode.
>
> Signed-off-by: Pratyush Yadav
> ---
>
Reviewed-by: Vignesh Raghavendra
> Notes:
> No changes in v2.
>
> arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++--
> 1 file changed, 2 insertions
D-8D-8D mode should be at least twice as fast as
> 1S-1S-8S mode.
>
> Signed-off-by: Pratyush Yadav
> ---
>
Reviewed-by: Vignesh Raghavendra
> Notes:
> No changes in v2.
>
> arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
> 1 file changed, 2 inser
On 3/5/21 9:09 PM, Pratyush Yadav wrote:
> TI J7200 has the Cadence OSPI controller for interfacing with OSPI
> flashes. Add its node to allow using SPI flashes.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
>
> Notes:
> Changes in
On 2/12/21 1:02 AM, Jan Kiszka wrote:
> From: Jan Kiszka
>
> These boards are based on AM6528 GP and AM6548 HS SOCs.
>
> Signed-off-by: Jan Kiszka
Reviewed-by: Vignesh Raghavendra
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 2 ++
> 1 fi
emens/meta-iot2050
> Signed-off-by: Jan Kiszka
Reviewed-by: Vignesh Raghavendra
Few minor comments below:
[...]
> +
> +&mcu_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_i2c0_pins_default>;
> + clock-frequency = <40>;
Hi Colin King,
On Thu, 25 Mar 2021 17:45:14 +, Colin King wrote:
> The variable timeo is being initialized with a value that is never read
> and it is being updated later with a new value. The initialization is
> redundant and can be removed.
Fixed up $subject prefix to match existing conven
Hi,
On 3/18/21 2:54 PM, Michael Walle wrote:
> Add support to show the name and JEDEC identifier as well as to dump the
> SFDP table. Not all flashes list their SFDP table contents in their
> datasheet. So having that is useful. It might also be helpful in bug
> reports from users.
>
Sorry for t
On 4/6/21 2:17 PM, Michael Walle wrote:
> Hi,
>
> Am 2021-04-06 09:56, schrieb Vignesh Raghavendra:
>> Hi,
>>
>> On 3/18/21 2:54 PM, Michael Walle wrote:
>>> Add support to show the name and JEDEC identifier as well as to dump the
>>> SFDP table. N
runtime
> PM counter on error.
>
> Signed-off-by: Dinghao Liu
> ---
Do we need a Fixes: tag to enable stable backports?
Reviewed-by: Vignesh Raghavendra
> drivers/i2c/busses/i2c-omap.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers
Hi,
On 4/7/21 11:57 AM, Tony Lindgren wrote:
> * Vignesh Raghavendra [210407 06:20]:
>> Do we need a Fixes: tag to enable stable backports?
>
> Well pm_runtime_resume_and_get() was introduced quite recently, and
> we already handle the error and bail out. And likely after a
On 3/26/21 6:30 PM, Pratyush Yadav wrote:
> The TI specific compatible should be followed by the generic
> "cdns,qspi-nor" compatible.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi |
On 3/26/21 6:30 PM, Pratyush Yadav wrote:
> The TI specific compatible should be followed by the generic
> "cdns,qspi-nor" compatible.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
On 3/26/21 6:30 PM, Pratyush Yadav wrote:
> The TI specific compatible should be followed by the generic
> "cdns,qspi-nor" compatible.
>
> Signed-off-by: Pratyush Yadav
> ---
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +-
&g
On 3/29/21 11:52 PM, Pratyush Yadav wrote:
>>> + cdns,fifo-depth:
>>> +description:
>>> + Size of the data FIFO in words.
>>> +$ref: "/schemas/types.yaml#/definitions/uint32"
>>> +enum: [ 128, 256 ]
>>> +default: 128
>>> +
>>> + cdns,fifo-width:
>>> +$ref: /schemas/typ
On 3/17/21 2:35 PM, Pratyush Yadav wrote:
> On 17/03/21 06:09AM, tudor.amba...@microchip.com wrote:
>> On 3/15/21 8:23 AM, Vignesh Raghavendra wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>>> content is safe
>>>
k3-am642-sk.dts file.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Lokesh Vutla
---
Rebase onto latest k3-dts-next:
v1: lore.kernel.org/r/20210309130708.12391-1-vigne...@ti.com
Do note that dtbs_check warns about having the bindings converted to
YAML which is in my future TODO list.
arch
AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
(FSS). Add DT entry for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
---
Rebase onto latest k3-dts-next
v1: lore.kernel.org/r/20210309130514.11740-1-vigne...@ti.com
arch/arm64/boot/dts/ti/k3
Both AM64 EVM and SK have a 512Mb S28HS512T Octal SPI NOR flash.
Add DT node for the same.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Pratyush Yadav
---
Boot logs:
https://pastebin.ubuntu.com/p/VsMmyWk5SX/
https://pastebin.ubuntu.com/p/KFcMwSGxr5/
Resend:
Rebase onto latest -next
There
Hi.
On 4/8/21 6:26 PM, Li Huafei wrote:
> pm_runtime_get_sync will increment pm usage counter even it failed.
> Forgetting to putting operation will result in reference leak here. Fix
> it by replacing it with pm_runtime_resume_and_get to keep usage counter
> balanced.
>
> Reported-by: Hulk Robot
Hi Michael,
On Thu, 3 Dec 2020 17:29:52 +0100, Michael Walle wrote:
> I bundled this as a series, because otherwise there will be conflicts
> because the "remove global protection flag" patches modify the same lines
> as the main patch.
>
> There are now two more patches:
> mtd: spi-nor: sst: f
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> Add QSPI controller support for Intel LGM SoC.
>
> Note from Vignesh(mtd subsystem maintainer):
> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
> support for the Cadence QSPI controller" by Ramuthevar,Vadivel Mur
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan
>
> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.
>
> Signed-off-by: Ramuthevar Vadivel Murugan
>
> ---
> drivers/spi/spi-cadence-quadspi.c | 15 +
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> Add QSPI controller support for Intel LGM SoC.
>
> Note from Vignesh(mtd subsystem maintainer):
> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
> support for the Cadence QSPI controller" by Ramuthevar,Vadivel Mur
xpander on SOM that's missing from DT
today. So this change looks good to me.
Reviewed-by: Vignesh Raghavendra
Regards
Vignesh
> .../dts/ti/k3-j7200-common-proc-board.dts | 11
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 26 +++
> 2 files chan
p3 and at the same time add the
> line names as well.
>
> Signed-off-by: Peter Ujfalusi
> ---
Yes, the schematics call this expander as exp3. Thanks for the fix
Reviewed-by: Vignesh Raghavendra
> arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 5 -
> 1 file
AM65 NUSS ethernet switch on K3 devices can be configured to work either
in independent mac mode where each port acts as independent network
interface (multi mac) or switch mode.
Add devlink hooks to provide a way to switch b/w these modes.
Signed-off-by: Vignesh Raghavendra
---
.../devlink
This series adds switchdev support for AM65 CPSW NUSS driver to support
multi port CPSW present on J721e and AM64 SoCs.
It adds devlink hook to switch b/w switch mode and multi mac mode.
Vignesh Raghavendra (4):
net: ti: am65-cpsw-nuss: Add devlink support
net: ti: am65-cpsw-nuss: Add
Register netdevice notifiers in order to receive notification when
individual MAC ports are added to the HW bridge.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 130 ++-
drivers/net/ethernet/ti/am65-cpsw-nuss.h | 4 +
2 files changed
J721e, J7200 and AM64 have multi port switches which can work in multi
mac mode and in switch mode. Add documentation explaining how to use
different modes.
Borrowed from:
Documentation/networking/device_drivers/ethernet/ti/cpsw_switchdev.rst
Signed-off-by: Vignesh Raghavendra
FLOOD
- SWITCHDEV_ATTR_ID_PORT_STP_STATE
- SWITCHDEV_OBJ_ID_PORT_VLAN
- SWITCHDEV_OBJ_ID_PORT_MDB
- SWITCHDEV_OBJ_ID_HOST_MDB
Hence AM65 CPSW switchdev driver supports:
- FDB offloading
- MDB offloading
- VLAN filtering and offloading
- STP
Signed-off-by: Vi
below, for pm_runtime of 'pdev->dev' should
> be disabled when pm_runtime_resume_and_get fails.
>
> Fixes: 3b0fb97c8dc4 ("I2C: OMAP: Handle error check for pm runtime")
> Reported-by: Hulk Robot
> Signed-off-by: Qinglang Miao
> ---
Reviewed-by: Vignesh Ra
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