n 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Use block IP version for operations
dt-bindings: pci: qcom: Add support for IPQ8074
PCI: dwc: qcom: Add support f
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 132 +++-
1 file
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 233
1 file changed, 233 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index c4cd039..5bfbbd3 100644
--- a/drivers
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
Stanimir,
> Hi,
>
> Thanks for the patch.
>
> On 31.07.2017 09:34, Varadarajan Narayanan wrote:
> >Add support for the IPQ8074 PCIe controller. IPQ8074 supports
> >Gen 1/2, one lane, two PCIe root complex with support for MSI and
> >legacy interrupts, and it
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 208
1 file changed, 208 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index c4cd039..1cb03dd 100644
--- a/drivers
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 132 +++-
1 file
equired to enable QMP phy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (3):
PCI: dwc: qcom: Us
d deinit if phy power on fails
v1:
Add definitions required to enable QMP phy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specificati
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Acked-by: Stanimir Varbanov
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 138
.
Acked-by: Stanimir Varbanov
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 210 +++-
1 file changed, 209 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci
On Fri, Aug 18, 2017 at 12:59:50PM +0530, Varadarajan Narayanan wrote:
> v9:
> Incorporate Stanimir's feedback for
> PCI: dwc: qcom: Add support for IPQ8074 PCIe controller
Forgot to mention that the patches were rebased against
Bjorn's pci.git/next.
Thanks
Varada
>
it for QUP versions later than v1.
Signed-off-by: Sham Muthayyan
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 1bfa889..c0d4def 100644
--- a/drivers/spi
To operate in DMA mode, the buffer should be aligned and
the size of the transfer should be a multiple of block size
(for v1). And the no. of words being transferred should
be programmed in the count registers appropriately.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
and the driver quietly fails. Patches 12 - 18 add support for this
in both interrupt and dma mode.
The entire series has been tested on ipq4019 with
SPI-NOR flash for block sizes > 64k.
Varadarajan Narayanan (15):
spi: qup: Enable chip select support
spi: qup:
Use different 'completion' structures to track the completion
of DMA Tx/Rx and PIO.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drive
Much like the block mode changes, we are breaking up DMA transactions
into 64K chunks so we can reset the QUP engine.
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 104 --
1 file changed, 76
Take specific sgl and nent to be prepared. This is in
preparation for splitting DMA into multiple transacations, this
contains no code changes just refactoring.
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 25 ++---
1
-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/spi/qcom,spi-qup.txt | 6
drivers/spi/spi-qup.c | 35 +-
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree
: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index a39a0d2..ca5206e 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -268,7 +268,7 @@ static void
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 128 +++---
1 file changed, 80 insertions(+), 48 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 37b51e3..026f25e 100644
--- a/drivers/spi/spi-qup.c
+++ b/dri
no functional change
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index bfb6d27..37b51e3 100644
--- a
refactoring, there should be no functional
change
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 109 +++---
1 file changed, 67 insertions(+), 42 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers
This patch corrects the behavior of the BLOCK
transactions. During block transactions, the controller
must be read/written to in block size transactions.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 151
sets controller->xfer = NULL and
restores it in the ISR. This looks to be some debug code which is not
required.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 27 +--
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 0683e47..e2b4a50 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -310,8 +310,8 @@ static
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index d3ccf53..0683e47 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
Add i/o completion timeout for DMA and PIO modes.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 59e799f
On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Varadarajan Narayanan
On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
+enum ipq8074_functions {
Please keep these sorted alphabetically.
Ok
On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
+enum ipq8074_functions
On Sat, Dec 26, 2020 at 01:51:28AM +0100, Konrad Dybcio wrote:
Konrad,
> Hi, are you going to resubmit this patch? Looks like
> MDM9607 uses Stromer PLL for its CPU clocks and could
> benefit from it.
Yes. But will take some time since we are held up with
additional activities.
Thanks
Varada
-
On Mon, Aug 24, 2015 at 03:49:28PM -0700, Stephen Boyd wrote:
> On 08/24, Varadarajan Narayanan wrote:
> > Add initial dts files and SoC support for IPQ40XX
> >
>
> So far we haven't added any Xs in the model names for our SoC
> support. Even for IPQ806X, we have it as
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
Changes in v2:
- Added devicetree bindings documentation
Changes in v3:
- Split 'gcnt' into a separate patch
- Added the new entries to Makefiles, Kconfig & board.c in sorted order
On Tue, Aug 25, 2015 at 02:14:05PM -0700, Stephen Boyd wrote:
> On 08/25, Varadarajan Narayanan wrote:
> > On Mon, Aug 24, 2015 at 03:49:28PM -0700, Stephen Boyd wrote:
> > > On 08/24, Varadarajan Narayanan wrote:
> >
> > > > + compatible
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
Changes in v2:
- Added devicetree bindings documentation
Changes in v3:
- Split 'gcnt' into a separate patch
- Added the new entries to Makefiles, Kconfig & board.c in sorted order
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
All,
Missed linux-arm-msm mailing list last time and
incorrectly versioned the patch as v5.
Kindly excuse.
Changes in v2:
- Added devicetree bindings documentation
Changes in v3
:
Error: invalid constant (1508000) after fixup
Hence, cannot use Linux's self extractor. Instead, create a compressed
image that will be de-compressed from U-Boot.
Signed-off-by: Varadarajan Narayanan
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 07ab3d2..cc
ged, 21 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>
NAND, BAM and SPI work fine.
Tested-by: Varadarajan Narayanan
-Varada
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ade7a38..b6c62c6 100644
> --- a/arch/a
On Thu, Aug 20, 2015 at 08:54:55PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 20, 2015 at 12:20:10PM -0500, Andy Gross wrote:
> > On Thu, Aug 20, 2015 at 02:00:06PM +0100, Russell King - ARM Linux wrote:
> > > On Thu, Aug 20, 2015 at 05:45:41PM +0530, Varadaraj
Add initial dts files and SoC support for IPQ40XX
Signed-off-by: Varadarajan Narayanan
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 246473a..6b4caee 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -477,7 +477,8 @@ dtb-$(CONFIG_ARCH_QCOM
On Fri, Aug 21, 2015 at 02:50:35PM +0530, Varadarajan Narayanan wrote:
> Add initial dts files and SoC support for IPQ40XX
Please ignore this. Missed the Devicetree bindings documentation.
Will post a revised patch.
Thanks
Varada
> Signed-off-by: Varadarajan Narayanan
>
> diff
Add initial dts files and SoC support for IPQ40XX
Signed-off-by: Varadarajan Narayanan
---
Changes in v2:
- Added devicetree bindings documentation
.../devicetree/bindings/clock/qca,gcnt.txt | 14
Documentation/devicetree/bindings/ipq.txt | 16
arch/arm/boot/dts
On Fri, Aug 21, 2015 at 09:21:33AM -0700, Bjorn Andersson wrote:
> On Fri 21 Aug 03:32 PDT 2015, Varadarajan Narayanan wrote:
>
> > Add initial dts files and SoC support for IPQ40XX
> >
> > Signed-off-by: Varadarajan Narayanan
> > ---
> > Changes in v
Add initial dts files and SoC support for IPQ40XX
Signed-off-by: Varadarajan Narayanan
---
Changes in v2:
- Added devicetree bindings documentation
Changes in v3:
- Split 'gcnt' into a separate patch
- Added the new entries to Makefiles, Kconfig & board.c in sorted order
Adding the dt data for the 56 global counter which supplies
the count to the arm arch timers.
Signed-off-by: Varadarajan Narayanan
---
> Refer http://www.spinics.net/lists/linux-arm-msm/msg16660.html
>
> On Fri, Aug 21, 2015 at 09:21:33AM -0700, Bjorn Andersson
> wrote:
>
>
The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq5018-mp03.1-c2 board.
Varadarajan Narayanan (7):
clk: qcom: clk-alpha-pll: Add support for Stromer PLLs
dt-bindings: arm64: ipq5018: Add binding description
Add support for the global clock controller found on IPQ5018
based devices.
Signed-off-by: Varadarajan Narayanan
---
drivers/clk/qcom/Kconfig |8 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq5018.c | 3833
include/linux
Add device tree binding Documentation details for ipq5018
pinctrl driver.
Signed-off-by: Varadarajan Narayanan
---
.../bindings/pinctrl/qcom,ipq5018-pinctrl.yaml | 143 +
1 file changed, 143 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl
This adds the pinctrl definitions for the TLMM of IPQ5018.
Signed-off-by: Varadarajan Narayanan
---
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 903 +
3 files changed
Add programming sequence support for managing the Stromer
PLLs.
Signed-off-by: Varadarajan Narayanan
---
drivers/clk/qcom/clk-alpha-pll.c | 156 ++-
drivers/clk/qcom/clk-alpha-pll.h | 5 ++
2 files changed, 160 insertions(+), 1 deletion(-)
diff --git a
Enables clk & pinctrl related configs
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6d04b95..ca25f79 100644
--- a/arch/arm64/configs/defconfig
+
This patch adds support for the global clock controller found on
the IPQ5018 based devices.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/clock/qcom,gcc.yaml| 3 +
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +
include/dt-bindings
Add initial device tree support for the Qualcomm IPQ5018 SoC and
MP03.1-C2 board.
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30
On Mon, Sep 28, 2020 at 01:43:22PM -0500, Bjorn Andersson wrote:
> On Mon 28 Sep 00:15 CDT 2020, Varadarajan Narayanan wrote:
> > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c
> > b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
> [..]
> > +static const struct msm_fu
On Mon, Sep 28, 2020 at 01:10:18PM -0500, Rob Herring wrote:
> On Mon, 28 Sep 2020 10:45:37 +0530, Varadarajan Narayanan wrote:
> > Add device tree binding Documentation details for ipq5018
> > pinctrl driver.
> >
> > Signed-off-by: Varadarajan Narayanan
> > -
Varadarajan Narayanan (3):
pinctrl: qcom: Add ipq8074 pinctrl driver
dt-bindings: qcom: Add IPQ8074 bindings
arm64: dts: Add ipq8074 SoC and MTP board support
Documentation/devicetree/bindings/arm/qcom.txt |2 +
.../devicetree/bindings/clock/qcom,gcc.txt |1
Add initial device tree support for the Qualcomm IPQ8074 SoC and
HK01 evaluation board.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Varadarajan Narayanan
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 202
drivers/pinctrl/qcom/Kconfig
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b/Documentation/devicetree/bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
--- a/Documentation
From: Abhishek Sahu
This patch adds support for the global clock controller found on
the IPQ8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/clock/qcom,gcc.txt |1 +
drivers/clk
From: Abhishek Sahu
These configs are required for booting kernel in QCOM
IPQ8074 boards.
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs
Rob,
On Fri, Jun 23, 2017 at 04:49:23PM -0500, Rob Herring wrote:
> On Tue, Jun 20, 2017 at 02:40:57PM +0530, Varadarajan Narayanan wrote:
> > Currently the QUP Version v1 does not work with DMA so added
> > the support for the same.
> >
> > 1. It uses ADM DMA which re
ested on ipq4019 with
SPI-NOR flash for block sizes > 64k.
Varadarajan Narayanan (14):
spi: qup: Enable chip select support
spi: qup: Setup DMA mode correctly
spi: qup: Add completion structures for DMA
spi: qup: Add completion timeout
spi: qup: Place the QUP in run mode before D
Use different 'completion' structures to track the completion
of DMA Tx/Rx and PIO.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drive
sets controller->xfer = NULL and
restores it in the ISR. This looks to be some debug code which is not
required.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 27 +--
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a
To operate in DMA mode, the buffer should be aligned and
the size of the transfer should be a multiple of block size
(for v1). And the no. of words being transferred should
be programmed in the count registers appropriately.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
it for QUP versions later than v1.
Signed-off-by: Sham Muthayyan
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 1bfa889..c0d4def 100644
--- a/drivers/spi
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 0683e47..e2b4a50 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -310,8 +310,8 @@ static
no functional change
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index bfb6d27..37b51e3 100644
--- a
This patch corrects the behavior of the BLOCK
transactions. During block transactions, the controller
must be read/written to in block size transactions.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 151
: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index a39a0d2..ca5206e 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -268,7 +268,7 @@ static void
Much like the block mode changes, we are breaking up DMA transactions
into 64K chunks so we can reset the QUP engine.
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 104 --
1 file changed, 76
Take specific sgl and nent to be prepared. This is in
preparation for splitting DMA into multiple transacations, this
contains no code changes just refactoring.
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 25 ++---
1
refactoring, there should be no functional
change
Signed-off-by: Matthew McClintock
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 109 +++---
1 file changed, 67 insertions(+), 42 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 128 +++---
1 file changed, 80 insertions(+), 48 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 37b51e3..026f25e 100644
--- a/drivers/spi/spi-qup.c
+++ b/dri
Add i/o completion timeout for DMA and PIO modes.
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 59e799f
Signed-off-by: Andy Gross
Signed-off-by: Varadarajan Narayanan
---
drivers/spi/spi-qup.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index d3ccf53..0683e47 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
On 5/18/2017 1:17 AM, Bjorn Andersson wrote:
On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
On 5/11/2017 4:13 AM, Bjorn
On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
On Thu 04 May 04:53 PDT 2017
Add initial device tree support for the Qualcomm IPQ8074 SoC and
HK01 evaluation board.
Acked-by: Bjorn Andersson
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq8074.
Acked-by: Rob Herring (bindings)
Acked-by: Bjorn Andersson
Signed-off-by: Manoharan Vijaya Raghavan
Signed-off-by: Varadarajan Narayanan
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 172
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b/Documentation/devicetree/bindings/arm/qcom.txt
index 028d16e..0ed4d39 100644
er nodes
* Fix sparse warnings in the gcc-ipq8074.c
* Updated pinctrl documentation
v1:
https://www.spinics.net/lists/kernel/msg2498734.html
This series adds minimal board boot support for ipq8074-hk01
board.
Abhishek Sahu (1):
arm64: defconfig: Enable qcom ipq8074 clock and pinctrl
V
From: Abhishek Sahu
These configs are required for booting kernel in qcom
ipq8074 boards.
Acked-by: Bjorn Andersson
Signed-off-by: Abhishek Sahu
Signed-off-by: Varadarajan Narayanan
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs
The node for xo and timer belong to the SoC DTS file.
Else, new board DT files may not inherit these nodes.
Signed-off-by: Varadarajan Narayanan
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 19 ---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 14 ++
2 files
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Doc
Add definitions required to enable QMP phy support for IPQ8074.
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
Varadarajan Narayanan (7
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 28 ++
1 file changed, 28 insertions(+)
diff --git a
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt
.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 259
1 file changed, 259 insertions(+)
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index d15657d..c1fa356 100644
--- a/drivers
rom the DT.
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 78ca628..97020ec 100644
--- a/d
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 135
1 file changed, 135 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
In some implementations of the QMP phy, some registers might not
be present. Provide a way identify such registers and not access
those registers.
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23 ++-
1 file changed, 14 insertions(+), 9
Bjorn,
On Mon, Jul 17, 2017 at 03:30:47PM -0700, Bjorn Andersson wrote:
> On Mon 17 Jul 05:03 PDT 2017, Varadarajan Narayanan wrote:
>
> > Presently, the phy pipe clock's name is assumed to be either
> > usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is th
On Mon, Jul 17, 2017 at 03:07:18PM -0700, Bjorn Andersson wrote:
> On Mon 17 Jul 05:04 PDT 2017, Varadarajan Narayanan wrote:
>
> > Add support for the IPQ8074 PCIe controller. IPQ8074 supports
> > Gen 1/2, one lane, two PCIe root complex with support for MSI and
> > l
On Tue, Jul 18, 2017 at 09:44:38AM -0700, Bjorn Andersson wrote:
> On Tue 18 Jul 02:58 PDT 2017, Varadarajan Narayanan wrote:
>
> > On Mon, Jul 17, 2017 at 03:07:18PM -0700, Bjorn Andersson wrote:
> > > On Mon 17 Jul 05:04 PDT 2017, Varadarajan Narayanan wrote:
> [..]
>
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertion
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