The PWM block is required for system clock source so it must be always
enabled. This patch fixes boot issues on SMDK6410 which did not have the
node enabled explicitly for other purposes.
Fixes: eeb93d02c5d8 ("clocksource: of: Respect device tree node status")
Signed-off-by: T
00a26000 2**6
25 .data 000db860 c0c22000 c0c22000 00a2a000 2**6
This series should not introduce any functional changes.
Tested on S3C6410-based Mini6410 board, booting with device tree.
Marek, Bart, could you do some testing on Exynos-based boards,
just to make sure?
Tomasz Figa
struct as const and __initconst.
Signed-off-by: Tomasz Figa
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 39 +++---
drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 12 ++---
drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 14 ++---
drivers/pinctrl/samsung/pinctrl-samsung.c | 86
There is no code using it and in fact there are pin controller variants
that do not even have this field initialized in their init data. This
patch removes it completely.
Signed-off-by: Tomasz Figa
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 22 --
drivers/pinctrl
copied to main samsung_pin_bank struct used
at runtime.
In addition, thanks to this change, all per-bank initdata can be marked
with const and __initconst keywords and dropped after init completes.
Signed-off-by: Tomasz Figa
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 44
This structure is not intended to be modified at runtime and functions
as constant data shared between multiple pin banks. This patch makes all
instances of it constant across the driver.
Signed-off-by: Tomasz Figa
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 8
drivers/pinctrl
Currently the function returns a valid pointer on success and NULL on
error, so exact error code is lost. This patch changes return convention
of the function to use ERR_PTR() on error instead.
Signed-off-by: Tomasz Figa
---
drivers/pinctrl/samsung/pinctrl-samsung.c | 6 +++---
1 file changed
On 24.09.2014 13:14, Mark Rutland wrote:
> On Wed, Sep 24, 2014 at 12:05:38PM +0100, Marek Szyprowski wrote:
>> From: Tomasz Figa
>>
>> Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
>> settings configured in registers leading to crashes i
On 25.09.2014 09:47, Linus Walleij wrote:
> On Tue, Sep 23, 2014 at 9:05 PM, Tomasz Figa wrote:
>
>> This series intends to clean up data structures used by pinctrl-samsung
>> driver.
>> More specifically, it separates initial compile time constants from data used
>&g
Hi Kukjin,
On 25.09.2014 10:26, Kukjin Kim wrote:
> On 09/25/14 17:17, Lorenzo Pieralisi wrote:
>> [CC'ed Daniel to make him aware this patch goes through your tree]
>>
> Thanks and just note the branch which is including this change actually
> v4 is just rebased not v3 will be sent out to arm-so
On 25.09.2014 10:44, Kukjin Kim wrote:
> On 09/25/14 17:28, Tomasz Figa wrote:
>> Hi Kukjin,
>>
>> On 25.09.2014 10:26, Kukjin Kim wrote:
>>> On 09/25/14 17:17, Lorenzo Pieralisi wrote:
>>>> [CC'ed Daniel to make him aware this patch goes throu
Hi Pankaj,
On 10.09.2014 07:56, Pankaj Dubey wrote:
> From: Chander Kashyap
>
> The parent name added in parent list as
> mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
> than the defined parent due to typo.
>
> Signed-off-by: Abhilash Kesavan
> Signed-off-by: Chander Kashyap
Missed
Hi Linus,
On 25.09.2014 09:49, Tomasz Figa wrote:
> On 25.09.2014 09:47, Linus Walleij wrote:
>> On Tue, Sep 23, 2014 at 9:05 PM, Tomasz Figa wrote:
>>
>>> This series intends to clean up data structures used by pinctrl-samsung
>>> driver.
>>> More
Hi Abhilash,
The patch itself seems fine, but I wonder if those config options aren't
really just leftovers from the past and couldn't be completely removed.
On 29.09.2014 07:16, Abhilash Kesavan wrote:
> From: Pankaj Dubey
>
> Exynos7 has a similar serial controller to that present in older Sa
Hi Kukjin,
On 26.08.2014 16:10, Tomasz Figa wrote:
> On Exynos-based boards running secure firmware the sequence of low level
> operations to enter and leave system-wide sleep mode is different than
> on those without the firmware. Namely:
> - CP15 power control and diagnostic regi
Russell, Olof, Kukjin,
On 26.08.2014 16:17, Tomasz Figa wrote:
> This series intends to add support for L2 cache on Exynos4 SoCs on boards
> running under secure firmware, which requires certain initialization steps
> to be done with help of firmware, as selected registers are writ
>> +static void exynos_l2_write_sec(unsigned long val, unsigned reg)
>> +{
>> +switch (reg) {
>> +case L2X0_CTRL:
>> +if (val & L2X0_CTRL_EN)
>> +exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
>
> If we're calling this with the cache already enabled, presumably yo
On 15.09.2014 11:03, Russell King - ARM Linux wrote:
>> diff --git a/arch/arm/mach-exynos/firmware.c
>> b/arch/arm/mach-exynos/firmware.c
>> index 554b350..71bcfbd 100644
>> --- a/arch/arm/mach-exynos/firmware.c
>> +++ b/arch/arm/mach-exynos/firmware.c
>> @@ -102,7 +102,9 @@ static int exynos_susp
On 17.02.2014 10:44, Naveen Krishna Chatradhi wrote:
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi
Reviewed-by: Tomasz Figa
TO:
TO: Tomasz Figa
CC: David S. Miller
CC: Kukjin Kim
CC:
---
changes since v6:
None
Hi Pankaj,
On 26.02.2014 06:24, Pankaj Dubey wrote:
add samsung common clock config option and let ARCH_EXYNOS or ARCH_S3C
select this if they want to use samsung common clock infrastructure.
CC: Mike Turquette
Signed-off-by: Pankaj Dubey
---
drivers/clk/Kconfig | 10 ++
dri
Hi Chanwoo,
On 11.03.2014 08:54, Chanwoo Choi wrote:
This patch add ADC(Analog to Digital Converter)'s dt data to get raw data
with IIO subsystem. Usually, ADC is used to check temperature, jack type, and
so on.
8< ---
Register map
- <0x126C 0x100> : ADC register's base address
- <0x100
ff-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4x12.dtsi | 6 ++
1 file changed, 6 insertions(+)
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
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Hi Chanwoo,
On 11.03.2014 08:54, Chanwoo Choi wrote:
This patch add GPS_ALIVE power domain for Exynos4x12 SoC. GPS_ALIVE power domain
include GPS_BLK for GPS IP. Exynos SoC used generic power-domain driver to
control power domain. After completed kernel booting, Exynos power-domain driver
disabl
: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4212.dtsi | 13 -
arch/arm/boot/dts/exynos4412.dtsi | 14 --
arch/arm/boot/dts/exynos4x12.dtsi | 8
3 files changed, 16 insertions(+), 19 deletions(-)
Reviewed-by: Tomasz Figa
Best
Hi Chanwoo,
On 11.03.2014 08:54, Chanwoo Choi wrote:
This patch use ADC to get the temperature of SoC/battery by using NTC thermistor
driver in hwmon. NTC thermistor driver covnvert ADC's raw data to temperature
by using following variables:
- pullup-uv: Voltage
- pullup-ohm : Pull-up res
Hi Pankaj,
On 25.04.2014 13:54, Pankaj Dubey wrote:
Add "samsung,syscon-phandle" property pointing to PMU node
to access PMU register via PMU regmap handle.
Signed-off-by: Pankaj Dubey
---
arch/arm/boot/dts/exynos5250.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot
Hi Pankaj,
On 25.04.2014 14:32, Pankaj Dubey wrote:
As machine function ops are used only in this file let's make
them static.
Signed-off-by: Pankaj Dubey
---
arch/arm/mach-exynos/exynos.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/exyn
Hi Pankaj,
On 25.04.2014 14:32, Pankaj Dubey wrote:
Remove unused and unwanted declarations from "mach-exynos/common.h"
Signed-off-by: Pankaj Dubey
---
arch/arm/mach-exynos/common.h |6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exy
-exynos/regs-sys.h | 22 ++
4 files changed, 24 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-exynos/regs-sys.h
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
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|2 --
arch/arm/mach-exynos/hotplug.c |3 +--
arch/arm/mach-exynos/include/mach/memory.h |3 +--
arch/arm/mach-exynos/platsmp.c |3 +--
4 files changed, 3 insertions(+), 8 deletions(-)
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
--
To unsubs
nos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -22,7 +22,7 @@
#include
#include
-#include "regs-pmu.h"
+#define S5P_INT_LOCAL_PWR_EN 0x7
nit: You could indent the value a bit more in case of adding any new
macros in future. While at it, you could probably also drop the
Hi Michal,
First of all, even though not touching DT bindings, this change is DT
related and so devicetree mailing list should be on Cc, as well as some
DT people, especially Grant. Adding them.
Otherwise, please see my comments inline.
On 08.04.2014 17:00, Michal Simek wrote:
Some platform
Hi,
On 25.04.2014 14:32, Pankaj Dubey wrote:
From: Young-Gun Jang
Add support for mapping Samsung Power Management Unit (PMU) base address
from device tree. Code will use existing samsung pmu binding information.
This patch also adds two helper functions as "get_exynos_pmuregmap" and
"get_exyn
-exynos/pmu.c
index 05c7ce1..4c3453a 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -11,7 +11,6 @@
#include
#include
-#include
#include
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
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Hi,
On 25.04.2014 14:32, Pankaj Dubey wrote:
Under "arm/mach-exynos" many files are using PMU register offsets.
Since we have added support for accessing PMU base address via DT,
now we can remove PMU mapping from exynosX_iodesc.
Let's convert all these access using either of "get_exynos_pmuaddr
Hi,
On 25.04.2014 14:32, Pankaj Dubey wrote:
This patch adds device tree based initialization for PMU and modifies
PMU initialization implementation in following way:
1: Let's initialize PMU based on device tree compatibility string.
2: Obtain PMU regmap handle using "syscon_early_regmap_lookup
s as static".
For making more cleanup in "mach-exynos/common.h"
as suggested by Tomasz Figa.
- Addressed comments of Tomasz Figa for cleaning "mach-exynos/common.h".
- Updated patch: Remove file path from comment section
As suggested by Michel
Hi Vivek,
On 22.04.2014 10:03, Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Thereby, removing old phy-samsung-usb3 driver and related cod
Hi Vivek,
I have reviewed v5 without noticing this one, but I think most of the
comments still apply.
Best regards,
Tomasz
On 22.04.2014 13:24, Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
Hi Kevin,
On 26.04.2014 00:52, Kevin Hilman wrote:
Tarek Dakhran writes:
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
[...]
diff --git a/arch/arm/mach-e
Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.
Cc: Arnd Bergmann
Cc: Marc Zynigier
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
arch/arm/mach-exynos/hotplug.c | 19 ++
Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU
ed-by: Kyungmin Park
---
arch/arm/mach-exynos/Kconfig | 22 ++
arch/arm/mach-exynos/exynos.c| 2 ++
arch/arm/plat-samsung/include/plat/cpu.h | 10 ++
3 files changed, 34 insertions(+)
You can add my
Reviewed-by: Tomasz Figa
Best regards,
T
ndependently of Exynos3250 support.
Kukjin, what do you think?
Anyway,
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
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Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa
This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
dual core and includes following dt nodes:
- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex
On 24.04.2014 15:11, Ulf Hansson wrote:
On 24 April 2014 12:13, Geert Uytterhoeven wrote:
When adding a device from DT, check if its clocks are suitable for Runtime
PM, and register them with the PM core.
If Runtime PM is disabled, just enable the clock.
This allows the PM core to automatica
On 26.04.2014 02:51, Tomasz Figa wrote:
Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa
This patch add new exynos3250.dtsi to support Exynos3250 SoC based on
Cortex-A7
dual core and includes following dt nodes:
- GIC interrupt controller
- Pinctrl to control GPIOs
g-soc/29360
Best regards,
Tomasz
On 14.04.2014 09:17, Tarek Dakhran wrote:
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/Makefile|1 +
arc
On 16.05.2014 12:35, Rahul Sharma wrote:
> On 16 May 2014 15:12, Rahul Sharma wrote:
>> On 16 May 2014 03:14, Tomasz Figa wrote:
>>> On 15.05.2014 06:01, Rahul Sharma wrote:
> [snip]
>>>>> the PHY provider.
>>>>>
>>>>
>>
Hi Rahul,
On 16.05.2014 12:39, Rahul Sharma wrote:
> [snip]
>> + gate->lock = &clkout_lock;
>> +
>> + mux->reg = reg + EXYNOS_PMU_DEBUG_REG;
>> + mux->mask = EXYNOS_CLKOUT_MUX_MASK;
>> + mux->shift = EXYNOS_CLKOUT_MUX_SHIFT;
>> + mux->lock = &clkout_lock;
>> +
>> +
On 16.05.2014 16:30, Rahul Sharma wrote:
> On 16 May 2014 16:20, Tomasz Figa wrote:
>> On 16.05.2014 12:35, Rahul Sharma wrote:
>>> On 16 May 2014 15:12, Rahul Sharma wrote:
>>>> On 16 May 2014 03:14, Tomasz Figa wrote:
>>>>> On 15.05.2014 06:01, R
On 16.05.2014 16:35, Rahul Sharma wrote:
> On 16 May 2014 16:22, Tomasz Figa wrote:
>> Hi Rahul,
>>
>> On 16.05.2014 12:39, Rahul Sharma wrote:
>>> [snip]
>>>> + gate->lock = &clkout_lock;
>>>> +
>>>&
Hi,
On 08.05.2014 14:49, Tomasz Figa wrote:
> Up till now there was no single generic method to bind devices to their
> power domains using Device Tree. Each platform has been doing this using
> its own way, example of which are Exynos power domain bindings [1] and
> look-up code [2
Hi Alexander,
On 12.05.2014 18:47, Alexander Holler wrote:
> During the step from .dts to .dtb the information about dependcies contained
> in the .dts through phandle references is lost. This makes it impossible to
> use the binary blob to create a dependency graph without knowing the semantic
>
Hi,
On 14.05.2014 16:05, Grant Likely wrote:
> On Mon, 12 May 2014 18:47:53 +0200, Alexander Holler
> wrote:
>> Use the properties named 'dependencies' in binary device tree blobs to build
>> a dependency based initialization order for platform devices and drivers.
>>
>> This is done by building
Hi Tushar,
On 19.05.2014 09:16, Tushar Behera wrote:
> On 05/15/2014 11:02 PM, Tomasz Figa wrote:
>> This patch introduces a driver that handles configuration of CLKOUT pin
>> of Exynos SoCs that can be used to output certain clocks from inside of
>> the SoC to a
On 19.05.2014 05:30, Tushar Behera wrote:
> On 15 May 2014 19:37, Tomasz Figa wrote:
>> Hi Rahul, Tushar,
>>
>> On 15.05.2014 15:44, Rahul Sharma wrote:
>>> Hi Tushar,
>>>
>>> Basically you are adding a new clock-type for Clkout. IMO clkout
>>
Hi Tarek,
On 19.05.2014 05:37, Tarek Dakhran wrote:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on big.LITTLE architecture
>
> Patches add new platform description, support of clock controller and device
> tree for Exynos 5410.
Hi Rickard,
On 15.05.2014 23:57, Rickard Strandqvist wrote:
> There is otherwise a risk of a possible null pointer dereference.
>
> Was largely found by using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
> ---
> sound/soc/samsung/dma.c | 10 ++---
On 19.05.2014 09:10, Rahul Sharma wrote:
> On 16 May 2014 20:19, Tomasz Figa wrote:
>> On 16.05.2014 16:30, Rahul Sharma wrote:
>>> On 16 May 2014 16:20, Tomasz Figa wrote:
>>>> On 16.05.2014 12:35, Rahul Sharma wrote:
>>>>> On 16 May 2014 15:12, Rah
Hi,
On 19.05.2014 13:05, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Monday, May 19, 2014 11:46:10 AM Amit Kachhap wrote:
>> On 5/15/14, Zhang Rui wrote:
>>> On δΈ€, 2014-05-05 at 13:15 +0200, Bartlomiej Zolnierkiewicz wrote:
Hi,
This patch series contains various cleanups for
Hi Tarek,
On 19.05.2014 05:37, Tarek Dakhran wrote:
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
> Reviewed-by: Tomasz Figa
IIRC, the Reviewed-by tag stan
Hi Kukjin, Chanwoo,
On 15.05.2014 06:28, Chanwoo Choi wrote:
> Dear Kukjin,
>
> Could you please pick following patches?
> - [PATCHv5 1/5] ARM: EXYNOS: Add Exynos3250 SoC ID
> - [PATCHv5 2/5] ARM: EXYNOS: Support secondary CPU boot of Exynos3250
I'd say that [PATCHv5 5/5] ARM: dts: Add device tr
On 19.05.2014 13:36, Tomasz Figa wrote:
> Hi Kukjin, Chanwoo,
>
> On 15.05.2014 06:28, Chanwoo Choi wrote:
>> Dear Kukjin,
>>
>> Could you please pick following patches?
>> - [PATCHv5 1/5] ARM: EXYNOS: Add Exynos3250 SoC ID
>> - [PATCHv5 2/5] ARM
On 14.02.2014 06:16, Alexandre Courbot wrote:
On 02/13/2014 08:01 PM, Tomasz Figa wrote:
Hi Alexandre,
On 07.02.2014 05:35, Alexandre Courbot wrote:
Some firmwares do not put the CPU into idle mode themselves, but still
need to be informed that the CPU is about to enter idle mode before this
Hi Kukjin,
On 14.02.2014 00:28, Kukjin Kim wrote:
On 02/07/14 14:24, Naveen Krishna Chatradhi wrote:
This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250
Signed-off-by: Naveen Krishna Chatradhi
Reviewed-by: Tomasz Figa
TO:
CC: Kukjin Kim
CC:
---
changes since
Hi Vivek,
On 14.02.2014 14:53, Vivek Gautam wrote:
Changes from v2:
1) Added support for multiple PHYs (UTMI+ and PIPE3) and
related changes in the driver structuring.
I'm a bit skeptical about this separation. Can the PHY operate with just the
UTMI+ or PIPE3 part enabled alone without t
Mike,
On 08.04.2014 17:45, Tomasz Figa wrote:
Hi,
On 04.04.2014 16:53, Tomasz Stanislawski wrote:
This patch adds support for propagation of setup of clock's parent one
level
up.
This feature is helpful when a driver changes topology of its clocks
using
clk_set_parent(). The problem o
On 04.04.2014 16:53, Tomasz Stanislawski wrote:
Export sclk_hdmiphy clock to be usable from DT.
Signed-off-by: Tomasz Stanislawski
---
drivers/clk/samsung/clk-exynos4.c |2 +-
include/dt-bindings/clock/exynos4.h |1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a
Hi Vivek,
Please see my comments inline.
On 30.04.2014 07:19, Vivek Gautam wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for older usb-phy intact right now, in order
to prevent any functionality break in absence of relevant
device tree side change for
Hi Vivek,
I believe the same comments as for the patch for ohci-exynos apply for
this patch as well.
Best regards,
Tomasz
On 30.04.2014 07:19, Vivek Gautam wrote:
From: Kamil Debski
Add the phy provider, supplied by new Exynos-usb2phy using
Generic phy framework.
Keeping the support for ol
Hi Vivek,
This looks much better, but there still are some issues. Please see my
comments inline.
On 02.05.2014 14:47, Vivek Gautam wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for older usb-phy intact right now, in order
to prevent any functionalit
Hi Pankaj,
On 03.05.2014 03:52, Pankaj Dubey wrote:
Hi,
Gentle ping.
Tomasz, Kukjin will you please have a look on this series.
Sure. I have added this series to my queue and should be able to find
some time to review it after the weekend.
Best regards,
Tomasz
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Hi Chanwoo,
On 13.05.2014 13:49, Chanwoo Choi wrote:
> Hi Tomasz,
>
> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>> Hi Chanwoo,
>>
>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>> From: Tomasz Figa
>>>
>>> This patch add new the clock drvier
Hi Chanwoo
On 14.05.2014 08:57, Chanwoo Choi wrote:
> On 05/14/2014 01:28 AM, Tomasz Figa wrote:
>> On 13.05.2014 13:49, Chanwoo Choi wrote:
>>> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>>>> +/
Hi Chanwoo,
On 13.05.2014 15:05, Chanwoo Choi wrote:
> From: Tomasz Figa
>
> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
> using common clock framework. The CMU (Clock Management Unit) of Exynos3250
> control PLLs(Phase Locked Loops) and generate sy
rming secure firmware about CPU id.
> @@ -50,7 +57,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long
> boot_addr)
>
> boot_reg = sysram_ns_base_addr + 0x1c;
>
> - if (!soc_is_exynos4212())
> + if (!soc_is_exynos4212() && !soc_is_exy
i
> Signed-off-by: Tomasz Figa
> Acked-by: Kyungmin Park
> Cc: Mike Turquette
> Cc: Kukjin Kim
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: Randy Dunlap
> Cc: Tomasz Figa
> ---
> .
Hi,
On 13.05.2014 15:05, Chanwoo Choi wrote:
> From: Tomasz Figa
>
> This patch add new exynos3250.dtsi to support Exynos3250 SoC based on
> Cortex-A7
> dual core and includes following dt nodes:
>
> - GIC interrupt controller
> - Pinctrl to control GPIOs
>
On 14.05.2014 21:46, Kukjin Kim wrote:
> On 05/15/14 04:35, Tomasz Figa wrote:
>> Hi,
>>
>> On 13.05.2014 15:05, Chanwoo Choi wrote:
>>> The Exynos3250 clocks are statically listed and registered using the
>>> Samsung specific common clock helper functions.
Hi Rahul, Tomasz,
On 14.05.2014 21:17, Rahul Sharma wrote:
> From: Tomasz Stanislawski
>
> Add exynos-simple-phy driver to support a single register
> PHY interfaces present on Exynos4 SoC.
>
> Signed-off-by: Tomasz Stanislawski
> Signed-off-by: Rahul Sharma
>
> ---
> .../devicetree/binding
Hi Rahul, Tushar,
On 15.05.2014 15:44, Rahul Sharma wrote:
> Hi Tushar,
>
> Basically you are adding a new clock-type for Clkout. IMO clkout
> is not a special hardware. Existing clock types can be reused to
> support clkout. I see 3 major problem here:
>
> 1) Clkout -> (Mux + Gate). You clubbed
Hi Mike,
On 07.05.2014 18:24, Tomasz Figa wrote:
> Commit c686078 ("clk: divider: Add round to closest divider") introduced
> a helper function to check whether given divisor is the best one instead
> of direct check. However due to int type used instead of unsigned long
>
This patch adds definitions of clocks that are used to drive clock
output signals of particular CMU sub-blocks that are then fed to PMU and
handled by Exynos CLKOUT driver added in further patch.
Signed-off-by: Tomasz Figa
---
drivers/clk/samsung/clk-exynos4.c | 115
This patch extends nodes of PMU system controller on Exynos4210, 4x12,
5250 and 5420 SoCs with newly defined properties used by Exynos CLKOUT
driver.
Signed-off-by: Tomasz Figa
---
arch/arm/boot/dts/exynos4210.dtsi | 10 ++
arch/arm/boot/dts/exynos4x12.dtsi | 7 +++
arch/arm/boot
x.kernel.samsung-soc/30631)
for Exynos4210/4x12 PMU DT nodes.
Tomasz Figa (4):
clk: samsung: exynos4: Add missing DMC clock hierarchy
clk: samsung: exynos4: Add CLKOUT clock hierarchy
clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
ARM: dts: exynos: Update PMU nod
This patch adds missing definitions of clocks from DMC clock domain,
which are necessary to properly represent CLKOUT clock hierarchy added
in further patch.
Signed-off-by: Tomasz Figa
---
drivers/clk/samsung/clk-exynos4.c | 41 +++
1 file changed, 41
This patch introduces a driver that handles configuration of CLKOUT pin
of Exynos SoCs that can be used to output certain clocks from inside of
the SoC to a dedicated output pin.
Signed-off-by: Tomasz Figa
---
.../devicetree/bindings/arm/samsung/pmu.txt| 18
drivers/clk/samsung
Hi Chander,
On 14.05.2014 10:03, Chander Kashyap wrote:
> Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle
> driver.
> Hence do not allow exynos cpuidle driver registration for Exynos5420.
>
> Signed-off-by: Chander Kashyap
> Signed-off-by: Chander Kashyap
> Acked-by: Da
On 15.05.2014 06:01, Rahul Sharma wrote:
> Thanks Tomasz,
>
> On 15 May 2014 01:31, Tomasz Figa wrote:
>> Hi Rahul, Tomasz,
> [snip]
>>> + simplephys: simple-phys@1004 {
>>> + compatible = "samsung,exynos5250-simple-phy";
&
en Boyd,
- replaced notifiers with direct hooks in driver core to make power domain
support independent from specific bus type and allow error handling.
Tomasz Figa (3):
base: power: Add generic OF-based power domain look-up
drivercore: Bind/unbind power domain on probe/remove
ARM: exynos: Mo
-specific power domain
bindings is provided, but for now the new code is not compiled when
CONFIG_ARCH_EXYNOS is selected to avoid collision with legacy code. This
will change as soon as Exynos power domain code gets converted to use
the generic framework in further patch.
Signed-off-by: Tomasz Figa
a driver.
Signed-off-by: Tomasz Figa
Reviewed-by: Stephen Boyd
Reviewed-by: Philipp Zabel
[on i.MX6 GK802]
Tested-by: Philipp Zabel
Reviewed-by: Mark Brown
Reviewed-by: Ulf Hansson
---
drivers/base/dd.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/base
a driver.
Signed-off-by: Tomasz Figa
Reviewed-by: Stephen Boyd
Reviewed-by: Philipp Zabel
[on i.MX6 GK802]
Tested-by: Philipp Zabel
Reviewed-by: Mark Brown
Reviewed-by: Ulf Hansson
---
drivers/base/dd.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/base
en Boyd,
- replaced notifiers with direct hooks in driver core to make power domain
support independent from specific bus type and allow error handling.
Tomasz Figa (3):
base: power: Add generic OF-based power domain look-up
drivercore: Bind/unbind power domain on probe/remove
ARM: exynos: Mo
This patch moves Exynos power domain code to use the new generic power
domain look-up framework introduced by previous patch, allowing the new
code to be compiled with CONFIG_ARCH_EXYNOS selected as well.
Signed-off-by: Tomasz Figa
Reviewed-by: Ulf Hansson
---
.../bindings/arm/exynos
-specific power domain
bindings is provided, but for now the new code is not compiled when
CONFIG_ARCH_EXYNOS is selected to avoid collision with legacy code. This
will change as soon as Exynos power domain code gets converted to use
the generic framework in further patch.
Signed-off-by: Tomasz Figa
Sent with wrong Rafael's address, please ignore this thread. Just resent
with correct address. Sorry for the noise.
Best regards,
Tomasz
On 08.05.2014 14:45, Tomasz Figa wrote:
> Up till now there was no single generic method to bind devices to their
> power domains using Device
This patch moves Exynos power domain code to use the new generic power
domain look-up framework introduced by previous patch, allowing the new
code to be compiled with CONFIG_ARCH_EXYNOS selected as well.
Signed-off-by: Tomasz Figa
Reviewed-by: Ulf Hansson
---
.../bindings/arm/exynos
Hi Vivek,
On 05.05.2014 14:30, Vivek Gautam wrote:
> The exynos5250-snow has a SMSC USB3503 connected in
> hardware only mode like a PHY. Enable support for it,
> and add necessary 'reset-gpio' for it.
>
> This is in correspondance to similar patch by Mark Brown
> 7c1b0ec ARM: dts: Enable USB hub
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