Hi Rob,
On 06/21/2016 08:33 AM, Rob Herring wrote:
On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No
On 06/21/2016 10:48 AM, Rob Herring wrote:
On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer
wrote:
Hi Rob,
On 06/21/2016 08:33 AM, Rob Herring wrote:
On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com
wrote:
From: Thor Thayer
Add the device tree bindings needed to
On 07/27/2016 12:10 PM, Borislav Petkov wrote:
On Thu, Jul 14, 2016 at 11:06:43AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add Altera Arria10 NAND FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac
onfig altr_a10sr_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
Reviewed-by: Thor Thayer
On 08/08/2016 08:36 AM, Borislav Petkov wrote:
On Tue, Aug 02, 2016 at 10:56:20AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC
is a dual port RAM implementation which is different than any
of the other
this EDAC device */
drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
Thank you for this patch!
Acked-by: Thor Thayer
From: Thor Thayer
Add SMMU support for the Stratix10 SOCFPGA. This patch requires
clock enables for the master TBUs and therefore has a dependency
on patches currently being reviewed.
This patchset is dependent on the patch series
"iommu/arm-smmu: Add runtime pm/sleep support&qu
From: Thor Thayer
Add SMMU support to the Stratix10 Device Tree which
includes adding the SMMU node and adding IOMMU stream
ids to the SMMU peripherals. Update bindings.
Signed-off-by: Thor Thayer
---
This patch is dependent on the patch series
"iommu/arm-smmu: Add runtime pm/sleep su
From: Thor Thayer
Add the clocks required for the Stratix10 SMMU. Define the
clock names in the SMMU name array and add DT compatible
matching element.
Signed-off-by: Thor Thayer
---
This patch is dependent on the patch series
"iommu/arm-smmu: Add runtime pm/sleep support&qu
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4 bytes at a time.
[7.947754] spi_nor_read[1048]:from 0x037cad74, len 1 [bfe07fff
From: Thor Thayer
Remove QSPI Sector 4K size force which is causing QSPI boot
problems with the JFFS2 root filesystem.
Fixes the following error:
"Magic bitmask 0x1985 not found at ..."
Signed-off-by: Thor Thayer
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1
Hi. Any comments on this patch?
On 03/26/2018 09:12 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4
Hi. Any comments on this patch?
On 03/26/2018 02:50 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Remove QSPI Sector 4K size force which is causing QSPI boot
problems with the JFFS2 root filesystem.
Fixes the following error:
"Magic bitmask 0x1985 not found at ...&quo
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4 bytes at a time.
[7.947754] spi_nor_read[1048]:from 0x037cad74, len 1 [bfe07fff
Hi Marek,
On 03/19/2018 05:33 PM, Marek Vasut wrote:
On 03/19/2018 07:45 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because
edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL, base,
+ edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
+(void *)base,
&s10_sdram_regmap_cfg);
}
Thanks for the fix.
Reviewed-by: Thor Thayer
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic sporadically
when writing to QSPI. The problem was caused by writing more bytes
than needed because the QSPI operated on 4 bytes at a time.
[ 11.202044] Unable to handle kernel paging request at virtual address
bffd3000
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic sporadically
when writing to QSPI. The problem was caused by writing more bytes
than needed because the QSPI operated on 4 bytes at a time.
[ 11.202044] Unable to handle kernel paging request at virtual address
bffd3000
Hi Vignesh,
On 11/14/18 6:00 AM, Vignesh R wrote:
Hi,
On 13/11/18 11:02 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The current Cadence QSPI driver caused a kernel panic sporadically
when writing to QSPI. The problem was caused by writing more bytes
than needed because the QSPI
From: Thor Thayer
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.
Signed-off-by: Thor Thayer
---
v2 s/_/-/ in qspi-clk
rename flash node.
use
ions(+), 55 deletions(-)
--
2.7.4
Nice patchset!
FWIW, I've tested patches 1-3 on Stratix10 SOCFPGA for a SMMU driver I'm
working on.
Tested-by: Thor Thayer
Hi Arnd,
On 12/14/18 6:36 AM, Arnd Bergmann wrote:
On Tue, Nov 13, 2018 at 5:03 PM wrote:
From: Thor Thayer
The SOCFPGA System Manager register block aggregate different
peripheral functions into one place.
On 32 bit ARM parts, the syscon framework fits this problem well.
On 64 bit ARM
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required, this
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls as
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager compatible
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
1
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9a57d11330b..873d807bb82b
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
---
v2 New compatible string and usage for Stratix10
---
.../devicetree/bindings/arm/altera/socfpga-system.txt| 12
1 file changed, 12 insertions(+)
diff --git a
From: Thor Thayer
Now there are device tree clocks for the ARM64 SMMU,
add SMMU support to the Stratix10 Device Tree which
includes adding the SMMU node and adding IOMMU stream
ids to the SMMU peripherals.
Signed-off-by: Thor Thayer
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 29
From: Thor Thayer
Vince has moved to a different role. Replace him as Altera
TSE maintainer.
Signed-off-by: Thor Thayer
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 72429b928626..f02cf78f5394 100644
--- a/MAINTAINERS
+++ b
On 10/12/2018 11:57 AM, Greg KH wrote:
On Fri, Oct 12, 2018 at 11:50:52AM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Vince has moved to a different role. Replace him as Altera
TSE maintainer.
Signed-off-by: Thor Thayer
Would be nice if Vince can ack this...
+ Vince (at
From: Thor Thayer
Add SMMU support to the Stratix10 Device Tree which
includes adding the SMMU node and adding IOMMU stream
ids to the SMMU peripherals.
Signed-off-by: Thor Thayer
---
v4 Add clock-name since clk_bulk_get() needs name
for clock.
v3 Remove bindings changes since not adding
On 06/04/2015 10:26 AM, Dinh Nguyen wrote:
On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs
Hi Boris,
On 06/05/2015 10:15 AM, Borislav Petkov wrote:
On Fri, Jun 05, 2015 at 08:49:15AM -0500, dingu...@opensource.altera.com wrote:
From: Alan Tull
Suspend-to-RAM and EDAC support are mutually exclusive on
SOCFPGA. If the EDAC is enabled, it will prevent the
platform from going into sus
Hi Sudeep,
On 04/04/2018 05:47 AM, Sudeep Holla wrote:
On 30/03/18 00:00, Thor Thayer wrote:
Hi,
I'm working on an ARM64 architecture that needs to manipulate some
protected registers that are only accessible in EL3. Linux is running at
EL1 which doesn't have the proper permi
On 05/15/2018 10:11 AM, Dinh Nguyen wrote:
On 05/11/2018 11:10 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory
From: Thor Thayer
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.
Signed-off-by: Thor Thayer
---
v2 s/_/-/ in qspi-clk
rename flash node.
use
Hi Rob,
On 3/12/19 11:00 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts
Hi Rob,
On 3/12/19 11:04 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:22AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.
What's the difference? Sounds
From: Thor Thayer
Stratix10 Double Bit Error Address was always read from
SDRAM Address register instead of each device's Address
register.
To determine which device had the DBE, cycle through
the EDAC devices comparing the DBE value to the db_irq
value. Once found, report the DBE Address
Hi Rob,
On 3/13/19 2:20 PM, Rob Herring wrote:
On Tue, Mar 12, 2019 at 2:28 PM Thor Thayer wrote:
Hi Rob,
On 3/12/19 11:04 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:22AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to
From: Thor Thayer
Improve the Arria10 and Stratix10 error injection routine
by reading the data and changing just 1 bit before writing
back out. Previous routine would overwrite the first bytes
to 0 then change 1 bit but this method is less intrusive.
Signed-off-by: Thor Thayer
---
drivers
From: Thor Thayer
The FIFO memory and ECC initialization doesn't need to be
done as a separate operation early in the startup.
Improve the Arria10 and Stratix10 peripheral FIFO init
by initializing memory and enabling ECC as part of the
device driver initialization.
Signed-off-by: Thor T
On 4/2/19 3:55 AM, Borislav Petkov wrote:
On Fri, Mar 29, 2019 at 09:43:58AM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Reserve ECC Double Bit Error SMC call to alert U-Boot that
a DBE has occurred. Moving the call from local EDAC header
file to this common file.
Is there
Hi Boris,
On 4/4/19 9:36 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
This patch series makes the Stratix10 EDAC Bindings
specific to the Stratix10 ARM64 architecture.
Instead of using the Arria10 (ARM32) EDAC bindings for
Stratix10 (ARM64), create Stratix10 specific EDAC
Hi Boris,
On 4/9/19 3:13 PM, Borislav Petkov wrote:
On Tue, Apr 09, 2019 at 02:11:58PM -0500, Thor Thayer wrote:
If possible, I'd like this series to go through the EDAC tree since future
patches will follow this format.
You know how that works - I need ACKs.
I have ACKs on patches
On 2/25/19 11:36 AM, Dinh Nguyen wrote:
Hi Thor,
On 2/19/19 12:59 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Enable the different ECC blocks by default on Cyclone5
and Arria10.
Signed-off-by: Thor Thayer
---
arch/arm/configs/socfpga_defconfig | 36
From: Thor Thayer
Enable the different ECC blocks by default on Cyclone5
and Arria10.
Signed-off-by: Thor Thayer
---
v2 Rebase patch to the arm/defconfig on the arm-soc tree
---
arch/arm/configs/socfpga_defconfig | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm
From: Thor Thayer
The CONFIG_ALTERA_EDAC flag always enables the SDRAM
EDAC. On the newer architectures, there are cases where
the peripheral EDACs are enabled but SDRAM needs to be
disabled.
This change moves SDRAM functions so they can be contained
inside the conditional CONFIG.
Create new
From: Thor Thayer
Most users want EDAC support so make it the default.
SOCFPGA SDRAM EDAC reporting was enabled by the parent EDAC
config (CONFIG_ALTERA_EDAC) since initial customers always
wanted SDRAM EDAC enabled.
There are cases where the SDRAM needs to be disabled while
the other block
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.
Signed-off-by: Thor Thayer
---
v2 No change
---
.../devicetree/bindings/edac/socfpga-eccmgr.txt| 106 +
1 file changed, 106 insertions
From: Thor Thayer
Replace the Stratix10 Machine compatible check with
specific ECC block compatible tests.
Signed-off-by: Thor Thayer
---
v2 New patch
---
drivers/edac/altera_edac.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/edac
From: Thor Thayer
Use the new Stratix10 binding format for EDAC nodes.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 25 ---
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/altera
From: Thor Thayer
Stratix10 Double Bit errors are configured as SErrors
so skip the Double Bit IRQ initialization if Stratix10.
Since all the ECC peripherals are handled in this routine,
the machine compatible device tree test is used here
instead of multiple ECC block device tree compatible
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts.
Indicate the differences between the ARM64 and ARM32
EDAC architecture in the bindings.
Signed-off-by: Thor Thayer
---
v2 No change
From: Thor Thayer
Instead of using the Arria10 (ARM32) EDAC bindings for
Stratix10 (ARM64), create Stratix10 specific EDAC bindings
to capture architecture differences between ARM32 and ARM64.
This requires fixing the previous Stratix10 bindings.
Also add the peripheral bindings for the
On 7/29/20 12:45 PM, Dinh Nguyen wrote:
Thor Thayer is leaving Intel and will no longer be able to maintain the
EDAC for SoCFPGA, thus transfer maintainership to Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote:
> On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM
On 07/31/2014 03:26 AM, Lee Jones wrote:
On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add a simple MFD for the Altera SDRAM Controller.
Signed-off-by: Alan Tull
Signed-off-by: Thor Thayer
---
v1-8: The MFD implementation was not included in the original
On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar
wrote:
> Hi!
>
> On Thu, May 15, 2014 at 11:04:49AM -0500, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> Addition of the Altera SDRAM controller bindings and device
>> tree changes to the Altera SoC projec
On Mon, May 19, 2014 at 2:12 PM, Steffen Trumtrar
wrote:
> Hi Thor!
>
> On Mon, May 19, 2014 at 01:36:30PM -0500, Thor Thayer wrote:
>> On Fri, May 16, 2014 at 2:53 AM, Steffen Trumtrar
>> wrote:
>> > Hi!
>> >
>> > On Thu, May 15, 2014 at 11:04:
On Mon, May 12, 2014 at 7:12 PM, Borislav Petkov wrote:
> On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
>> + ptemp[0] = 0x5A5A5A5A;
>> + ptemp[1] = 0xA5A5A5A5;
>> + /* Clear the error injection bits */
>> + regmap_write(drvdata->mc_vbase, CTLCFG, read_reg);
>>
On Thu, May 8, 2014 at 7:05 AM, Borislav Petkov wrote:
> On Mon, May 05, 2014 at 05:52:17PM -0500, ttha...@altera.com wrote:
>> From: Thor Thayer
>
> Missing commit message.
Whoops. I don't know what happened there. I'll fix it.
>
>> ---
>> v2: Use the
On Thu, May 8, 2014 at 5:44 PM, Dinh Nguyen wrote:
>
> On 5/5/14 5:52 PM, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> ---
>> v2: Use the SDRAM controller registers to calculate memory size
>> instead of the Device Tree. Update To & Cc
On Fri, May 9, 2014 at 8:52 AM, Borislav Petkov wrote:
> On Thu, May 08, 2014 at 03:37:19PM -0500, Thor Thayer wrote:
>> Yes. Their reasoning is that they want to retain the rights and
>> warranty language with the file (just in case the COPYING file
>> changes).
>
> Ok
On Fri, May 9, 2014 at 3:52 PM, Borislav Petkov wrote:
> On Fri, May 09, 2014 at 03:31:53PM -0500, Thor Thayer wrote:
>> Yes, good point. Our hardware can't recover from Double Bit Errors so
>> I'll go back to the panic() in that path. I like the flexibility of
>
On Tue, 2014-04-08 at 12:08 +0200, Borislav Petkov wrote:
> On Mon, Apr 07, 2014 at 04:54:09PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM
On Tue, 2014-04-08 at 14:45 +0200, Steffen Trumtrar wrote:
> On Tue, Apr 08, 2014 at 11:45:25AM +0100, Mark Rutland wrote:
> > On Mon, Apr 07, 2014 at 10:54:09PM +0100, ttha...@altera.com wrote:
> > > From: Thor Thayer
> > >
> > > Added EDAC support for report
On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote:
> Hi!
>
> On Mon, Apr 07, 2014 at 04:54:07PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Addition of the Altera SDRAM controller bindings and device
> > tree changes to t
On Tue, 2014-04-08 at 18:22 +0200, Borislav Petkov wrote:
> On Tue, Apr 08, 2014 at 05:10:54PM +0100, Mark Rutland wrote:
> > Typically the bindings would go with the driver via the appropriate
> > subsystem maintainer. That way we don't get bindings without drivers
> > or vice-versa if there's a p
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
> On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
> wrote:
> > On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
> > wrote:
> >> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> >>> On
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
> On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
> wrote:
> > On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
> > wrote:
> >> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> >>> On
On Tue, 2014-04-08 at 13:52 -0500, Rob Herring wrote:
> On Tue, Apr 8, 2014 at 11:02 AM, delicious quinoa
> wrote:
> > On Tue, Apr 8, 2014 at 9:33 AM, Steffen Trumtrar
> > wrote:
> >> On Tue, Apr 08, 2014 at 09:29:50AM -0500, Thor Thayer wrote:
> >>> On
On Sat, Jun 21, 2014 at 4:04 AM, Steffen Trumtrar
wrote:
> Hi!
>
> On Fri, Jun 20, 2014 at 06:22:01PM -0500, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> Addition of the Altera SDRAM Controller bindings and device tree changes.
>>
>> v2: C
On Sat, Jun 21, 2014 at 4:06 AM, Steffen Trumtrar
wrote:
> On Fri, Jun 20, 2014 at 06:22:02PM -0500, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> Addition of the Altera SDRAM EDAC bindings and device tree changes
>>
>> v2: Changes to SoC EDAC source c
Hi Mark
On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland wrote:
> On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
>> project.
>>
>> S
On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland wrote:
> On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
>> project.
>>
>> Signed-off
On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote:
> Hi!
>
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM Controller registers are used by the FPGA bridge so
> &g
On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar
wrote:
> Hi!
>
> On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote:
>> On Mon, May 19, 2014 at 2:37 PM, Thor Thayer wrote:
>>
>> >>> >> diff --git
>> >>> >> a/Documentatio
On Mon, May 26, 2014 at 4:57 AM, Borislav Petkov wrote:
> On Thu, May 15, 2014 at 11:04:51AM -0500, ttha...@altera.com wrote:
>> From: Thor Thayer
>>
>> v2: Use the SDRAM controller registers to calculate memory size
>> instead of the Device Tree. Update T
On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar
wrote:
> On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote:
>> On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar
>> wrote:
>> > Hi!
>> >
>> > On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull
Hi Sören
On Mon, May 5, 2014 at 6:16 PM, Sören Brinkmann
wrote:
>
> Hi Thor,
>
> On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Addition of the Altera SDRAM controller bindings and device
> > tree changes to
On Tue, May 6, 2014 at 10:42 AM, Dinh Nguyen wrote:
> On Mon, 2014-05-05 at 17:52 -0500, Thor Thayer wrote:
>> From: Thor Thayer
>>
>> ---
>> v2: Use the SDRAM controller registers to calculate memory size
>> instead of the Device Tree. Update To & Cc li
Hi Dinh,
On Wed, Jun 25, 2014 at 4:12 PM, Dinh Nguyen wrote:
> Hi Thor,
>
>
> On 06/25/2014 04:15 PM, ttha...@altera.com wrote:
>>
>> From: Thor Thayer
>>
>> This patch adds support for the CycloneV and ArriaV SDRAM controllers.
>> Correction and repo
On 08/14/2014 01:49 PM, Pavel Machek wrote:
On Mon 2014-08-11 10:18:13, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer
Acked-by: Pavel Machek
Hi All,
Any further
On 08/14/2014 01:49 PM, Pavel Machek wrote:
On Mon 2014-08-11 10:18:12, ttha...@opensource.altera.com wrote:
From: Thor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
Signed-off-by: Thor Thayer
Acked-by: Pavel
On 08/17/2014 07:50 PM, Rob Herring wrote:
On 07/30/2014 01:22 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add the Altera SDRAM controller bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor Thayer
---
v2: Changes to SoC SDRAM EDAC code.
v3
On 08/15/2014 11:07 AM, atull wrote:
On Fri, 15 Aug 2014, Steffen Trumtrar wrote:
Hi!
Hello
Thanks for the feedback...
ttha...@opensource.altera.com writes:
From: Thor Thayer
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor
On 08/01/2014 03:13 AM, Lee Jones wrote:
On Thu, 31 Jul 2014, Thor Thayer wrote:
On 07/31/2014 03:26 AM, Lee Jones wrote:
On Wed, 30 Jul 2014, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Add a simple MFD for the Altera SDRAM Controller.
Signed-off-by: Alan Tull
Signed-off-by
On 08/02/2014 12:08 PM, Steffen Trumtrar wrote:
Hi!
On Fri, Aug 01, 2014 at 05:27:57PM -0500, Thor Thayer wrote:
On 08/01/2014 03:13 AM, Lee Jones wrote:
On Thu, 31 Jul 2014, Thor Thayer wrote:
On 07/31/2014 03:26 AM, Lee Jones wrote:
On Wed, 30 Jul 2014, ttha...@opensource.altera.com
Hi Boris!
On 11/04/2014 09:12 AM, Borislav Petkov wrote:
On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory
Hi Borislav,
On 10/17/2014 03:33 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.
Thor Thayer (4
On 10/27/2014 03:43 PM, Borislav Petkov wrote:
On Mon, Oct 27, 2014 at 01:50:24PM -0500, Thor Thayer wrote:
Do you have any comments about this driver?
Just a question: why do you have three .c files for something which
does only error injection and nothing else AFAICT? Why isn't this pa
On 10/27/2014 04:59 PM, Borislav Petkov wrote:
On Mon, Oct 27, 2014 at 04:35:00PM -0500, Thor Thayer wrote:
Should I move the EDAC Device probe and error handling from
altera_edac_mgr.c to altera_edac.c? Can I mix the MC and Device models
in the same file?
Right, for basic practical reasons
Hi Dinh,
On 11/07/2014 02:13 PM, Dinh Nguyen wrote:
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail
Hi Dinh,
On 11/07/2014 02:32 PM, Dinh Nguyen wrote:
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will
On 04/15/2016 04:40 AM, Mauro Carvalho Chehab wrote:
Em Thu, 14 Apr 2016 09:35:01 -0500
Rob Herring escreveu:
On Tue, Apr 12, 2016 at 05:12:55PM -0500, ttha...@opensource.altera.com wrote:
This patch set adds the memory initialization functions for Altera's
Arria10 peripherals, the first of
Hi Vladimir,
On 01/22/2016 12:02 AM, Vladimir Zapolskiy wrote:
Hi Thor,
On 21.01.2016 19:34, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory
On 01/22/2016 12:08 PM, Borislav Petkov wrote:
On Fri, Jan 22, 2016 at 06:56:57PM +0200, Vladimir Zapolskiy wrote:
it sounds like the author of the original change is Dinh, but if you agreed
about authorship transfer, then "From: Thor Thayer" statement should be
correct, but in any
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