On Tue, 2012-08-14 at 17:22 +0300, Peter Ujfalusi wrote:
> Signed-off-by: Peter Ujfalusi
I think this one could use a short commit message, also about why
kfree():s are dropped (handled internally by devm_* etc.)
-Tero
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To unsubscribe from this list: send the line "unsubscribe linux-kernel" i
Hi Peter,
The MFD patches in this set look good to me except for the minor comment
on patch 2 I just sent. That is with my limited knowledge of DT
though...
-Tero
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To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
Mor
Acked-by: Tero Kristo
On Wed, 2012-10-31 at 15:54 +0100, Peter Ujfalusi wrote:
> The correct chip id is 1 since the PWM module is on address 0x49. With the
> current TWL6030_MODULE_ID1 the kernel will crash early since:
> #define TWL6030_MODULE_ID1 0x0E
> and
> static st
minor beautification of clk-provider.h where some whitespace is
added and of_fixed_factor_clock_setup is relocated to maintain a
consistent style.
Tero Kristo contributed helpful bug fixes to this patch.
Signed-off-by: Mike Turquette
Tested-by: Heiko Stuebner
Reviewed-by: Heiko Stuebner
Hi,
Chirping in my thoughts below.
On 09/05/2013 11:30 PM, Stephen Warren wrote:
On 09/05/2013 12:29 PM, Mike Turquette wrote:
On Wed, Sep 4, 2013 at 11:36 AM, Stephen Warren wrote:
On 09/03/2013 05:22 PM, Mike Turquette wrote:
Quoting Stephen Warren (2013-08-30 14:37:46)
On 08/30/2013 02:
On 08/29/2013 09:23 PM, Santosh Shilimkar wrote:
Mike,
On Thursday 22 August 2013 01:53 AM, Mike Turquette wrote:
This series introduces binding definitions for common register-mapped
clock multiplexer, divider and gate IP blocks along with the
corresponding setup functions for matching DT data
me, thus for whole set:
Acked-by: Tero Kristo
On Tue, 2012-11-13 at 09:28 +0100, Peter Ujfalusi wrote:
> Hello,
>
> This series converts the twl-core to use regmap for IO towards the chip.
> With the conversion to regmap IO we no longer need to allocate bigger buffer
> for
>
On 08/02/2013 10:30 AM, Roger Quadros wrote:
Hi Nishant,
On 08/01/2013 06:06 PM, Nishanth Menon wrote:
On 08/01/2013 09:58 AM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
Signed-off-by: Roger
Looks good to me. Ack.
On Fri, 2013-02-15 at 22:23 +0800, Axel Lin wrote:
> Since commit ba305e31 "regulator: twl: fix twl4030 support for smps
> regulators",
> VDD1_VSEL_table and VDD2_VSEL_table are not used any more. Remove them.
>
> Signed-off-by: Axel Lin
> ---
> drivers/regulator/twl-reg
On 08/09/16 20:31, Kevin Hilman wrote:
Nishanth Menon writes:
On 09/07/2016 01:55 PM, Kevin Hilman wrote:
Nishanth Menon writes:
[...] full mail thread in https://lkml.org/lkml/2016/9/6/747
Overall architecture is very similar to SCPI[4] as follows:
Dumb Q: I'm curious about the limita
dex ..6c43e097e6d6
--- /dev/null
+++ b/drivers/clk/keystone/sci-clk.c
@@ -0,0 +1,539 @@
+/*
+ * SCI Clock driver for keystone based devices
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo
+ *
+ * This program is free software; you can
Hi Santosh,
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
https://github.com/t-kristo/linux-pm.git 4.8-rc1-ti-sci-fw
for you to fetch changes up to 7a2c510cdfa6a4b2f4200c122a37
On 01/09/16 01:31, Stephen Boyd wrote:
On 08/31, Tero Kristo wrote:
On 24/08/16 11:34, Stephen Boyd wrote:
On 08/19, Nishanth Menon wrote:
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
new file mode 100644
index ..6c43e097e6d6
--- /dev/null
+++ b
("clk: keystone: Add sci-clk driver support")
Signed-off-by: Arnd Bergmann
Looks ok to me. Tero?
Yeah, looks okay to me also, been traveling so sorry about the latency.
Acked-by: Tero Kristo
PM / QoS: Fix device resume latency PM QoS")
Signed-off-by: Tero Kristo
Cc: Rafael J. Wysocki
Applied.
And pushed to Linus.
I'm afraid it is not sufficient.
Commit 0cc2b4e5a020fc7f ("PM / QoS: Fix device resume latency PM QoS")
introduced two issues on Renesas platform
On 14/11/17 19:37, Tony Lindgren wrote:
* Joonsoo Kim [171114 06:34]:
On Fri, Nov 10, 2017 at 07:36:20AM -0800, Tony Lindgren wrote:
* Joonsoo Kim [171110 06:34]:
On Thu, Nov 09, 2017 at 07:26:10PM -0800, Tony Lindgren wrote:
+#define OMAP34XX_SRAM_PHYS 0x4020
+#define OMAP34XX_SRAM
On 14/11/17 21:44, Tony Lindgren wrote:
* Tero Kristo [171114 19:34]:
I guess you could just use rx51_secure_dispatcher and ditch the
save_secure_ram_context call completely (and most of the other related
code)? That one would handle the cache also in a clean manner.
Something like
econd level issues like
probe failures and increased power consumption among other things.
Fix this by adding a proper return value for devices that don't
implement PM QoS implicitly.
Fixes: 0cc2b4e5a020 ("PM / QoS: Fix device resume latency PM QoS")
Signed-off-by: Tero Kristo
C
On 31/10/17 01:27, Rafael J. Wysocki wrote:
On Monday, October 30, 2017 11:19:08 AM CET Rafael J. Wysocki wrote:
On Mon, Oct 30, 2017 at 8:10 AM, Tero Kristo wrote:
The recent change to the PM QoS framework to introduce a proper
no constraint value overlooked to handle the devices which don&#
On 31/10/17 10:40, Rafael J. Wysocki wrote:
On Tue, Oct 31, 2017 at 8:13 AM, Tero Kristo wrote:
On 31/10/17 01:27, Rafael J. Wysocki wrote:
On Monday, October 30, 2017 11:19:08 AM CET Rafael J. Wysocki wrote:
On Mon, Oct 30, 2017 at 8:10 AM, Tero Kristo wrote:
The recent change to the
becomes 0x0a instead of the expected 0x10.
Fix by moving the +1 addition within the bin2bcd call also.
Fixes: 1d1945d261a2 ("drivers/rtc/rtc-ds1307.c: add alarm support for mcp7941x
chips")
Signed-off-by: Tero Kristo
---
drivers/rtc/rtc-ds1307.c |4 ++--
1 file changed, 2 insert
On 09/30/2015 01:37 AM, Suman Anna wrote:
The default clock enabling functions for TI clocks -
omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
NULL check for the enable_reg field of the clk_hw_omap structure.
This enable_reg field however is merely a combination of the index
of the
I fixed up most of these last year, but this
one managed to sneak in since then.
clk-next should be fine.
The patch looks fine to me also, just had to test this out with my
latest development branch as it conflicts with that one a bit.
Acked-by: Tero Kristo
--
Texas Instruments Finland Oy
On 10/07/18 08:56, Tony Lindgren wrote:
* Keerthy [180621 01:18]:
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.
Patches 1 to
On 16/01/18 03:11, Tony Lindgren wrote:
We can support the RSTCTRL reset registers on many TI SoCs with
reset-simple.
Cc: Dave Gerlach
Cc: Mark Rutland
Cc: Nishant Menon
Cc: Philipp Zabel
Cc: Rob Herring
Cc: Suman Anna
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
---
That's all
et if usb_otg_ss instances 3 and 4 are affected by this
issue or not so don't add this flag for those instances.
Cc: Tero Kristo
Signed-off-by: Roger Quadros
Signed-off-by: Tony Lindgren
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
This fails to build for me on arm32 wi
On 23/11/2018 10:20, Arnd Bergmann wrote:
On Thu, Nov 22, 2018 at 12:41 PM Roger Quadros wrote:
+
+ if (IS_ERR_OR_NULL(rproc))
+ return ERR_PTR(-EINVAL);
Any usage of IS_ERR_OR_NULL() tends to be an indication of a badly
designed API. Please change this to allow only on
On 20/11/2018 12:44, Vignesh R wrote:
On 20/11/18 4:07 PM, Tero Kristo wrote:
On 20/11/2018 12:09, Vignesh R wrote:
On 19/11/18 12:49 PM, Tero Kristo wrote:
On 17/11/2018 18:05, Nishanth Menon wrote:
On 11:31-20181113, Vignesh R wrote:
The dt-bindings header for TI K3 AM6 SoCs define a set
On 20/11/2018 12:09, Vignesh R wrote:
On 19/11/18 12:49 PM, Tero Kristo wrote:
On 17/11/2018 18:05, Nishanth Menon wrote:
On 11:31-20181113, Vignesh R wrote:
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
[...]
Thanks for reducing the combinations down to the
On 30/11/2018 09:20, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-29 22:15:34)
Hi Stephen,
On Thu, 29 Nov 2018 16:25:05 -0800
Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:14)
Code might use autoidle api with clocks not being omap2 clocks,
so check if clock type is n
On 30/11/2018 02:26, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:12)
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is enough
to show up that problem, if there are no other things enabled.
Further researc
On 30/11/2018 09:57, Stephen Boyd wrote:
Quoting Tero Kristo (2018-11-29 23:35:35)
On 30/11/2018 09:20, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-29 22:15:34)
Hi Stephen,
On Thu, 29 Nov 2018 16:25:05 -0800
Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:14)
Code
On 30/11/2018 09:57, Stephen Boyd wrote:
Quoting Tero Kristo (2018-11-29 23:37:35)
On 30/11/2018 02:26, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:12)
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is
On 17/11/2018 18:05, Nishanth Menon wrote:
On 11:31-20181113, Vignesh R wrote:
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
defining pinmux configs in human readable form, instead of raw-coded
hex values.
Signed-off-by: Vignesh R
---
MAINTAINERS |
On 07/11/2018 23:00, Nishanth Menon wrote:
On 10:10-20181005, Vutla, Lokesh wrote:
On Thursday 27 September 2018 10:31 AM, Vignesh R wrote:
cbass_wakeup interconnect which is the parent of wakeup_uart node
defines address-cells=1 and size-cells=1, therefore fix up reg property
of wakeup_uart
On 19/06/18 07:28, Keerthy wrote:
The default restore context function enables or disables
the clock based on the enable_count. This is done in cases
where the clock context is lost and based on the enable_count
the clock either needs to be enabled/disabled. This particularly
helps restore the st
On 30/05/18 17:50, Tony Lindgren wrote:
* Faiz Abbas [180530 14:12]:
From: Lokesh Vutla
Add MCAN hwmod data and register it for dra762 silicons.
Signed-off-by: Lokesh Vutla
Signed-off-by: Faiz Abbas
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 32 +++
1 file chang
On 30/05/18 18:28, Tony Lindgren wrote:
* Tero Kristo [180530 15:18]:
For the OCP if part, I think that is still needed until we switch over to
full sysc driver. clkctrl_offs you probably also need because that is used
for mapping the omap_hwmod against a specific clkctrl clock. Those can be
On 30/05/18 18:54, Tony Lindgren wrote:
* Tero Kristo [180530 15:44]:
On 30/05/18 18:28, Tony Lindgren wrote:
* Tero Kristo [180530 15:18]:
For the OCP if part, I think that is still needed until we switch over to
full sysc driver. clkctrl_offs you probably also need because that is used
On 31/05/18 13:14, Faiz Abbas wrote:
Hi,
On Thursday 31 May 2018 09:33 AM, Rob Herring wrote:
On Wed, May 30, 2018 at 07:41:30PM +0530, Faiz Abbas wrote:
Add clkctrl data for the m_can clocks and register it within the
...
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings
On 09/12/2018 12:22, Vignesh R wrote:
There are 3 instances of McSPI in MCU domain and 4 instances in Main domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52
arch/arm64/boot/d
On 13/12/2018 17:03, Vignesh R wrote:
On 13-Dec-18 8:29 PM, Tero Kristo wrote:
On 09/12/2018 12:22, Vignesh R wrote:
There are 3 instances of McSPI in MCU domain and 4 instances in Main
domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: Vignesh R
---
arch
On 28/12/2018 22:02, Tony Lindgren wrote:
* Andreas Kemnade [181227 20:13]:
Hi,
On Tue, 4 Dec 2018 08:45:57 -0800
Tony Lindgren wrote:
* Andreas Kemnade [181204 06:17]:
On Mon, 3 Dec 2018 07:39:10 -0800
Tony Lindgren wrote:
The consumer device stays active just fine with PM runtime
call
On 04/01/2019 01:39, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-12-31 00:30:21)
On Mon, 31 Dec 2018 09:23:01 +0200
Tero Kristo wrote:
On 28/12/2018 22:02, Tony Lindgren wrote:
* Andreas Kemnade [181227 20:13]:
Hi,
On Tue, 4 Dec 2018 08:45:57 -0800
Tony Lindgren wrote
On 04/10/2018 23:38, Andreas Kemnade wrote:
Deny autoidle for hwmods with the OCPIF_SWSUP_IDLE flag,
that makes hwmods working properly which cannot handle
autoidle properly in lower power states.
Affected is e. g. the omap_hdq.
Since an ick might have mulitple users, autoidle is disabled
when an
On 04/10/2018 23:38, Andreas Kemnade wrote:
We have the scenario that first autoidle is disabled for all clocks,
then it is disabled for selected ones and then enabled for all. So
we should have some counting here, also according to the
comment in _setup_iclk_autoidle()
Signed-off-by: Andreas K
On 08/11/2018 13:08, Andreas Kemnade wrote:
Hi,
On Thu, 8 Nov 2018 12:26:08 +0200
Tero Kristo wrote:
On 04/10/2018 23:38, Andreas Kemnade wrote:
Deny autoidle for hwmods with the OCPIF_SWSUP_IDLE flag,
that makes hwmods working properly which cannot handle
autoidle properly in lower power
On 04/10/18 08:51, Andreas Kemnade wrote:
We have the scenario that first autoidle is disabled for all clocks,
then it is disabled for selected ones and then enabled for all. So
we should have some counting here, also according to the
comment in _setup_iclk_autoidle()
Signed-off-by: Andreas Kem
On 04/10/18 17:25, Tony Lindgren wrote:
* Andreas Kemnade [181004 05:56]:
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is enough
to show up that problem, if there are no other things enabled.
Further research reveals th
On 04/10/18 18:07, Tony Lindgren wrote:
* Tero Kristo [181004 14:47]:
On 04/10/18 17:25, Tony Lindgren wrote:
It seems we should just provide a generic interface for
clk_allow_autoidle() and clk_deny_autoidle()? Otherwise we'll
be forever stuck with pdata callbacks it seems.
The TI
The synth traces incorrectly print pointer to the synthetic event values
instead of the actual value when using u64 type. Fix by addressing the
contents of the union properly.
Fixes: ddeea494a16f ("tracing/synthetic: Use union instead of casts")
Cc: sta...@vger.kernel.org
Signed-of
Hi Masami,
On 15/09/2023 09:01, Masami Hiramatsu (Google) wrote:
Hi Tero,
On Mon, 11 Sep 2023 17:17:04 +0300
Tero Kristo wrote:
The synth traces incorrectly print pointer to the synthetic event values
instead of the actual value when using u64 type. Fix by addressing the
contents of the
On 03/20/2015 11:54 PM, Eduardo Valentin wrote:
On Fri, Mar 20, 2015 at 02:47:39PM -0500, Nishanth Menon wrote:
From: Tero Kristo
OMAP4 has a finer counter granularity, which allows for a delay of 1000ms
in the thermal zone polling intervals. OMAP5/DRA7 have different counter
mechanism, which
On 04/15/2015 12:17 AM, Michael Welling wrote:
Greetings,
I have developed an AM3354 based SoM and it uses an external SI5351 clock
generator to drive the clock inputs for an external duart and I2S audio
master clock. With the registration according to the documentation the
reference clock is no
On 04/15/2015 05:09 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 09:34:48AM +0300, Tero Kristo wrote:
On 04/15/2015 12:17 AM, Michael Welling wrote:
Greetings,
I have developed an AM3354 based SoM and it uses an external SI5351 clock
generator to drive the clock inputs for an external
On 04/15/2015 11:51 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 01:45:53PM -0700, Mike Turquette wrote:
On Wed, Apr 15, 2015 at 12:47 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 09:43:30PM +0300, Tero Kristo wrote:
On 04/15/2015 05:09 PM, Michael Welling wrote:
On Wed, Apr 15
, 2015 at 07:32:32AM +0300, Tero Kristo wrote:
On 04/15/2015 11:51 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 01:45:53PM -0700, Mike Turquette wrote:
On Wed, Apr 15, 2015 at 12:47 PM, Michael Welling wrote:
[...]
There is still an issue with the si5351.
I had to comment out the clk_put
only.
-Tero
Cc: Paul Walmsley mailto:p...@pwsan.com>>
Cc: Tero Kristo mailto:t-kri...@ti.com>>
Cc: Tony Lindgren mailto:t...@atomide.com>>
Signed-off-by: Brian Hutchinson mailto:b.hutch...@gmail.com><mailto:t...@atomide.com>>
--- arch/arm/mach-omap2/omap_hwmod_81
please. Or use a mailer that doesn't convert tabs to
spaces. This patch seems to have something else that is strange also.
Cc: Paul Walmsley mailto:p...@pwsan.com>>
Cc: Tero Kristo mailto:t-kri...@ti.com>>
Cc: Tony Lindgren mailto:t...@atomide.com>>
Signed-off-by: Brian Hu
On 06/01/2015 02:53 PM, Vignesh R wrote:
Add hwmod entries for the PWMSS on DRA7.
Can you provide some documentation references for this data?
I was looking at the TRM and at least the main_clk selection is somewhat
unclear to me.
-Tero
Signed-off-by: Vignesh R
---
arch/arm/mach-omap2
On 06/01/2015 02:53 PM, Vignesh R wrote:
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
Care to add TRM reference here?
-Tero
Signed-off-by: Vignesh R
---
arch/arm/boot/dts/dra7.dtsi | 5 +
arch/arm/boot/dts/dra7xx-cl
On 28/03/2019 14:31, Rob Herring wrote:
On Tue, Mar 12, 2019 at 02:35:17PM +0530, Vignesh Raghavendra wrote:
Add dt bindings for TI syscon gate clock.
Signed-off-by: Vignesh Raghavendra
---
.../bindings/clock/ti,syscon-gate-clock.txt | 35 +++
1 file changed, 35 insertions
-bindings: arm: keystone: Convert ti,sci to json schema
For the whole series:
Reviewed-by: Tero Kristo
.../bindings/arm/keystone/ti,sci.txt | 86
.../bindings/arm/keystone/ti,sci.yaml | 129 ++
.../devicetree/bindings/clock/ti,sci-clk.txt
Hi Dario,
Spent some time looking at this, had to read through the TRM chapter of
it also in quite detailed level to figure out how this is supposed to
work out.
Other than couple of minor nits below, the code seems ok to me. What is
the testing that has been done with this?
On 01/04/2021
On 07/04/2021 15:52, Rob Herring wrote:
On Wed, Apr 7, 2021 at 2:07 AM Dario Binacchi wrote:
Il 07/04/2021 03:16 Rob Herring ha scritto:
On Tue, Apr 6, 2021 at 5:02 PM Dario Binacchi wrote:
Il 06/04/2021 16:06 Rob Herring ha scritto:
On Fri, Apr 2, 2021 at 2:21 PM Dario Binacchi
ently M to satisfy the
constraint imposed by SSC.
Signed-off-by: Dario Binacchi
Reviewed-by: Tero Kristo
---
Changes in v5:
- Remove ssc_ack_mask field from dpll_data structure. It was not used.
- Change ssc_downspread type from u8 to bool in dpll_data structure.
Changes in v4:
- Update comm
On 08/04/2021 23:24, Dario Binacchi wrote:
Il 07/04/2021 15:21 Tero Kristo ha scritto:
On 07/04/2021 15:52, Rob Herring wrote:
On Wed, Apr 7, 2021 at 2:07 AM Dario Binacchi wrote:
Il 07/04/2021 03:16 Rob Herring ha scritto:
On Tue, Apr 6, 2021 at 5:02 PM Dario Binacchi wrote
On 11/04/2021 22:30, Dario Binacchi wrote:
Il 09/04/2021 12:32 Tero Kristo ha scritto:
On 08/04/2021 23:24, Dario Binacchi wrote:
Il 07/04/2021 15:21 Tero Kristo ha scritto:
On 07/04/2021 15:52, Rob Herring wrote:
On Wed, Apr 7, 2021 at 2:07 AM Dario Binacchi wrote:
Il 07
On 02/04/2021 22:20, Dario Binacchi wrote:
Until now, only the register offset was retrieved from the device tree
to be added, during access, to a common base address for the clocks.
If possible, we try to retrieve the physical address of the register
directly from the device tree.
The physical
move myself as secondary contact point where someone else has
taken over the maintainership.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Nishanth Menon
Cc: Santosh Shilimkar
Cc: Borislav Petkov
Cc: Tony Luck
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
MAINTAINERS | 12 ++
'hw'
description in '_register_dpll'
Cc: Tero Kristo
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: linux-o...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Signed-off-by: Lee Jones
Reviewed-by: Tero Kristo
---
drivers/clk/ti/dpll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
ction parameter 'clk'
description in 'omap2_init_clk_clkdm'
Cc: Tero Kristo
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: linux-o...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Signed-off-by: Lee Jones
Reviewed-by: Tero Kristo
---
drivers/clk/ti/clockdomain.c | 2 +-
1 file chan
ction parameter 'clk'
description in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
Cc: Tero Kristo
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: linux-o...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Signed-off-by: Lee Jones
Reviewed-by: Tero Kristo
---
drivers/clk/ti/gat
On 20/01/2021 21:51, Nishanth Menon wrote:
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla
Signed-off-by: Nishanth Menon
Reviewed-by: Tero Kristo
---
AM65: https
2 +-
drivers/clk/tegra/clk-tegra30.c| 5 +-
drivers/clk/tegra/cvb.c| 1 +
drivers/clk/ti/clkt_dpll.c | 3 +-
drivers/clk/ti/dpll3xxx.c | 20 ++---
drivers/clk/ti/dpll44xx.c | 6 +-
For the TI portions:
Reviewed-by: Tero
On 03/14/2014 01:36 AM, Joel Fernandes wrote:
On 03/13/2014 04:52 PM, Rob Herring wrote:
On Thu, Mar 13, 2014 at 3:35 PM, Joel Fernandes wrote:
Introduce a generic omap timer initialization function that can
be used by all SoCs for which support is available in the clocksource
driver introduce
On 03/13/2014 10:35 PM, Joel Fernandes wrote:
Signed-off-by: Joel Fernandes
---
arch/arm/boot/dts/am33xx.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 4e6c959..51b7008 100644
--- a/arch/arm/boot/dts/am33xx.dts
On 01/29/2014 08:19 PM, Nishanth Menon wrote:
cpu0 clock node has no functionality, since cpufreq-cpu0 is already
capable of picking up the clock from dts.
Signed-off-by: Nishanth Menon
Acked-by: Tero Kristo
---
drivers/clk/ti/clk-33xx.c |1 -
1 file changed, 1 deletion(-)
diff
good to me.
Acked-by: Tero Kristo
---
arch/arm/boot/dts/am33xx.dtsi |4
arch/arm/boot/dts/am4372.dtsi |5 +
arch/arm/boot/dts/dra7.dtsi |5 +
arch/arm/boot/dts/omap3.dtsi |5 +
arch/arm/boot/dts/omap4.dtsi |5 +
arch/arm/boot/dts/omap5.dtsi
On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.
Do you have some sort of TRM refer
On 04/24/2014 12:11 PM, Peter Ujfalusi wrote:
Mike, Tero,
On 04/03/2014 09:29 AM, Peter Ujfalusi wrote:
On 04/02/2014 05:12 PM, Tero Kristo wrote:
On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL
On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
On 07/29/2014 07:12 PM, Mike Turquette wrote:
Oh yea, seems this got lost into the myriad of branches I have. I can push
this on top of my for-v3.17/ti-clk-drv if you like.
That is the easiest thing for me. I think that Peter wanted to take
this as
On 07/31/2014 01:42 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-07-30 05:27:07)
On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
On 07/29/2014 07:12 PM, Mike Turquette wrote:
Oh yea, seems this got lost into the myriad of branches I have. I can push
this on top of my for-v3.17/ti-clk-drv
On 07/31/2014 09:28 AM, Tony Lindgren wrote:
* Felipe Balbi [140730 09:23]:
Hi,
On Wed, Jul 30, 2014 at 10:45:41AM -0500, Nishanth Menon wrote:
On Wed, Jul 30, 2014 at 9:40 AM, Felipe Balbi wrote:
HI,
On Tue, Jul 29, 2014 at 11:04:21PM -0700, Tony Lindgren wrote:
* Felipe Balbi [140729 0
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
In some cases, clocks can switch their parent with clk_set_rate, for
example clk_mux can do this in some cases. Current implementation of
clk_change_rate uses un-safe list iteration on the clock children, which
will cause
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
/* Skip children who will be reparented to another clock */
if (child->new_parent && child->new
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
/* Skip children who will be
On 09/29/2014 11:10 AM, Peter Ujfalusi wrote:
It is safe to call the pm sync calls in interrupt context in this driver.
Signed-off-by: Peter Ujfalusi
Thanks, applied to for-v3.18/ti-clk-drv.
-Tero
---
drivers/clk/ti/clk-dra7-atl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/driv
On 09/27/2014 03:57 AM, Behan Webster wrote:
On 09/26/14 17:55, Felipe Balbi wrote:
On Fri, Sep 26, 2014 at 05:31:48PM -0700, Behan Webster wrote:
As written, the __init for ti_clk_get_div_table is in the middle of
the return
type.
The gcc documentation indicates that section attributes should
On 09/30/2014 09:54 AM, Mike Turquette wrote:
Quoting Stephen Boyd (2014-09-29 18:40:23)
On 09/29/14 11:17, Tomeu Vizoso wrote:
Also moves clock state to struct clk_core, but takes care to change as little
API as possible.
struct clk_hw still has a pointer to a struct clk, which is the
impleme
On 09/30/2014 10:07 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-29 01:09:24)
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen
On 03/07/2014 03:09 PM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
CC: Mike Turquette
CC: Tero Kristo
Signed-off-by: Roger Quadros
---
drivers/clk/ti/clk-7xx.c | 11 +++
1 file
usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.
CC: Tero Kristo
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index
On 03/10/2014 02:49 PM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Program USB_DLL_M2 output to half rate as well.
Patch depends on
https://www.mail-archive.com/linux-omap@vger.kernel.org/msg101300.html
CC: Mike Turquette
CC: Tero
On 05/19/2014 10:41 AM, Dan Carpenter wrote:
This one does feel like a bug in the original code as you mention. I
have added the TI devs to the CC list so they can help us.
Yes this is a bug, the dra7_apll_enable() should return some sort of
error code if the lock fails. EBUSY maybe?
-Tero
: Tero Kristo
Mike, do you want to queue this as a fix or shall I add this to be
queued for 3.16?
-Tero
---
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index b986f61..efc71a0 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -77,13 +77,11 @@ static int
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
Mike,
On 04/24/2014 06:03 PM, Tero Kristo wrote:
On 04/24/2014 12:11 PM, Peter Ujfalusi wrote:
Mike, Tero,
On 04/03/2014 09:29 AM, Peter Ujfalusi wrote:
On 04/02/2014 05:12 PM, Tero Kristo wrote:
On 04/02/2014 04:48 PM, Peter Ujfalusi wrote
On 04/30/2014 02:39 PM, Peter Ujfalusi wrote:
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.
Signed-off-by: Peter Ujfalusi
Thanks, queued for 3.15-rc/ti-clk-drv.
-Tero
---
drivers/clk/ti/clk-54xx.c | 6 ++
1
On 04/30/2014 03:30 PM, Tero Kristo wrote:
On 04/30/2014 02:41 PM, Peter Ujfalusi wrote:
In OMAP5 bit 8 in PRCM registers are not defined (Reserved) unlike their
counterpart in OMAP4.
It is better to not write to these bits.
Yeah, looks like this bug was copied over from the legacy clock data
On 04/30/2014 03:31 PM, Tero Kristo wrote:
On 04/30/2014 02:41 PM, Peter Ujfalusi wrote:
abe_iclk's parent is aess_fclk and not abe_clk.
Also correct the parameters for clock rate calculation as used for OMAP4
since in PRCM level there's no difference between the two platform
regardi
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