On 7/7/2018 5:09 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-04 23:55:21)
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c
b/drivers/clk/qcom/lpasscc-sdm845.c
new file mode 100644
index 000..5285b26
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -0,0 +1,243 @@
+// SPDX
On 7/7/2018 5:12 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-04 23:55:20)
diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
new file mode 100644
index 000..fe7378b
--- /dev/null
+++ b/Documentation
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 2 ++
.../devicetree/bindings/clock/qcom,lpasscc.txt | 33 ++
inclu
ntroller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SDM845
.../device
tree flag.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm845.c | 35 +++
drivers/clk/qcom/lpasscc-sdm845.c | 189 ++
4 files changed, 234 insertions
On 8/8/2018 12:54 AM, skan...@codeaurora.org wrote:
On 2018-08-07 04:12, Sudeep Holla wrote:
On Mon, Aug 06, 2018 at 01:54:24PM -0700, skan...@codeaurora.org wrote:
On 2018-08-03 16:46, Stephen Boyd wrote:
>Quoting Taniya Das (2018-07-24 03:42:49)
>>diff --git
>>a/Documenta
update the Kconfig.
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Taniya Das (3):
clk: qcom: Move frequency table macro to common file
dt-bindings: clock: Introduce QCOM Display clock bindings
clk
Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 ++
drivers/clk/qcom/gcc-apq8084.c| 2 --
drivers/clk/qcom/gcc-ipq4019.c| 2 --
drivers/clk/qcom/gcc-ipq8074.c
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/qcom,dispcc.txt | 19 +
include/dt-bindings/clock/qcom,dispcc-sdm845.h
Hello Stephen,
Thanks for the comments.
On 6/19/2018 8:53 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-13 03:33:15)
[v2]
* Removed unused header file includes.
* Moved the frequency table macro to a common file [1].
* Move to pll config to probe.
* Update SoC name in
On 8/28/2018 2:34 AM, Stephen Boyd wrote:
Quoting Stephen Boyd (2018-08-23 11:25:41)
Quoting Taniya Das (2018-08-22 03:28:31)
H. Ok. That won't work then. recalc_rate() better not try to
populate the frequency table then or it will not work. So I suppose it
needs to fallba
On 8/8/2018 11:52 AM, Stephen Boyd wrote:
Quoting skan...@codeaurora.org (2018-08-06 13:46:05)
On 2018-08-03 15:24, Stephen Boyd wrote:
Quoting skan...@codeaurora.org (2018-08-03 12:52:48)
On 2018-08-03 12:40, Evan Green wrote:
Hi Taniya,
On Tue, Jul 24, 2018 at 3:44 AM Taniya Das wrote
/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++
1 file changed, 3 insertions(+)
Acked-by: Rob Herring
Reviewed-by: Taniya Das
--
To unsubscribe from this list: send the line "unsubscribe linux-clk" in
the body of a message to majord...@vger.kernel.org
More majordomo inf
cc_qspi_core_clk_src.clkr,
+ [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
+ [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
Reviewed-by: Taniya Das
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index
-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 2 +
drivers/clk/qcom/clk-rcg2.c | 224
2 files changed, 226 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index dbd5a9e..e6300e0 100644
--- a/drivers/clk/qcom
c_register_rcg_dfs and instead pass array of
clk_rcg2.
* Add a dfs_enable flag to identify if dfs mode is enabled.
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequenc
Hello Craig,
Could you please correct the authorship and also provide the reference
to code where this is picked from?
On 8/11/2018 1:51 AM, Craig Tatlor wrote:
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to p
Hello Stephen,
Thanks for the changes, I have tested the changes and would require the
change mentioned below for this to work.
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das
On 8/21/2018 9:00 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-21 04:36:20)
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add
On 7/27/2018 3:35 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-23 03:54:35)
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
This is fine to merge as long
Hi Doug,
Please find my comments inline.
On 7/18/2018 11:34 PM, Douglas Anderson wrote:
Add both the interface and core clock.
Signed-off-by: Douglas Anderson
---
drivers/clk/qcom/gcc-sdm845.c | 73 +++
1 file changed, 73 insertions(+)
diff --git a/drivers
On 7/19/2018 11:25 PM, Doug Anderson wrote:
Hi,
On Thu, Jul 19, 2018 at 4:04 AM, Taniya Das wrote:
Hi Doug,
Please find my comments inline.
On 7/18/2018 11:34 PM, Douglas Anderson wrote:
Add both the interface and core clock.
Signed-off-by: Douglas Anderson
---
drivers/clk/qcom
the corresponding
performance corner and thus would aggregate and request the desired
performance state to genpd.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-pd.c | 193 ++
drivers/clk/qcom/clk-pd.h | 55
The power domain class is being initialized for clocks which has
an associated power domains before registering the clocks with
the clock framework.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-regmap.h | 5 +
drivers/clk/qcom/common.c | 17 +++--
2 files changed, 12
mappings. This depends on power domain drivers of
SDM845 https://lkml.org/lkml/2018/6/27/7.
Taniya Das (4):
clk: qcom: Add support to request power domain state
clk: qcom: Initialize the power domain class for each clock
clk: qcom: Add prepare/unprepare clock ops for PLL/RCG
clk: qcom: sdm845
performance state to
genpd framework when a new frequency is being requested.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 52 +++---
drivers/clk/qcom/clk-rcg2.c | 61 +++-
2 files changed, 96 insertions(+), 17
Test code for GCC Power Domain Voting for root clocks/plls.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +
drivers/clk/qcom/gcc-sdm845.c| 83 +---
drivers/clk/qcom/vdd-level.h | 31 ++
3 files changed, 101
pll config to probe.
* Update SoC name in device tree binding and
also update the Kconfig.
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Taniya Das (1):
clk: qcom: Add display clock
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
would allow display drivers to probe and
control their clocks.
Taniya Das (1):
clk: qcom: Add display clock controller driver for SDM845
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c | 687
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
On 7/24/2018 3:24 AM, Douglas Anderson wrote:
Add both the interface and core clock.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Only 19.2, 100, 150, and 300 MHz now.
- All clocks come from MAIN rather than EVEN.
- Use parent map 0 instead of new parent map 9.
drivers/clk/qcom/g
turn -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-bindings: cpufreq: Introduce QCOM CPUFREQ Firmware bindings
Hello Viresh,
Thanks for your review comments.
On 7/18/2018 11:16 AM, Viresh Kumar wrote:
On 18-07-18, 11:07, Taniya Das wrote:
+static int qcom_cpu_resources_init(struct platform_device *pdev,
+ struct device_node *np, unsigned int cpu
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +++
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
++ Display driver team,
On 7/9/2018 8:36 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-09 02:34:07)
On 7/9/2018 1:07 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-09 00:07:21)
On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> Why is the nocache flag needed? Applies to
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 10
iver would not be used as module, also updated
the Kconfig to bool from tristate.
* Updated the subsystem in device tree bindings.
[v1]
* Fixed compilation reported by Amit K.
Taniya Das (2):
dt-bindings: cpufreq: Introduce QCOM CPUFREQ Firmware bindings
cpufreq: qcom-hw: Add support
, Jun 12, 2018 at 04:32:35PM +0530, Taniya Das wrote:
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 158 +++
Hello Stephen,
Thanks for your review comments.
On 7/9/2018 12:34 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-28 04:47:30)
Dynamic Frequency switch is a feature of clock controller by which request
from peripherals allows automatic switching frequency of input clock.
There are various
om qcom_cc_register_rcg_dfs and instead pass array of
clk_rcg2.
* Add a dfs_enable flag to identify if dfs mode is enabled.
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the freq
-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 2 +
drivers/clk/qcom/clk-rcg2.c | 173
2 files changed, 175 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index b209a2f..bffb625 100644
--- a/drivers/clk/qcom
QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index
SPDX headers updated for common/branch/pll/regmap files.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 10 +-
drivers/clk/qcom/clk-alpha-pll.h | 14 ++
drivers/clk/qcom/clk-branch.c| 10 +-
drivers/clk/qcom/clk-branch.h| 14
Hello Stephen,
On 7/13/2018 1:55 PM, spa...@codeaurora.org wrote:
On 2018-07-13 01:11, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-12 10:21:33)
++ Display driver team,
On 7/9/2018 8:36 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-07-09 02:34:07)
>>
>>
>>
Thanks Stephen for the review.
On 4/6/2018 4:50 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-03-28 23:17:53)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh.txt
b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt
new file mode 100644
index 000..8222c88
--- /dev/null
[v2]
* Addressed comments from Stephen
* Addressed comments from Evan
This patch series adds a driver and device tree documentation binding
for the clock control via Resource Power Manager-hardened (RPMh) on some
Qualcomm Technologies, Inc, SoCs such as SDM845. The clock RPMh driver
would sen
From: Amit Nischal
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: David Collins
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom
From: Amit Nischal
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom
[v2]
* Addressed review comments given in v1 series
This series implements the below logic for the GDSCs
1. logic to reset the AON logic before or assert/deassert the block
control reset removing the clamp io for few GDSCs on SDM845 SoC.
2. It also introduces the requirement to poll for h
,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya
[v2]
* Addressed review comments given in v1 series
This series implements the below logic for the GDSCs
1. logic to reset the AON logic before or assert/deassert the block
control reset removing the clamp io for few GDSCs on SDM845 SoC.
2. It also introduces the requirement to poll for h
From: Amit Nischal
For some gdscs, it might take longer time up to 500us for updating their
status. Update the timeout value for all GDSC polling status.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gdsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
for at least 1us before being de-asserted.
Signed-off-by: Taniya Das
Signed-off-by: Amit Nischal
---
drivers/clk/qcom/gdsc.c | 22 --
drivers/clk/qcom/gdsc.h | 4 +++-
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom
Hello Stephen,
Thanks for the review comments.
On 4/6/2018 4:54 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-02 03:45:44)
From: Amit Nischal
For some gdscs, it might take longer time up to 500us for
updating their status. So add support for the same by
defining a new flag
Hello Stephen,
Thanks for the review comments.
On 4/6/2018 10:10 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-02 03:45:45)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index e89584e..e0c83ba 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -83,6
Changes in v4:
* Cleanup the GPUCC code to keep only the clocks which would be requested
from the GPU client SW.
* Clean up of code as well as header file clock IDs.
* Due to the above cleanup the patches to enable/disable clocks for GPU GDSC
requirement is not supported : https://patchwork.ker
From: Amit Nischal
Add support for the graphics clock controller found on SDM845
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile
From: Amit Nischal
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Amit Nischal
---
.../devicetree/bindings/clock/qcom,gpucc.txt | 18
include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 +++
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +++
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
[v2]
* Fixed the alignment issues in "qcom_cpufreq_fw_target_index" for dev_err
and
also for "qcom_cpu_resources_init".
* Removed ret = 0 from qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_ini
Hello Stephen,
On 11/22/2018 12:37 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-09 17:44:16)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f..ba8ff99 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6
Hello Rob,
On 11/13/2018 5:49 AM, Rob Herring wrote:
On Sat, Nov 10, 2018 at 07:14:15AM +0530, Taniya Das wrote:
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 4 +++-
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++
in
roller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (3):
dt-bindings: clock: Update GCC bindings for protected-clocks
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpa
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom
protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
Hello Stephen,
On 11/5/2018 12:04 PM, Stephen Boyd wrote:
Quoting Amit Nischal (2018-08-12 23:33:04)
For some of the GDSCs, there is a requirement to enable/disable the
few clocks before turning on/off the gdsc power domain. Add support
for the same by specifying a list of clk_hw pointers per g
Hello Stephen,
On 11/5/2018 12:07 PM, Stephen Boyd wrote:
Quoting Amit Nischal (2018-08-12 23:33:07)
+
+static int gpu_cc_sdm845_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ unsigned int value, mask;
+ int ret;
+
+ regmap = qcom_cc_map(pdev, &gpu_cc_
s into a better shape. Thanks for your efforts..
On 02-12-18, 09:25, Taniya Das wrote:
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
+struct cpufreq_qcom {
+ struct cpufreq_frequency_table *table;
+ void __iomem *perf_state_reg;
+ cpumask_t related_cpus;
+};
+
+static stru
This adds the low pass audio clock controller node to sdm845 based on
the example in the bindings.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 +++-
arch/arm64/boot/dts/qcom/sdm845.dtsi| 8
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a
The GCC lpass clocks are updated as protected, so clean up the ifdefers.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index c782e62..ba8ff99 100644
--- a/drivers
Hello Stephen,
On 11/27/2018 2:44 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 23:53:41)
+
+static struct clk_branch lpass_qdsp6ss_core_clk = {
+ .halt_reg = 0x20,
+ /* CLK_OFF would not toggle until LPASS is not out of reset */
Is this really "CLK_OFF won
Hello Stephen,
On 11/29/2018 2:40 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 23:53:41)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f..ba8ff99 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6
child nodes and use reg-names to differentiate various
domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (3):
dt-bindings: clock:
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Reviewed-by: Rob Herring
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 4 +++-
.../devicetree/bindings/clock/qcom,lpasscc.txt
protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Reviewed-by: Rob Herring
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation
Hello Rob,
On 11/27/2018 12:28 AM, Rob Herring wrote:
On Wed, Nov 21, 2018 at 10:02:36AM -0800, Matthias Kaehlcke wrote:
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managin
Hello Matthias,
On 11/21/2018 11:32 PM, Matthias Kaehlcke wrote:
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled b
Hello Matthias,
On 11/22/2018 12:11 AM, Matthias Kaehlcke wrote:
Hi Taniya,
thanks for respinning, a few nits inline.
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The
Hello Stephen,
Thanks for the patch, I have updated the latest series with the patch
and few comments from Matthias.
On 11/21/2018 11:53 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 02:42:47)
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index d5ee456..789b2e0
d the alignment issues in "qcom_cpufreq_fw_target_index" for dev_err
and
also for "qcom_cpu_resources_init".
* Removed ret = 0 from qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove ini
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +++
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Stephen Boyd
Signed-off-by: Taniya Das
---
drivers/cpufreq
Hello Viresh,
On 12/4/2018 10:42 AM, Viresh Kumar wrote:
Hi Taniya,
Sorry that I haven't been reviewing it much from last few iterations as I was
letting others get this into a better shape. Thanks for your efforts..
On 02-12-18, 09:25, Taniya Das wrote:
+++ b/drivers/cpufreq/qcom-cp
protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
us
domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom:
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 16 +
.../devicetree/bindings/clock/qcom,lpasscc.txt
Hello Vinod,
On 11/9/2018 3:20 PM, Vinod Koul wrote:
Device tree node name are not supposed to have "_" in them so fix the
node name use of xo_board to xo-board
Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for
QCS404")
Signed-off-by: Vinod Koul
---
Steve: RobH poi
Hello Stephen,
Thanks for your comments.
On 11/4/2018 9:50 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-02 20:06:00)
Hello Stephen,
On 10/18/2018 5:02 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-11 04:36:01)
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
Hello Stephen,
Thanks for your review comments.
On 7/9/2018 5:24 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-23 07:19:27)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
new file mode 100644
index 000..af437e0
--- /dev/null
+++ b/drivers/clk/qcom
On 7/9/2018 11:46 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-08 20:38:03)
Hello Stephen,
Thanks for your review comments.
On 7/9/2018 5:24 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-23 07:19:27)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc
On 7/9/2018 1:07 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-09 00:07:21)
On 7/9/2018 11:46 AM, Stephen Boyd wrote:
> Why is the nocache flag needed? Applies to all clks in this file.
>
This flag is required for all RCGs whose PLLs are controlled outside the
at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Taniya Das (2):
clk: qcom: Add support for RCG to register for DFS
clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845
drivers/clk/qcom/clk-rcg.h|
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