On 11/26/2012 10:31 PM, Oleg Nesterov wrote:
On 11/26, Suzuki K. Poulose wrote:
@@ -121,8 +125,11 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe,
struct pt_regs *regs)
* to be executed.
*/
regs->nip = utask->vaddr + MAX_UINSN_BYTES;
+ regs->ms
On 11/26/2012 11:40 PM, Sebastian Andrzej Siewior wrote:
On 11/26/2012 12:05 PM, Suzuki K. Poulose wrote:
diff --git a/arch/powerpc/include/asm/probes.h
b/arch/powerpc/include/asm/probes.h
index 5f1e15b..836e9b9 100644
--- a/arch/powerpc/include/asm/probes.h
+++ b/arch/powerpc/include/asm
./perf[0x414a61]
Make sure we remove the node from the rblist before we delete the
node. The rblist__remove_node() will invoke rblist->node_delete,
which will take care of deleting the node with the suitable function
provided by the user.
Reported-by: Ananth N. Mavinakayanahalli
Signed-off-by: Suz
On 08/29/2012 11:59 AM, David Ahern wrote:
On 8/29/12 12:00 AM, Suzuki K. Poulose wrote:
The following commit:
authorDavid Ahern
Tue, 31 Jul 2012 04:31:33 + (22:31 -0600)
committerArnaldo Carvalho de Melo
Fri, 3 Aug 2012 13:39:51 + (10:39 -0300)
commit
ser.
Signed-off-by: Suzuki K Poulose
Cc: David Ahern
---
tools/perf/util/intlist.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/intlist.c b/tools/perf/util/intlist.c
index fd530dc..77c504f 100644
--- a/tools/perf/util/intlist.c
+++ b/tools/perf/util/intlis
The nr_entries in rblist is never decremented when an element
is deleted. Also, use rblist__remove_node to delete a node in
rblist__delete(). This would keep the nr_entries sane.
Signed-off-by: Suzuki K. Poulose
Cc: David S. Ahern
---
tools/perf/util/rblist.c |4 ++--
1 files changed, 2
On 10/04/2013 07:14 PM, Andi Kleen wrote:
> On Fri, Oct 04, 2013 at 04:00:12PM +0530, Janani Venkataraman wrote:
>> Hi all,
>>
>> The following series implements an infrastructure for capturing the core of
>> an
>> application without disrupting its process.
>
> The problem is that gcore et.al.
On 09/12/2013 12:57 AM, KOSAKI Motohiro wrote:
> (9/3/13 4:39 AM), Janani Venkataraman wrote:
>> Hello,
>>
>> We are working on an infrastructure to create a system core file of a
>> specific
>> process at run-time, non-disruptively. It can also be extended to a
>> case where
>> a process is able t
On 09/07/2012 07:05 AM, Benjamin Herrenschmidt wrote:
On Tue, 2012-08-21 at 17:12 +0530, Suzuki K. Poulose wrote:
There are some device-tree nodes, whose values are of type phys_addr_t.
The phys_addr_t is variable sized based on the CONFIG_PHSY_T_64BIT.
Change these to a fixed unsigned long
e the context in arch_uprobe_abort_xol() (Oleg)
---
Suzuki K. Poulose (4):
kprobes/powerpc: Do not disable External interrupts during single step
powerpc: Move the single step enable code to a generic path
uprobes/powerpc: Introduce routines for save/restore context
up
From: Suzuki K. Poulose
External/Decrement exceptions have lower priority than the Debug Exception.
So, we don't have to disable the External interrupts before a single step.
However, on BookE, Critical Input Exception(CE) has higher priority than a
Debug Exception. Hence we mask them.
S
From: Suzuki K. Poulose
This patch moves the single step enable code used by kprobe to a generic
routine header so that, it can be re-used by other code, in this case,
uprobes. No functional changes.
Signed-off-by: Suzuki K. Poulose
Cc: Ananth N Mavinakaynahalli
Cc: Kumar Gala
Cc
From: Suzuki K. Poulose
Introduce routines for saving and restoring the context
befre/after the single step. No functional changes involved.
These will be extended later to save/restore more info about
the process once we replace the ptrace helpers.
Signed-off-by: Suzuki K. Poulose
---
arch
From: Suzuki K. Poulose
Replace the ptrace helpers with the powerpc generic routines to
enable/disable single step. We save/restore the MSR (and DCBR for BookE)
across for the operation. We don't have to disable the single step,
as restoring the MSR/DBCR would restore the previous state.
S
On 12/03/2012 08:45 PM, Ananth N Mavinakayanahalli wrote:
On Mon, Dec 03, 2012 at 08:39:35PM +0530, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose
Introduce routines for saving and restoring the context
befre/after the single step. No functional changes involved.
These will be extended
On 12/03/2012 08:37 PM, Suzuki K. Poulose wrote:
From: Suzuki K. Poulose
External/Decrement exceptions have lower priority than the Debug Exception.
So, we don't have to disable the External interrupts before a single step.
However, on BookE, Critical Input Exception(CE) has higher pri
On 12/15/2012 01:32 AM, Oleg Nesterov wrote:
On 12/03, Suzuki K. Poulose wrote:
Replace the ptrace helpers with the powerpc generic routines to
enable/disable single step. We save/restore the MSR (and DCBR for BookE)
across for the operation. We don't have to disable the single ste
from arch/powerpc/include/uapi to build the perf tool.
Signed-off-by: Sukadev Bhattiprolu
Without this patch, I couldn't build perf on powerpc, with 3.7.0-rc2
Tested-by: Suzuki K. Poulose
Thanks
Suzuki
---
tools/perf/perf.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
dif
On 08/07/2012 09:42 PM, Sebastian Andrzej Siewior wrote:
by the time we get here (after we pass cleanup_ret) uprobe is always is
set. If it is NULL we leave very early in the code.
Signed-off-by: Sebastian Andrzej Siewior
---
kernel/events/uprobes.c | 16 +++-
1 file changed, 7
On 08/08/2012 03:05 PM, Sebastian Andrzej Siewior wrote:
On 08/08/2012 11:10 AM, Suzuki K. Poulose wrote:
--- a/kernel/events/uprobes.c
+++ b/kernel/events/uprobes.c
@@ -1528,17 +1528,15 @@ cleanup_ret:
utask->active_uprobe = NULL;
utask->state = UTASK_RUNNING;
}
- if (uprobe) {
- if (!(
'phys_addr_t' (which
is 32bit on some ppc32 and 64 bit on ppc64 and some ppc32)
* Rebased the patch to use recently fixed prom_update_property()
which would add the property if it didn't exist.
---
Suzuki K. Poulose (2):
[powerpc] Change memory_limit from phys_add
the different sized values and then change
the above.
Suggested-by: Benjamin Herrenschmidt
Signed-off-by: Suzuki K. Poulose
---
arch/powerpc/include/asm/setup.h|2 +-
arch/powerpc/kernel/fadump.c|3 +--
arch/powerpc/kernel/machine_kexec.c |2 +-
arch/powerpc/kernel/prom.c
of the memory
regions.
Tested this patch on ppc64 and ppc32(ppc440) with a kexec-tools
patch by Mahesh.
Signed-off-by: Suzuki K. Poulose
Tested-by: Mahesh J. Salgaonkar
---
arch/powerpc/kernel/machine_kexec.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
di
applies on top of the patches posted by Oleg at :
https://lkml.org/lkml/2012/10/28/92
Patches have been verified on Power6 and PPC440 (BookE).
---
Suzuki K. Poulose (2):
powerpc: Move the single step enable code to a generic path
uprobes/powerpc: Make use of generic routines to
From: Suzuki K. Poulose
This patch moves the single step enable code used by kprobe to a generic
routine so that, it can be re-used by other code, in this case,
uprobes.
Signed-off-by: Suzuki K. Poulose
Cc: linuxppc-...@ozlabs.org
---
arch/powerpc/include/asm/probes.h | 29
From: Suzuki K. Poulose
Replace the ptrace helpers with the powerpc generic routines to
enable/disable single step. We save/restore the MSR (and DCBR for BookE)
across for the operation.
Signed-off-by: Suzuki K. Poulose
---
arch/powerpc/include/asm/uprobes.h |4
arch/powerpc/kernel
From: Suzuki K. Poulose
Uprobes uses emulate_step in sstep.c, but we haven't explicitly specified
the dependency. On pseries HAVE_HW_BREAKPOINT protects us, but 44x has no
such luxury.
Consolidate other users that depend on sstep and create a new config option.
Signed-off-by: Ana
On 18/07/16 20:51, Mathieu Poirier wrote:
With this commit [1] address range filter information is now found
in the struct hw_perf_event::addr_filters. As such pass the event
itself to the coresight_source::enable/disable() functions so that
both event attribute and filter can be accessible for
On 18/07/16 20:51, Mathieu Poirier wrote:
This patch implements the required API needed to access
and retrieve range and start/stop filters from the perf core.
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 146 ---
drivers/hwtracing/c
Cc:
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/smp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 62ff3c0..d242e81 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kern
;)
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: James Morse
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/smp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index d242e81..ec08b7a 100644
--- a/arch/arm64/kernel/sm
On 20/07/16 21:38, Mathieu Poirier wrote:
Up to now function coresight_build_path() was counting on a sink to
have been selected (from sysFS) prior to being called. This patch
adds a string argument so that a sink matching the argument can be
selected.
static int _coresight_build_path(struc
On 16/09/16 18:07, Mathieu Poirier wrote:
On 14 September 2016 at 07:53, Suzuki K Poulose wrote:
The mode of operation of the TMC tracked in drvdata->mode is defined
as a local_t type. This is always checked and modified under the
drvdata->spinlock and hence we don't need local_t
On 19/09/16 17:59, Suzuki K Poulose wrote:
On 16/09/16 18:07, Mathieu Poirier wrote:
On 14 September 2016 at 07:53, Suzuki K Poulose wrote:
Cheers
Suzuki
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the
userspace.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Rutland
Signed-off-by: Steve Capper
[ ABI documentation updates, hotplug notifiers ]
Signed-off-by: Suzuki K Poulose
---
Changes since V5:
- Add hotplug notifier to {add/remove} the attributes when the CPU is brought
{online/offline
atch gets
rid of the incorrect dma_free_coherent() call.
Fixes: commit de5461970b3e9e194 ("coresight: tmc: allocating memory when
needed")
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc.c | 3 ---
1 file changed, 3 deletions(-)
s all
such error messages to print something more meaningful.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etb10.c | 6 ++
drivers/hwtracing/coresight/coresight-etm4x.c | 6 ++
drivers/hwtracing/coresight/coresight-tmc.c | 6 ++
3
rly(i.e, either NULL or valid conns array).
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight.c
b/drivers/hwtracing/core
At present the ETF or ETR gives out the entire device
buffer, even if there is less or even no trace data
available. This patch limits the trace data given out to
the actual trace data collected.
Cc: mathieu.poir...@linaro.org
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight
entries do. While at it, correct the comment for A57 and the A53 entry.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b
Use the defined symbol rather than hardcoding the value to
check whether the TMC buffer is full.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing
This patch cleans up the error handling path for tmc_probe
as a side effect of the removal of the spurious dma_free_coherent().
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc.c | 36 ++---
1 file changed, 17 insertions
on.
May be the checkpatch needs to be fixed ?
Suzuki K Poulose (7):
coresight: Remove erroneous dma_free_coherent in tmc_probe
coresight: Consolidate error handling path for tmc_probe
coresight: Fix csdev connections initialisation
coresight: tmc: Limit the trace to available data
s on mathieu's coresight/next tree [1]
https://git.linaro.org/kernel/coresight.git next
Reported-by: Venkatesh Vivekanandan
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 32 +++--
drivers/hwtracing/coresight/
Get rid of the superfluous mode parameter and the check for
the mode in tmc_etX_enable_sink_{perf/sysfs}. While at it, also
remove the unnecessary WARN_ON() checks.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 18
The tmc_etr_enable_hw() fills the buffer with 0's before enabling
the hardware. So, we don't need an explicit memset() in
tmc_enable_etr_sink_sysfs() before calling the tmc_etr_enable_hw().
This patch removes the explicit memset from tmc_enable_etr_sink_sysfs.
Signed-off-by: Suzuki
On 27/07/16 18:29, fu@linaro.org wrote:
From: Tomasz Nowicki
This commit provides APEI arch-specific bits for aarch64
Meanwhile,
(1)add a new subfunction "hest_ia32_init" for
"acpi_disable_cmcff" which is used by IA-32 Architecture
Corrected Machine Check (CMC).
(2)move HEST type (ACPI_HES
On 13/09/16 16:41, Mathieu Poirier wrote:
On 13 September 2016 at 06:20, Venkatesh Vivekanandan
wrote:
tmc_etb_dump_hw is never called in sysFS mode to collect trace from
hardware, because drvdata->mode is set to CS_MODE_DISABLED at
tmc_disable_etf/etr_sink
static void tmc_etb_disable_hw(struc
On 14/09/16 12:30, Venkatesh Vivekanandan wrote:
On Wed, Sep 14, 2016 at 3:26 PM, Suzuki K Poulose mailto:suzuki.poul...@arm.com>> wrote:
On 13/09/16 16:41, Mathieu Poirier wrote:
On 13 September 2016 at 06:20, Venkatesh Vivekanandan
mailto:venkatesh.viv
s on mathieu's coresight/next tree [1]
https://git.linaro.org/kernel/coresight.git next
Reported-by: Venkatesh Vivekanandan
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 32 +++--
drivers/hwtracing/coresight/
On 30/08/16 17:19, Mathieu Poirier wrote:
Using the PMU::set_drv_config() callback to enable the CoreSight
sink that will be used for the trace session.
+int cs_etm_set_drv_config(struct perf_evsel_config_term *term)
+{
+ int ret;
+ char enable_sink[ENABLE_SINK_MAX];
+
+ snpr
On 17/08/16 20:42, Zhengyu Shen wrote:
MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6
QuadPlus devices, but this driver only suppor
On 17/08/16 20:42, Zhengyu Shen wrote:
MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6
QuadPlus devices, but this driver only suppor
On 31/08/16 15:14, Mathieu Poirier wrote:
On 31 August 2016 at 03:37, Suzuki K Poulose wrote:
On 30/08/16 17:19, Mathieu Poirier wrote:
Using the PMU::set_drv_config() callback to enable the CoreSight
sink that will be used for the trace session.
+int cs_etm_set_drv_config(struct
On 26/08/16 18:00, Catalin Marinas wrote:
On Fri, Aug 26, 2016 at 05:16:27PM +0100, Will Deacon wrote:
On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote:
On 26/08/16 14:04, Suzuki K Poulose wrote:
It might be worth looking to see if we can pass the ctr as an extra
parameter
On 02/09/16 16:52, Catalin Marinas wrote:
On Fri, Aug 26, 2016 at 10:22:13AM +0100, Suzuki K. Poulose wrote:
On 25/08/16 18:26, Catalin Marinas wrote:
Just a heads up. I have a patch [1] which moves the "check_local_cpu_errata()"
around to smp_prepare_boot_cpu(). This patch sh
On 04/08/16 17:53, Mathieu Poirier wrote:
Now that PMU specific configuration is available as part of the event,
lookup the sink identified by users from the perf command line and build
a path from source to sink.
With this functionality it is no longer required to select a sink in a
separate st
On 22/08/16 14:02, Will Deacon wrote:
On Thu, Aug 18, 2016 at 02:10:32PM +0100, Suzuki K Poulose wrote:
Systems with differing CPU i-cache/d-cache line sizes can cause
problems with the cache management by software when the execution
is migrated from one to another. Usually, the application
, otherwise the compiler
generates the bitmap test.
Because of the early call to static_branch_enable() via
check_local_cpu_errata() -> update_cpu_capabilities(), the jump labels
are initialised in cpuinfo_store_boot_cpu().
Cc: Will Deacon
Cc: Suzuki K. Poulose
Signed-off-by: Catalin Mari
Adds helpers for decoding/encoding the PC relative addresses for adrp.
This will be used for handling dynamic patching of 'adrp' instructions
in alternative code patching.
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
Changes since V1:
Zyngier
Cc: Andre Przywara
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
Changes since V1:
- Add align_down macro. Couldn't find the best place to add it.
Didn't want to add this to uapi/ headers where the kernel's generic
ALIGN helpers are really defined. For the tim
bit more reader friendly.
Cc: Andre Przywara
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
Changes since V1:
- Add comments for iss field definitions for other exceptions.
---
arch/arm64/include/asm/esr.h | 76
(i.e, avoiding to lookup the system wide value of CTR_EL0
via read_system_reg), we keep track of the pointer to table entry for
CTR_EL0 in the CPU feature infrastructure.
Cc: Mark Rutland
Cc: Andre Przywara
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64
: Suzuki K Poulose
---
arch/arm64/include/asm/assembler.h | 24
arch/arm64/kernel/hibernate-asm.S | 2 +-
arch/arm64/kernel/relocate_kernel.S | 2 +-
3 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h
b/arch/arm64
.
Suzuki K Poulose (9):
arm64: Set the safe value for L1 icache policy
arm64: Use consistent naming for errata handling
arm64: Rearrange CPU errata workaround checks
arm64: alternative: Disallow patching instructions using literals
arm64: insn: Add helpers for adrp offsets
arm64
we have
initialised the system wide CPU feature values.
Cc: Mark Rutland
Cc: Andre Przywara
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpufeature.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 30 --
arch/arm6
lect the same.
2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds()
Use errata_workarounds instead of _errata.
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpufeature.h | 4 ++--
arch/arm64/kernel/cpu_errata.c | 4 ++--
arch/arm64/kernel/cpufeature.c |
-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpufeature.h | 2 +-
arch/arm64/kernel/cpufeature.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h
b/arch/arm64/include/asm/cpufeature.h
index 7099f26..f6f5e49 100644
--- a/arch
r
Cc: Andre Przywara
Cc: Mark Rutland
Cc: Catalin Marinas
Suggested-by: Will Deacon
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/alternative.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
index d2ee1b2..6b
On 26/08/16 14:04, Suzuki K Poulose wrote:
On 26/08/16 12:03, Ard Biesheuvel wrote:
Hello Suzuki,
For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0
via read_system_reg), we keep track of the pointer to table entry for
CTR_EL0 in the CPU feature infrastructure
On 26/08/16 12:03, Ard Biesheuvel wrote:
Hello Suzuki,
For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0
via read_system_reg), we keep track of the pointer to table entry for
CTR_EL0 in the CPU feature infrastructure.
IIUC it is the runtime sorting of the arm64_f
Hi Mark,
On 16/08/17 15:10, Mark Rutland wrote:
On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
+/*
+ * struct dsu_pmu - DSU PMU descriptor
+ *
+ * @pmu_lock : Protects accesses to DSU PMU register from multiple
+ * CPUs.
+ * @hw_events
On 17/08/17 16:57, Mark Rutland wrote:
On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote:
On 16/08/17 15:10, Mark Rutland wrote:
On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote:
+static struct attribute *dsu_pmu_event_attrs[] = {
+ DSU_EVENT_ATTR(cycles
On 17/10/17 17:11, Will Deacon wrote:
On Tue, Oct 17, 2017 at 04:24:23PM +0100, Mark Rutland wrote:
On Tue, Oct 10, 2017 at 11:33:00AM +0100, Suzuki K Poulose wrote:
Make use of the new generic helper to convert an of_node of a CPU
to the logical CPU id in parsing the topology.
Cc: Catalin
On 17/10/17 17:20, Suzuki K Poulose wrote:
On 17/10/17 17:11, Will Deacon wrote:
On Tue, Oct 17, 2017 at 04:24:23PM +0100, Mark Rutland wrote:
On Tue, Oct 10, 2017 at 11:33:00AM +0100, Suzuki K Poulose wrote:
Make use of the new generic helper to convert an of_node of a CPU
to the logical CPU
This patch documents the devicetree bindings for ARM DSU PMU.
Cc: Mark Rutland
Cc: Will Deacon
Cc: devicet...@vger.kernel.org
Cc: frowand.l...@gmail.com
Acked-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
Changes since V3:
- Fixed node name in the example, suggested by Rob
Use the new generic helper of_cpu_node_to_id() instead
of using our own version to map a device node to logical CPU
number.
Acked-by: Marc Zyngier
Signed-off-by: Suzuki K Poulose
---
Changes since V3:
- Reflect the change in the helper name and return value.
---
drivers/irqchip/irq-gic-v3.c
Reuse the new generic helper, of_cpu_node_to_id() to map a
given CPU phandle to a logical CPU number.
Acked-by: Mathieu Poirier
Tested-by: Leo Yan
Signed-off-by: Suzuki K Poulose
---
Changes since V4:
- Fix a regression introduced in v4, reported by bugrobot
Changes since V3:
- Reflect the
Export perf_event_update_userpage() so that PMU driver using them,
can be built as modules.
Cc: Peter Zilstra
Signed-off-by: Suzuki K Poulose
---
kernel/events/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 9d93db81fa36
d-by: Marc Zyngier
Reviewed-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
Changes since V6:
- Use faster of_cpu_device_node_get instead of of_get_cpu_node(),
which now falls back to latter if called in early.
Changes since V3:
- Renamed the helper to of_cpu_node_to_id(), sugges
ed with DSU
Changes since V4:
- Fix regressions introduced by v4, with the rename of generic
helper.
- Added reviewed-by tag from Rob
Changes since V3:
- Rename the of generic helper to of_cpu_node_to_id(), and return
-ENODEV upon failure than nr_cpus_id
- Fix node name in
drivers.
The driver only supports ARM64 at the moment. It can be extended
to support ARM32 by providing register accessors like we do in
arch/arm64/include/arm_dsu_pmu.h.
Cc: Mark Rutland
Cc: Will Deacon
Reviewed-by: Jonathan Cameron
Signed-off-by: Suzuki K Poulose
---
Changes since V8
Make use of the new generic helper to convert an of_node of a CPU
to the logical CPU id in parsing the topology.
Cc: Catalin Marinas
Cc: Leo Yan
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/topology.c | 16 ++--
1 file changed, 6
Use the new generic helper, of_cpu_node_to_id(), to map a
a phandle to the logical CPU number while parsing the
PMU irq affinity.
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
drivers/perf/arm_pmu_platform.c | 15 +++
1 file changed, 3 insertions
On 20/10/17 13:34, Julien Thierry wrote:
Hi Suzuki,
On 19/10/17 18:15, Suzuki K Poulose wrote:
At the moment we adjust the buffer pointers for reading the trace
data via misc device in the common code for ETF/ETB and ETR. Since
we are going to change how we manage the buffer for ETR, let us
On 30/10/17 21:44, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:39PM +0100, Suzuki K Poulose wrote:
Right now we open code filling the trace buffer with synchronization
packets when the circular buffer wraps around in different drivers.
Move this to a common place.
Cc: Mathieu Poirier
On 31/10/17 22:13, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:40PM +0100, Suzuki K Poulose wrote:
This patch introduces a generic sg table data structure and
associated operations. An SG table can be used to map a set
of Data pages where the trace data could be stored by the TMC
ETR
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4b9e2b276122..4424eb67a54c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -21,6 +21,89 @@
#include "cores
On 20/10/17 18:11, Julien Thierry wrote:
+static int __maybe_unused
+tmc_etr_sg_table_rotate(struct etr_sg_table *etr_table, u64 base_offset)
+{
+ u32 last_entry, first_entry;
+ u64 last_offset;
+ struct tmc_sg_table *sg_table = etr_table->sg_table;
+ sgte_t *table_ptr = sg_table->ta
On 01/11/17 23:47, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:42PM +0100, Suzuki K Poulose wrote:
Make the ETR SG table Circular buffer so that we could start
at any of the SG pages and use the entire buffer for tracing.
This can be achieved by :
1) Keeping an additional LINK pointer
On 12/11/17 17:55, Jerome Glisse wrote:
On Fri, Nov 10, 2017 at 03:11:15PM +, Robin Murphy wrote:
On 09/11/17 22:58, Krishna Reddy wrote:
MAX_PHYSMEM_BITS greater than ARM64_VA_BITS is causing memory
access fault, when HMM_DMIRROR test is enabled.
In the failing case, ARM64_VA_BITS=39 and M
On 13/11/17 12:56, Robin Murphy wrote:
On 13/11/17 10:32, Suzuki K Poulose wrote:
On 12/11/17 17:55, Jerome Glisse wrote:
On Fri, Nov 10, 2017 at 03:11:15PM +, Robin Murphy wrote:
On 09/11/17 22:58, Krishna Reddy wrote:
MAX_PHYSMEM_BITS greater than ARM64_VA_BITS is causing memory
access
On 02/11/17 17:48, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:43PM +0100, Suzuki K Poulose wrote:
At the moment we always use contiguous memory for TMC ETR tracing
when used from sysfs. The size of the buffer is fixed at boot time
and can only be changed by modifiying the DT. With the
On 02/11/17 19:40, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:46PM +0100, Suzuki K Poulose wrote:
Track if the ETR is dma-coherent or not. This will be useful
in deciding if we should use software buffering for perf.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers
On 02/11/17 20:26, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:47PM +0100, Suzuki K Poulose wrote:
Since the ETR could be driven either by SYSFS or by perf, it
becomes complicated how we deal with the buffers used for each
of these modes. The ETR driver cannot simply free the current
On 02/11/17 20:36, Mathieu Poirier wrote:
On Thu, Oct 19, 2017 at 06:15:49PM +0100, Suzuki K Poulose wrote:
We zero out the entire trace buffer used for ETR before it
is enabled, for helping with debugging. Since we could be
restoring a session in perf mode, this could destroy the data.
I&#
When the PMU driver is built as a module, the perf expects the
pmu->module to be valid, so that the driver is prevented from
being unloaded while it is in use. Fix the SPE pmu driver to
fill in this field.
Cc: Will Deacon
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
drivers/p
ll Deacon
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
drivers/bus/arm-ccn.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c
index e8c6946fed9d..3063f5312397 100644
--- a/drivers/bus/arm-ccn.c
+++ b/drivers/bus/arm-ccn.c
@@ -1276,6 +127
On 03/11/17 12:20, Mark Rutland wrote:
Hi Suzuki,
This looks good, but there are a couple of edge cases I think that we
need to handle, as noted below.
On Tue, Oct 31, 2017 at 05:23:18PM +, Suzuki K Poulose wrote:
Changes since V8:
- Fill in the "module" field for the PMU
Export perf_event_update_userpage() so that PMU driver using them,
can be built as modules.
Cc: Peter Zilstra
Signed-off-by: Suzuki K Poulose
---
kernel/events/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 9d93db81fa36
1 - 100 of 2943 matches
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