On 4/2/2013 10:29 AM, Borislav Petkov wrote:
On Tue, Apr 02, 2013 at 05:03:04PM +0200, Joerg Roedel wrote:
On Tue, Apr 02, 2013 at 04:40:37PM +0200, Borislav Petkov wrote:
While you guys are at it, can someone fix this too pls (ASUS board with
a PD on it).
[0.220342] [Firmware Bug]: AMD-Vi
On 10/2/2013 11:15 AM, Oleg Nesterov wrote:
On 10/02,suravee.suthikulpa...@amd.com wrote:
>
>From: Suravee Suthikulpanit
>
>Frederic, this is the rebase of the V4 patch onto the linux-3.12.0-rc3
(linux.git),
>and retest.
But the code is the same? If yes,
Reviewed-by: Oleg
On 9/26/2013 6:06 PM, Andreas Herrmann wrote:
On Fri, Sep 27, 2013 at 12:13:22AM +0200, Borislav Petkov wrote:
On Thu, Sep 26, 2013 at 04:54:32PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
On AMD family15h, applying microcode patch on the a core (core0)
would
On 4/29/2013 7:30 AM, Oleg Nesterov wrote:
On 04/29, Ingo Molnar wrote:
* Oleg Nesterov wrote:
Obviously I can't ack the changes in this area, but to me the whole
series looks fine.
Thanks Oleg - can I add your Reviewed-by tags?
Yes, sure, thanks,
Reviewed-by: Oleg Nesterov
Hi All,
I am
wrote:
> On 16.12.12 10:04:10, Ingo Molnar wrote:
> >
> > * suravee.suthikulpa...@amd.com wrote:
> >
> > > From: Suravee Suthikulpanit
> > >
> > > Currently, the AMD IBS PMU initialize pmu.task_ctx_nr to
> > > perf_invalid_context which only allows IBS to be runnin
On 4/18/2013 1:35 PM, Joerg Roedel wrote:
On Thu, Apr 18, 2013 at 11:59:58AM -0500, Suthikulpanit, Suravee wrote:
One last concern I have for this patch is the case when we re-enable
the interrupt, then another interrupt happens while we processing
the log and set the bit. If the interrupt thre
Ping
On 5/22/2013 2:15 PM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
This patch set implements framework for handling errors reported via IOMMU
event log. It also implements mechanism to filter/suppress error messages when
IOMMU hardware generates large amount event
On 7/3/2013 2:55 AM, Peter Zijlstra wrote:
On Tue, Jul 02, 2013 at 05:50:29PM -0700, Linus Torvalds wrote:
On Mon, Jul 1, 2013 at 2:03 AM, Ingo Molnar wrote:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
perf-core-for-linus
Kernel improvements:
* AMD IOMMU uncore PMU suppo
This is the rework of the original patch set here:
http://lists.linuxfoundation.org/pipermail/iommu/2013-January/005075.html
These patches implement the AMD IOMMU Performance Counter functionality
via custom perf PMU and implement static counting for various IOMMU
translations.
1) Extend the
Udo,
I am trying to debug the issue but need to check one thing on your
system. Would you please try the following and check the output value
on your system?
# setpci -s 00:00.02 F0.w=90
# setpci -s 00:00.02 F4.w
Thank you,
Suravee
On Mon, 2013-01-21 at 10:04 -0600, Jacob Shin wrote:
> On
On 1/23/2013 8:19 AM, Udo van den Heuvel wrote:
On 2013-01-23 00:29, Suravee Suthikulanit wrote:
I sent out a patch
(http://marc.info/?l=linux-kernel&m=135889686523524&w=2) which should
implement
the workaround for AMD processor family15h model 10-1Fh erratum 746 in
the IOMMU driver.
In your cas
On 1/23/2013 8:23 AM, Udo van den Heuvel wrote:
On 2013-01-23 00:29, Suravee Suthikulanit wrote:
message in "dmesg".
"AMD-Vi: Applying erratum 746 for IOMMU at :00:00.2"
This is expected.
Regards,
Suravee
[1.091733] AMD-Vi: Found IOMMU at :00:00.2 cap 0x40
I assume that is c
On 1/23/2013 1:06 AM, Joerg Roedel wrote:
On Tue, Jan 22, 2013 at 05:19:10PM -0600, Suthikulpanit, Suravee wrote:
From: Suravee Suthikulpanit
@@ -1171,6 +1195,8 @@ static int iommu_init_pci(struct amd_iommu *iommu)
for (i = 0; i < 0x83; i++)
io
Hi,
I am following up with this patch. Please let me know if you would like
me to provide any more data or verifications.
Thank you,
Suravee
On Tue, 2012-12-18 at 16:54 -0600, Suravee Suthikulpanit wrote:
> Ingo, Robert
>
> I am including a set of output from "perf report"
Hi,
On 9/19/16 13:11, Colin King wrote:
From: Colin Ian King
vm_data->avic_vm_id is a u32, so the check for a error
return (less than zero) such as -EAGAIN from
avic_get_next_vm_id currently has no effect whatsoever.
Fix this by using a temporary int for the comparison
and assign vm_data->avic
Thanks All. Please let me know if you need anything else from my side.
Suravee
On 9/2/16 21:05, Joerg Roedel wrote:
Hi Paolo,
On Fri, Sep 02, 2016 at 12:46:28PM +0200, Paolo Bonzini wrote:
Joerg, if there's no other issues, could you apply the first 9 patches
to a branch based on 4.8-rc1 or s
Hi Joerg/Radim/Paolo,
Are there any other concerns about this series?
Thanks,
Suravee
On 7/25/16 16:31, Suravee Suthikulpanit wrote:
From: Suravee Suthikulpanit
CHANGES FROM V4
===
* Remove the hash look up in the amd_iommu_update_ga() (see patch 7/12).
Instead, use per
From: Suravee Suthikulpanit
This patch introduces a new IOMMU driver parameter, amd_iommu_guest_ir,
which can be used to specify different interrupt remapping mode for
passthrough devices to VM guest:
* legacy: Legacy interrupt remapping (w/ 32-bit IRTE)
* vapic : Guest vAPIC interrupt
From: Suravee Suthikulpanit
Currently, IOMMU support two interrupt remapping table entry formats,
32-bit (legacy) and 128-bit (GA). The spec also implies that it might
support additional modes/formats in the future.
So, this patch introduces the new struct amd_irte_ops, which allows
the same
From: Suravee Suthikulpanit
Move existing unions and structs for accessing/managing IRTE to a proper
header file. This is mainly to simplify variable declarations in subsequent
patches.
Besides, this patch also introduces new struct irte_ga for the new
128-bit IRTE format.
Signed-off-by
From: Suravee Suthikulpanit
This patch enables support for the new 128-bit IOMMU IRTE format,
which can be used for both legacy and vapic interrupt remapping modes.
It replaces the existing operations on IRTE, which can only support
the older 32-bit IRTE format, with calls to the new struct
From: Suravee Suthikulpanit
Introduce struct iommu_dev_data.use_vapic flag, which IOMMU driver
uses to determine if it should enable vAPIC support, by setting
the ga_mode bit in the device's interrupt remapping table entry.
Currently, it is enabled for all pass-through device if vAPIC mo
From: Suravee Suthikulpanit
This patch implements irq_set_vcpu_affinity() function to set up interrupt
remapping table entry with vapic mode for pass-through devices.
In case requirements for vapic mode are not met, it falls back to set up
the IRTE in legacy mode.
Signed-off-by: Suravee
From: Suravee Suthikulpanit
This patch adds AMD IOMMU guest virtual APIC log (GALOG) handler.
When IOMMU hardware receives an interrupt targeting a blocking vcpu,
it creates an entry in the GALOG, and generates an interrupt to notify
the AMD IOMMU driver.
At this point, the driver processes the
From: Suravee Suthikulpanit
CHANGES FROM V6
===
Per Radim:
* No longer expose struct amd_ir_data to SVM.
* Introduce struct amd_svm_iommu_ir (amd_ir_data wrapper).
* Fix logic to manage ir_list where we need to remove
the posted interrupt from the previous ir_list
From: Suravee Suthikulpanit
This patch adds support to detect and initialize IOMMU Guest vAPIC log
(GALOG). By default, it also enable GALog interrupt to notify IOMMU driver
when GA Log entry is created.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_init.c | 112
From: Suravee Suthikulpanit
Introduces per-VM AVIC ID and helper functions to manage the IDs.
Currently, the ID will be used to implement 32-bit AVIC IOMMU GA tag.
The ID is 24-bit one-based indexing value, and is managed via helper
functions to get the next ID, or to free an ID once a VM is
From: Suravee Suthikulpanit
Introduces a new IOMMU API, amd_iommu_update_ga(), which allows
KVM (SVM) to update existing posted interrupt IOMMU IRTE when
load/unload vcpu.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 39
From: Suravee Suthikulpanit
This patch introduces avic_ga_log_notifier, which will be called
by IOMMU driver whenever it handles the Guest vAPIC (GA) log entry.
Reviewed-by: Radim Krčmář
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/svm.c
From: Suravee Suthikulpanit
This patch implements update_pi_irte function hook to allow SVM
communicate to IOMMU driver regarding how to set up IRTE for handling
posted interrupt.
In case AVIC is enabled, during vcpu_load/unload, SVM needs to update
IOMMU IRTE with appropriate host physical
[RESEND] Not sure if the email went out the first time.
Hi Marc,
On 10/6/15 12:36, Marc Zyngier wrote:
So far, our irq domains are still looked up by device node.
Let's change this and allow a domain to be looked up using
a fwnode_handle pointer.
The existing interfaces are preserved with a co
Hi Rafael,
On 9/9/15 21:48, Suthikulpanit, Suravee wrote:
Hi Rafael,
On 9/10/2015 3:38 AM, Rafael J. Wysocki wrote:
On Wednesday, September 09, 2015 07:16:49 PM Suthikulpanit, Suravee
wrote:
>Hi All,
>
>Are there any other concerns about this patch series?
I have none, but then it sort of mi
Hi
On 10/12/15 15:27, Rafael J. Wysocki wrote:
Just wondering if you are planning to queue this series up for 4.4 as well?
You don't seem to have addressed the Bjorn's comments on patch [2/4].
They need to be addressed before I can take this series.
Thanks,
Rafael
Ah, I missed that one. So
Hi Bjorn,
Thanks for your feedback. And sorry for late response. Some how I didn't
see this earlier. Please see my comments below.
On 09/14/2015 09:34 AM, Bjorn Helgaas wrote:
[..]
So, in order to simplify the function, this patch renames acpi_check_dma()
to acpi_check_dma_coherency() to cle
This patch introduces an interface for irqchip to register a callback,
to provide a way to determine appropriate MSI domain for a pci device.
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/msi.c | 30 ++
include/linux/msi.h | 7 +++
2 files changed, 37
This patch introduces gicv2m_acpi_init(), which uses information
in MADT GIC MSI frames structure to initialize GICv2m driver.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-gic-v2m.c | 106
drivers/irqchip/irq
This patch refactors gicv2m_init_one() to prepare for ACPI support.
It also replaces the irq_domain_add_tree() w/ irq_domain_create_tree()
since we will need to pass the struct fwnode_handle, instead of
struct device_node, when adding ACPI support later.
Signed-off-by: Suravee Suthikulpanit
This patch introduces pci_host_bridge_acpi_msi_domain(), which returns
the MSI domain of the specified PCI host bridge with DOMAIN_BUS_PCI_MSI
bus token. Then, it is assigned to pci device.
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/pci-acpi.c | 13 +
drivers/pci/probe.c
-requsite patches (mainly for ARM64 PCI support for ACPI).
https://github.com/ssuthiku/linux.git irq-domain-fwnode-v2-v2m
This has been tested on AMD Seattle (Overdrive) RevB system.
Suravee Suthikulpanit (4):
pci: msi: Add support to query MSI domain for pci device
acpi: pci: Setup MSI domain for
This patch adds an accessor function to retrieve struct irqchip_fwid.name.
Signed-off-by: Suravee Suthikulpanit
---
include/linux/irqdomain.h | 1 +
kernel/irq/irqdomain.c| 18 ++
2 files changed, 19 insertions(+)
diff --git a/include/linux/irqdomain.h b/include/linux
helps are appreciated.
Thanks,
Suravee
Changes from V1: (https://lkml.org/lkml/2015/10/13/859)
- Rebase on top of Marc's patch to addng support for multiple MSI frames
(https://lkml.org/lkml/2015/10/14/271)
- Adding fwnode convenient functions (patch 3 and 4)
Suravee Suthikulpanit
This patch replaces the struct device_node in v2m_data with
struct fwnode_handle since this structure is common between DT and ACPI.
It also refactors gicv2m_init_one() to prepare for ACPI support.
There should be no functional changes.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip
This patch introduces pci_host_bridge_acpi_msi_domain(), which returns
the MSI domain of the specified PCI host bridge with DOMAIN_BUS_PCI_MSI
bus token. Then, it is assigned to pci device.
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/pci-acpi.c | 13 +
drivers/pci/probe.c
Since there will be several places checking if fwnode.type
is equal FWNODE_IRQCHIP, this patch adds a convenient function
for this purpose.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip/irq-gic.c | 2 +-
include/linux/irqdomain.h | 5 +
kernel/irq/irqdomain.c| 2 +-
3 files
This patch introduces gicv2m_acpi_init(), which uses information
in MADT GIC MSI frames structure to initialize GICv2m driver.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-gic-v2m.c | 94 +
drivers/irqchip/irq
This patch introduces an interface for irqchip to register a callback,
to provide a way to determine appropriate MSI domain for a pci device.
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/msi.c | 30 ++
include/linux/msi.h | 7 +++
2 files changed, 37
This patch adds support for setting up PCI device DMA coherency from
ACPI _CCA object that should normally be specified in the DSDT node
of its PCI host bridge.
Signed-off-by: Suravee Suthikulpanit
CC: Bjorn Helgaas
CC: Catalin Marinas
CC: Rob Herring
CC: Will Deacon
CC: Rafael J. Wysocki
This patch move of_pci_dma_configure() to a more generic
pci_dma_configure(), which can be extended by non-OF code (e.g. ACPI).
This has no functional change.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Rob Herring
CC: Bjorn Helgaas
CC: Catalin Marinas
CC: Will Deacon
CC: Rafael J
A device could have one of the following DMA attributes:
* DMA not supported
* DMA non-coherent
* DMA coherent
So, this patch introduces enum dev_dma_attribute. This will be used by
new APIs introduced in later patches.
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
CC
These DMA APIs are replaced with the newer versions, which return
the enum dev_dma_attr. So, we can safely remove them.
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
---
drivers/base/property.c | 13 -
include/acpi/acpi_bus.h | 34
From: Jeremy Linton
ACPI configurations can now mark devices as noncoherent,
support that choice.
NOTE: This is required to support USB on ARM Juno Development Board.
Signed-off-by: Jeremy Linton
Signed-off-by: Suravee Suthikulpanit
CC: Bjorn Helgaas
CC: Catalin Marinas
CC: Rob Herring
CC
t for _CCA=0
* Clean up acpi_check_dma() per Bjorn suggestions
* Split the original V1 patch into two patches (patch 3 and 4)
Jeremy Linton (1):
Honor ACPI _CCA attribute setting
Suravee Suthikulpanit (7):
device property: Introducing enum dev_dma_attr
acpi: Adding DMA Attribute API
Now that we have the new DMA attribute APIs, we can replace the older
acpi_check_dma() and device_dma_is_coherent().
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
CC: Tom Lendacky
CC: Herbert Xu
CC: David S. Miller
---
drivers/acpi/acpi_platform.c | 7
function, device_dma_supported(),
to check DMA support of the specified device.
Signed-off-by: Suravee Suthikulpanit
CC: Rafael J. Wysocki
---
drivers/base/property.c | 29 +
include/linux/property.h | 4
2 files changed, 33 insertions(+)
diff --git a/drivers/base
, acpi_dma_supported(),
to check DMA support of the specified ACPI device.
Signed-off-by: Suravee Suthikulpanit
Suggested-by: Bjorn Helgaas
CC: Rafael J. Wysocki
---
drivers/acpi/scan.c | 42 ++
include/acpi/acpi_bus.h | 3 +++
include/linux/acpi.h| 10
This patch introduces an interface for irqchip to register a callback,
to provide a way to determine appropriate MSI domain for a pci device.
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/msi.c | 30 ++
include/linux/msi.h | 7 +++
2 files changed, 37
This patch introduces gicv2m_acpi_init(), which uses information
in MADT GIC MSI frames structure to initialize GICv2m driver.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-gic-v2m.c | 95 +
drivers/irqchip/irq
This patch replaces the struct device_node with struct fwnode_handle
since this structure is common between DT and ACPI.
It also refactors gicv2m_init_one() to prepare for ACPI support.
There should be no functional changes.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip/irq-gic
This patch introduces pci_host_bridge_acpi_msi_domain(), which returns
the MSI domain of the specified PCI host bridge with DOMAIN_BUS_PCI_MSI
bus token. Then, it is assigned to pci device.
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/pci-acpi.c | 13 +
drivers/pci/probe.c
Since there will be several places checking if fwnode.type
is equal FWNODE_IRQCHIP, this patch adds a convenient function
for this purpose.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip/irq-gic.c | 2 +-
include/linux/irqdomain.h | 5 +
kernel/irq/irqdomain.c| 2 +-
3 files
ml/2015/10/14/271)
- Adding fwnode convenient functions (patch 3 and 4)
Suravee Suthikulpanit (6):
pci: msi: Add support to query MSI domain for pci device
acpi: pci: Setup MSI domain for ACPI based pci devices
irqdomain: introduce is_fwnode_irqchip helper
irqdomain:
This patch adds an accessor function to retrieve struct irqchip_fwid.name.
Signed-off-by: Suravee Suthikulpanit
---
include/linux/irqdomain.h | 1 +
kernel/irq/irqdomain.c| 18 ++
2 files changed, 19 insertions(+)
diff --git a/include/linux/irqdomain.h b/include/linux
Hi Bjorn/Rafael,
Let me redo the patch with enum then. At least, that's more clear to
everyone.
Thanks,
Suravee
On 10/19/15 21:17, Bjorn Helgaas wrote:
On Tue, Oct 13, 2015 at 06:53:28PM -0500, Suravee Suthikulanit wrote:
Bjorn / Rafael,
On 10/13/2015 10:52 AM, Suravee Suthikul
Currently, the driver only supports lower 32-bit of IOMMU Control register.
However, newer AMD IOMMU specification has extended this register
to 64-bit. Therefore, replace the accessing API with the 64-bit version.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu
Alex/Joerg,
On 1/24/18 5:04 AM, Alex Williamson wrote:
+static size_t try_unmap_unpin_fast(struct vfio_domain *domain, dma_addr_t iova,
+ size_t len, phys_addr_t phys,
+ struct list_head *unmapped_regions)
+{
+ struct vfio_r
Alex / Joerg,
On 1/24/18 5:04 AM, Alex Williamson wrote:
@@ -648,12 +685,40 @@ static int vfio_iommu_type1_unpin_pages(void *iommu_data,
return i > npage ? npage : (i > 0 ? i : -EINVAL);
}
+static size_t try_unmap_unpin_fast(struct vfio_domain *domain, dma_addr_t iova,
+
Hi Joerg,
On 12/27/17 4:20 PM, Suravee Suthikulpanit wrote:
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 73 -
drivers/iommu/amd_iommu_init.c | 7
ned-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu.c | 6 +++---
drivers/iommu/intel-iommu.c | 4 ++--
drivers/iommu/iommu.c | 16
include/linux/iommu.h | 20 ++--
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/driv
Change iommu_unmap[_fast] interfaces return type to ssize_t since
it can also return error code.
Cc: Joerg Roedel
Cc: Alex Williamson
Suravee Suthikulpanit (2):
iommu: Fix iommu_unmap and iommu_unmap_fast return type
vfio/type1: Add iommu_unmap error check when vfio_unmap_unpin
drivers
Besides zero check the number of unmapped page, also check
and handle iommu_unmap errors.
Cc: Alex Williamson
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
drivers/vfio/vfio_iommu_type1.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/vfio
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
Changes from v2 (https://lkml.org/lkml/2017/12/27/44)
* Call domain_flush_complete() after domain_flush_tlb_pde().
drivers/iommu/amd_iommu.c | 77
Williamson
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
Changes from v3 (https://lkml.org/lkml/2018/1/21/244)
* Refactor the code to unmap_unpin_fast() and unmap_unpin_slow()
to improve code readability.
* Fix logic in vfio_unmap_unpin() to fallback to unmap_unpin_slow()
only for the
Hi Robin,
On 2/1/18 1:02 AM, Robin Murphy wrote:
Hi Suravee,
On 31/01/18 01:48, Suravee Suthikulpanit wrote:
Currently, iommu_unmap and iommu_unmap_fast return unmapped
pages with size_t. However, the actual value returned could
be error codes (< 0), which can be misinterpreted as la
Alex,
On 1/31/18 4:45 PM, Suravee Suthikulpanit wrote:
Currently, VFIO IOMMU type1 unmaps IOVA pages synchronously, which requires
IOTLB flush for every IOVA unmap. This results in a large number of IOTLB
flushes during initialization of pass-through devices.
This can be avoided using the
: Alex Williamson
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
Changes from v4 (https://lkml.org/lkml/2018/1/31/153)
* Change return type from ssize_t back to size_t since we no longer
changing IOMMU API. Also update error handling logic accordingly.
* In unmap_unpin_fast(), also
Hi Joerg,
Do you have any feedback regarding this patch for AMD IOMMU? I'm re-sending the
patch 1/2
separately per Alex's suggestion.
Thanks,
Suravee
On 12/27/17 4:20 PM, Suravee Suthikulpanit wrote:
Implement the newly added IOTLB flushing interface for AMD IOMMU.
Signed-off-b
AMD IOMMU with certain dGPUs.
This can be avoided by using the new IOTLB flushing interface.
Cc: Alex Williamson
Cc: Joerg Roedel
Signed-off-by: Suravee Suthikulpanit
---
Changes from V2: (https://lkml.org/lkml/2017/12/27/43)
* In vfio_unmap_unpin(), fallback to use slow IOTLB flush
when
Hi Alex,
On 1/9/18 4:07 AM, Alex Williamson wrote:
@@ -661,6 +705,8 @@ static long vfio_unmap_unpin(struct vfio_iommu *iommu,
struct vfio_dma *dma,
if (!IS_IOMMU_CAP_DOMAIN_IN_CONTAINER(iommu))
return 0;
+ INIT_LIST_HEAD(&unmapped_regions);
+
/*
* We
Hi Alex,
On 1/9/18 3:53 AM, Alex Williamson wrote:
On Wed, 27 Dec 2017 04:20:34 -0500
Suravee Suthikulpanit wrote:
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index e30e29a..f000844 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio
.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/cacheinfo.h | 7 +++
arch/x86/kernel/cpu/amd.c| 19 +++
arch/x86/kernel/cpu/cacheinfo.c | 37 +
3 files changed, 47 insertions(+), 16 deletions(-)
create mode 100644
/AMD: Remove unnecessary check for CONFIG_SMP
x86/CPU: Rename intel_cacheinfo.c to cacheinfo.c
Suravee Suthikulpanit (2):
perf/x86/amd/uncore: Fix amd_uncore_llc ID to use pre-defined
cpu_llc_id
x86/CPU/AMD: Calculate LLC ID from number of sharing threads
arch/x86/events/amd/uncore.c
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/uncore.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index f5cbbba..981ba5e 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch
From: Borislav Petkov
Move smp_num_siblings and cpu_llc_id to cpu/common.c so that they're
always present as symbols and not only in the CONFIG_SMP case. Then,
other code using them doesn't need ugly ifdeffery anymore.
Signed-off-by: Borislav Petkov
Signed-off-by: Suravee Sut
From: Borislav Petkov
Since this file contains general cache-related information for x86,
rename the file to a more appropriate name.
Signed-off-by: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kernel/cpu/Makefile | 2 +-
arch/x86/kernel/cpu
Linux currently provides function detect_extended_topology()
for parsing CPUID Fn0xB and derive CPU topology information.
Therefore, also call this function in AMD code path.
Thanks,
Suravee
Suravee Suthikulpanit (2):
x86/CPU: Modify detect_extended_topology() to return result
x86/CPU/AMD
Current implementation does not communicate whether it can successfully
detect CPUID Fn0x000B information. Therefore, modify the function
to return success or error codes. This will be used by subsequent patches.
Reviewed-by: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch
Derive topology information from Extended Topology Enumeration
(CPUID Fn0x000B) when the information is available.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kernel/cpu/amd.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu
Hi All,
On 3/27/18 1:52 PM, David Rientjes wrote:
On Tue, 27 Mar 2018, Ingo Molnar wrote:
Linux currently provides function detect_extended_topology()
for parsing CPUID Fn0xB and derive CPU topology information.
Therefore, also call this function in AMD code path.
Thanks,
Suravee
Suravee
Hi All,
On 3/26/18 3:05 PM, Suravee Suthikulpanit wrote:
Derive topology information from Extended Topology Enumeration
(CPUID Fn0x000B) when the information is available.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kernel/cpu/amd.c | 16
1 file changed, 12
ned-off-by: Suravee Suthikulpanit
---
arch/x86/kernel/cpu/cacheinfo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 38354c6..0c5fcbd 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/c
helping to test, investigate, provide data
and report issues on several platforms in the field.
Regards,
Suravee
Paul Menzel (1):
Revert "iommu/amd: Fix performance counter initialization"
Suravee Suthikulpanit (1):
iommu/amd: Remove performance counter pre-initialization test
drivers
://lore.kernel.org/linux-iommu/alpine.lnx.3.20.13.2006030935570.3...@monopod.intra.ispras.ru/
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201753
Cc: Tj (Elloe Linux)
Cc: Shuah Khan
Cc: Alexander Monakov
Cc: David Coe
Signed-off-by: Paul Menzel
Signed-off-by: Suravee Suthikulpanit
---
Note
kernel.org/show_bug.cgi?id=201753
Cc: Tj (Elloe Linux)
Cc: Shuah Khan
Cc: Alexander Monakov
Cc: David Coe
Cc: Paul Menzel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/iommu/am
specifies PCI-defined class code (i.e. base-class, subclass and
programming interface).
This patch adds support for matching ACPI devices using the _CLS method.
Signed-off-by: Suravee Suthikulpanit
---
drivers/acpi/scan.c | 79 +++--
include/acpi
logic to retrieve and evaluate _CLS handle. (per Hanjun)
Suravee Suthikulpanit (2):
ACPI / scan: Add support for ACPI _CLS device matching
ata: ahci_platform: Add ACPI _CLS matching
drivers/acpi/scan.c | 79 +++--
drivers/ata/Kconfig
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 387 }
})
}
Also, since ATA driver should not require PCI support for ATA_ACPI,
this patch removes dependency in the driver/ata/Kconfig.
Acked-by: Tejun Heo
Signed-off-by: Suravee Suthikulpanit
---
drivers/ata/Kconfig
Hi,
I am not sure if this thread is still alive. I'm trying to see what I
can do to help clean up/convert to make the PCI GHC also works for arm64
w/ zero or minimal ifdefs.
Please let me know if someone is already working on this. I noticed that
Lorenzo's patches has already been in 3.19-rc
On 1/16/15 09:17, Al Stone wrote:
On 01/16/2015 03:20 AM, Catalin Marinas wrote:
On Thu, Jan 15, 2015 at 09:31:53PM +, Al Stone wrote:
On 01/15/2015 11:23 AM, Catalin Marinas wrote:
On Thu, Jan 15, 2015 at 04:26:20PM +, Grant Likely wrote:
On Wed, Jan 14, 2015 at 3:04 PM, Hanjun Guo
On 3/8/15 21:34, Yijing Wang wrote:
This patch separate pci_host_bridge creation out
of pci_create_root_bus(), and try to make a generic
pci_host_bridge, then we could place generic PCI
infos like domain number in it. Also Ripping out
pci_host_bridge creation from pci_create_root_bus()
make cod
ACPI Device configuration often contain _CLS object to suppy PCI-defined
class code for the device. This patch introduces logic to process the _CLS
object.
Acked-by: Mika Westerberg
Reviewed-by: Hanjun Guo
Signed-off-by: Suravee Suthikulpanit
---
drivers/acpi/acpica/acutils.h | 3
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