Quoting Nicholas Mc Guire (2018-07-13 09:40:04)
> of_find_compatible_node() is returning a device node with refcount
> incremented and must be explicitly decremented after the last use
> which is right after the us in of_iomap() here.
>
> Signed-off-by: Nicholas Mc Guire
> Fixes: commit 4a5f720b6
Quoting Nicholas Mc Guire (2018-07-13 09:40:04)
> of_find_compatible_node() is returning a device node with refcount
> incremented and must be explicitly decremented after the last use
> which is right after the us in of_iomap() here.
>
> Signed-off-by: Nicholas Mc Guire
> Fixes: commit 4a5f720b6
Quoting Nicholas Mc Guire (2018-07-15 03:18:24)
> Refactoring of code to make it more readable and at the same time make
> sparse happy again.
>
> Signed-off-by: Nicholas Mc Guire
> ---
>
> sparse complained about:
> drivers/clk/st/clkgen-pll.c:225:12: warning: context imbalance in
> 'clkgen_p
Quoting Nicholas Mc Guire (2018-07-15 03:18:23)
> While the return value of clkgen_get_register_base() is being checked
> at the call site, there is no indication of failure cause thus making
> diagnosis of the issues hard. The WARN_ON() allows to determine the
> cause of failure.
>
> Signed-off-
Quoting Aapo Vienamo (2018-07-12 04:52:59)
> Add the missing linux/delay.h include statement for udelay() used by
> fence_udelay() macro.
>
> Signed-off-by: Aapo Vienamo
> Acked-by: Peter De Schrijver
> Acked-by: Jon Hunter
> ---
Applied to clk-next
Quoting Aapo Vienamo (2018-07-12 04:53:00)
> From: Peter De Schrijver
>
> Move this to a separate file so it can be used to calculate the sdmmc
> clock dividers.
>
> Signed-off-by: Peter De-Schrijver
> Signed-off-by: Aapo Vienamo
> Acked-by: Peter De Schrijver
> Acked-by: Jon Hunter
> ---
A
Quoting Aapo Vienamo (2018-07-12 04:53:01)
> From: Peter De-Schrijver
>
> Add a clock type to model the sdmmc switch divider clocks which have paths
> to source clocks bypassing the divider (Low Jitter paths). These
> are handled by selecting the lj path when the divider is 1 (ie the
> rate is th
Quoting Aapo Vienamo (2018-07-12 04:53:02)
> From: Peter De-Schrijver
>
> These clocks have low jitter paths to certain parents. To model these
> correctly, use the sdmmc mux divider clock type.
>
> Signed-off-by: Peter De-Schrijver
> Signed-off-by: Aapo Vienamo
> Acked-by: Peter De Schrijver
it will need to remux the
pin as a GPIO function input pin, enable the irq, and wait for wakeup.
On resume, it will disable the irq and remux the pin as "UART" mode.
Changes from v1:
* Squashed the raw status bit part into the same write in unmask path
based on suggestion from Doug
but
let's explicitly configure this in the code so that DT implementers
don't have to get this part right.
Cc: Bjorn Andersson
Cc: Doug Anderson
Signed-off-by: Stephen Boyd
---
Changes from v1:
* None
drivers/pinctrl/qcom/pinctrl-msm.c | 37 ++
1 file ch
pio is use from gpiolib.
Cc: Bjorn Andersson
Cc: Doug Anderson
Signed-off-by: Stephen Boyd
---
Changes from v1:
* None
drivers/pinctrl/qcom/pinctrl-msm.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-m
bit for level type
interrupts so that the hardware stops latching the status of the
interrupt after we ack it. We don't do this for edge type interrupts
because it seems that toggling the raw status enable bit for edge type
interrupts causes spurious edge interrupts.
Cc: Bjorn Andersson
Quoting Phil Edworthy (2018-07-18 06:56:26)
> Hi Russell,
>
> On 18 July 2018 14:19, Geert Uytterhoeven wrote:
> > On Wed, Jul 18, 2018 at 3:02 PM Russell King - ARM Linux wrote:
> > > On Wed, Jul 18, 2018 at 01:57:38PM +0100, Phil Edworthy wrote:
> > > > Behaves the same as (devm_)clk_get except
Quoting Masahiro Yamada (2018-07-20 01:37:35)
> The Denali NAND controller IP needs three clocks:
>
> - clk: controller core clock
>
> - clk_x: bus interface clock
>
> - ecc_clk: clock at which ECC circuitry is run
>
> Currently, only the first one (50MHz) is provided. The rest of the
> two
Quoting Masahiro Yamada (2018-07-20 01:37:36)
> Add USB3 PHY clocks where missing. Use fixed-factor clocks for those
> without gating.
>
> For clarification, prefix clock names with 'ss' or 'hs'.
>
> Signed-off-by: Masahiro Yamada
> ---
Applied to clk-next
Quoting Marcel Ziswiler (2018-07-20 00:54:22)
> From: Marcel Ziswiler
>
> Actually report the error code from devm_regulator_get() which may as
> well just be a probe deferral.
>
> Signed-off-by: Marcel Ziswiler
>
> ---
>
> drivers/clk/tegra/clk-dfll.c | 5 +++--
> 1 file changed, 3 insertio
Quoting Keiji Hayashibara (2018-07-18 22:23:48)
> From: Kunihiko Hayashi
>
> Add clock control for SPI controller on UniPhier SoCs.
>
> Signed-off-by: Kunihiko Hayashi
> Signed-off-by: Masahiro Yamada
> ---
Signed-off-by chain is a little weird, but I'll go with it.
Applied to clk-next
Quoting Saravanan Sekar (2018-07-19 02:06:45)
> Add REGMAP_MMIO as dependency to avoid undefined
> reference to regmap symbols.
>
> Fixes: d85d20053e19 ("clk: actions: Add S900 SoC clock support")
> Signed-off-by: Saravanan Sekar
> Reviewed-by: Andreas Färber
> Reviewed-by: Manivannan Sadhasivam
Quoting Saravanan Sekar (2018-07-19 02:06:46)
> Add clock bindings constants for action S700
> Maintain common clock dt-bindings for Actions Semi SoC's
> S700 and S900.
>
> Signed-off-by: Parthiban Nallathambi
> Signed-off-by: Saravanan Sekar
> Reviewed-by: Rob Herring
> ---
Applied to clk-nex
Quoting Saravanan Sekar (2018-07-19 02:06:47)
> Add Actions Semi S700 SoC clock support
>
> Signed-off-by: Parthiban Nallathambi
> Signed-off-by: Saravanan Sekar
> Reviewed-by: Manivannan Sadhasivam
> ---
Applied to clk-next
by 4 clock node in
> the SDHost clock path.
>
> This will ensure the right clock frequency is selected when
> the mmc driver tries to configure frequency on card insert.
>
> Signed-off-by: Govindraj Raja
> Signed-off-by: Andreas Färber
> ---
Acked-by: Stephen Boyd
Quoting Gustavo A. R. Silva (2018-07-18 18:58:45)
> There is a potential execution path in which function
> platform_get_resource() returns NULL. If this happens,
> we will end up having a NULL pointer dereference.
>
> Fix this by adding asanity check in order to avoid a
> NULL pointer dereference
ies.
>
> Cc:
> Fixes: 53c31b3437a6 ("mfd: sec-core: Add of_compatible strings for clock MFD
> cells")
> Signed-off-by: Krzysztof Kozlowski
> ---
Acked-by: Stephen Boyd
Quoting Shawn Guo (2018-07-11 01:43:03)
> On Fri, Jul 06, 2018 at 01:58:46PM -0700, Stephen Boyd wrote:
> > Quoting Anson Huang (2018-06-21 23:32:33)
> > > According to Reference Manual Rev.0, 06/2017,
> > > there are GPIO LPCGs defined in CCM CCGRs,
>
Quoting Joel Stanley (2018-07-10 22:53:52)
> Hi Stephen,
>
> On 7 July 2018 at 03:55, Stephen Boyd wrote:
> > Quoting Joel Stanley (2018-06-28 16:15:40)
> >> The HPLL can be configured through a register (SCU24), however some
> >> platforms chose to configure
Quoting Taniya Das (2018-07-12 10:21:33)
> ++ Display driver team,
>
> On 7/9/2018 8:36 PM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-07-09 02:34:07)
> >>
> >>
> >> On 7/9/2018 1:07 PM, Stephen Boyd wrote:
> >>> Quoting Taniya Das (20
Quoting Taniya Das (2018-07-12 11:05:45)
> The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
> for changing the frequency of CPUs. The driver implements the cpufreq
> driver interface for this hardware engine.
>
> Signed-off-by: Saravana Kannan
> Signed-off-by: Taniya Das
Quoting Taniya Das (2018-07-12 11:05:44)
[..]
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + next-level-cache = <&L2_600>;
> + qcom,freq-domain = <&
Quoting Matthias Kaehlcke (2018-07-09 14:25:21)
> diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi
> b/arch/arm64/boot/dts/qcom/pm8998.dtsi
> index 92bed1e7d4bb..7eea94701b23 100644
> --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
> @@ -11,6 +11,13 @@
>
Quoting Nicholas Mc Guire (2018-07-13 04:13:20)
> of_find_compatible_node() is returning a device node with refcount
> incremented and must be explicitly decremented after the last use
> which is right after the us in of_iomap() here.
>
> Signed-off-by: Nicholas Mc Guire
> Fixes: commit 787b4271a
On 01/22, Timur Tabi wrote:
> On 1/9/18 7:58 PM, Stephen Boyd wrote:
> >+ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp,
> >+ len);
> >+if (ret < 0) {
> >+
them so
that the v2m code works mostly unmodified.
Cc:
Acked-by: Rob Herring
Tested-by: Srinivas Kandagatla
Cc: Marc Zyngier
Signed-off-by: Stephen Boyd
---
Picked up acks/tested-by.
.../bindings/interrupt-controller/arm,gic-v3.txt | 48 +-
drivers/irqchip/irq-gic-v2m.c
OSes are able to know what
pins to avoid reading/writing.
For now, we plumb this into the gpiochip irq APIs so that
GPIO/pinctrl drivers can use the gpiochip_irqchip_irq_valid() to
test validity of GPIOs.
Signed-off-by: Stephen Boyd
---
Or this can move into a dedicated API and not be tied to the
able to know what
pins to avoid reading/writing.
Cc: Grant Likely
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/gpio/gpio.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt
b/Documentation
available pins and set
the irq valid bits for gpiolib to know what to consider 'valid'.
This should avoid any issues with gpiolib. Furthermore, implement
the pinmux_ops::request function so that pinmux can also make
sure to not use pins that are unavailable.
Signed-off-by: St
don't blow up easily.
Changes from v1:
* Pushed into gpiolib-of core under irq valid line logic
* Fixed up qcom driver patch to free stuff properly and remove custom code
* Dropped export patch as it got picked up
* Renamed binding to 'reserved-gpio-ranges'
Stephen Boyd (3):
dt
On 01/10, Linus Walleij wrote:
> On Wed, Jan 10, 2018 at 2:58 AM, Stephen Boyd wrote:
>
> > +- ngpios-ranges:
> > + Usage: optional
> > + Value type:
> > + Definition: Tuples of GPIO ranges (base, size) indicating
> > +
On 01/03, Geert Uytterhoeven wrote:
> The "flags" parameter passed to of_clk_detect_critical() cannot be a
> pointer to a real clk_core.flags field, as clk_core is private to the
> clock framework internals.
>
> Change the comment to refer to top-level framework flags instead.
>
> Signed-off-by:
On 01/03, Geert Uytterhoeven wrote:
> Currently the virtual "clk_flags" file in debugfs shows the numeric
> value of the top-level framework flags for the specified clock.
> Hence the user must manually interpret these values.
>
> Moreover, on big-endian 64-bit systems, the wrong half of the value
On 01/03, Geert Uytterhoeven wrote:
> Octal permissions are preferred, as they are easier to read than
> symbolic permissions. Hence replace "S_IRUGO" by "0444".
>
> Signed-off-by: Geert Uytterhoeven
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Foru
On 01/03, Geert Uytterhoeven wrote:
> When exposing data access through debugfs, the correct
> debugfs_create_*() functions must be used, matching the data types.
>
> Remove all casts from data pointers passed to debugfs_create_*()
> functions, as such casts prevent the compiler from flagging bugs
On 01/02, Stephen Boyd wrote:
> Now that all the users of asm/clkdev.h have been replaced with
> the generic file we can get rid of the asm-generic file as well
> and implement that code directly where it's used.
>
> We only have one caller of __clkdev_alloc(), in clkdev.
On 01/02, Stephen Boyd wrote:
> The generic header file is equivalent to the blackfin version, so
> just use the generic one.
>
> Signed-off-by: Stephen Boyd
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundatio
On 01/02, Stephen Boyd wrote:
> We can move these APIs into the private header file now that we
> don't have any users of the __clk_get() and __clk_put() APIs
> outside of clkdev.c and clk.c.
>
> Cc: Russell King
> Signed-off-by: Stephen Boyd
> ---
Applied to clk-nex
On 01/02, Stephen Boyd wrote:
> Now that every architecture is using the generic clkdev.h file
> and we no longer include asm/clkdev.h anywhere in the tree, we
> can remove it.
>
> Cc: Russell King
> Cc: Arnd Bergmann
> Cc:
> Signed-off-by: Stephen Boyd
&g
On 01/02, Stephen Boyd wrote:
> We'd like to privatize __clk_get(), but the sunxi clk driver is
> calling this function to keep a reference held on the clk and
> call clk_prepare_enable() on it. We support this design in the
> clk core now with the CLK_IS_CRITICAL flag, so let&
g. We also make sure to set
> flags in this case so that we are not returning an uninitialized value.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: David Lechner
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 01/05, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Changes from v1->v2:
> Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable
> reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should
> be quite reasonable because the reset controller is tightly embedded
>
On 01/06, David Lechner wrote:
> clk_round_rate() 'answers the question "if I were to pass @rate to
> clk_set_rate(), what clock rate would I end up with?" without changing
> the hardware'.
>
> Currently, clk_divider_round_rate() returns the "current value" when
> divider->flags & CLK_DIVIDER_READ
On 01/12, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> STM32F769 has 2 SDMMC port, add clock entry for the second one.
>
> Signed-off-by: Alexandre TORGUE
> Signed-off-by: Patrice Chotard
> ---
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc
On 01/10, Viresh Kumar wrote:
> On 09-01-18, 18:54, Stephen Boyd wrote:
> > My read of Kevin's comments lead me to think he's saying that a
> > generic 'domain-performance-state' property is worse than putting
> > the numbers directly inside of the opp tabl
On 01/29, Rajendra Nayak wrote:
>
>
> On 01/27/2018 03:45 AM, Stephen Boyd wrote:
> > On 01/25, Rajendra Nayak wrote:
> >> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> >> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
> >
arguments through any number of nexus nodes and end up with the
actual gpio provider being used.
Cc: Pantelis Antoniou
Acked-by: Linus Walleij
Cc: Mark Brown
Signed-off-by: Stephen Boyd
---
drivers/gpio/gpiolib-of.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dr
reset-gpios' from <&connector 2 GPIO_ACTIVE_LOW>
to <&soc_gpio1 3 GPIO_ACTIVE_LOW>.
Cc: Pantelis Antoniou
Cc: Linus Walleij
Cc: Mark Brown
Signed-off-by: Stephen Boyd
---
drivers/of/base.c | 184 +
include/linux/of.h |
difference between this
API and of_parse_phandle_with_args()
Stephen Boyd (3):
Document nexus nodes/specifier remapping
of: Support parsing phandle argument lists through a nexus node
of: unittest: Add phandle remapping test
gpio: Support gpio nexus dt bindings
Kernel:
drivers/gpio/gpiolib-of.c
Test the functionality of of_parse_phandle_with_args_map().
Cc: Pantelis Antoniou
Cc: Linus Walleij
Cc: Mark Brown
Signed-off-by: Stephen Boyd
---
drivers/of/unittest-data/tests-phandle.dtsi | 25 ++
drivers/of/unittest.c | 120
2 files
On 02/01, Marc Zyngier wrote:
> On 29/01/18 16:49, Stephen Boyd wrote:
> > @@ -1815,6 +1815,8 @@ static int __init its_of_probe(struct device_node
> > *node)
> >
> > for (np = of_find_matching_node(node, its_device_id); np;
> > np = of_fin
t are marked as "disabled" in DT so
that we can describe the hardware that exists and use the status
property to indicate how the firmware has configured things.
Cc: Stuart Yoder
Cc: Laurentiu Tudor
Cc: Greg Kroah-Hartman
Cc: Marc Zyngier
Cc: Rajendra Nayak
Signed-off-by: Stephen Boyd
On 01/29, Jerome Brunet wrote:
> On Thu, 2017-12-21 at 18:15 -0800, Stephen Boyd wrote:
> > On 12/19, Michael Turquette wrote:
> > > Quoting Jerome Brunet (2017-12-01 13:51:50)
> > > > This Patchset is related the RFC [0] and the discussion around
> > >
fore enabling the outputs
clk: si5351: Rename internal plls to avoid name collisions
clk: si5351: Do not enable parent clocks on probe
Srinivas Kandagatla (3):
clk: qcom: msm8916: Fix i2s clk rates required for mclk
clk: qcom: msm8916: fix mnd_width for codec_di
On 12/29, Viresh Kumar wrote:
> On 28-12-17, 16:32, Stephen Boyd wrote:
> > On 12/28, Viresh Kumar wrote:
>
> > > So what we need now is:
> > >
> > > - Stephen to start responding and clarify all the doubts he had as being
> > > silent
>
On 01/25, Rajendra Nayak wrote:
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
Do we really need two files? Maybe collapse the two?
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
> diff --git a/arch/arm64/bo
On 01/25, Rajendra Nayak wrote:
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi
> new file mode 100644
> index ..b97f99e6f4b4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi
> @@ -0,0 +1,32 @@
> +// SPDX-License-I
On 01/22, Amit Nischal wrote:
> Add support for the global clock controller found on SDM845
> based devices. This should allow most non-multimedia device
> drivers to probe and control their clocks.
>
> Signed-off-by: Taniya Das
Is Taniya the author? Should be a From: line then.
> Signed-off-by
On 01/12, Benjamin Herrenschmidt wrote:
> The USB port 1 clock gate control has an inversed polarity
> from all the other clock gates in the chip. This makes the
> aspeed_clk_{enable,disable} functions honor the flag
> CLK_GATE_SET_TO_DISABLE and set that flag appropriately
> so it's set for all cl
re
> related to clocks control. It provides one clock per TCU channel (plus
> one for the watchdog and one for the OS timer) that can be used by other
> drivers.
>
> Signed-off-by: Paul Cercueil
> ---
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code
t are marked as "disabled" in DT so
that we can describe the hardware that exists and use the status
property to indicate how the firmware has configured things.
Cc: Marc Zyngier
Cc: Rajendra Nayak
Signed-off-by: Stephen Boyd
---
drivers/irqchip/irq-gic-v3-its-pci-msi.c | 2 ++
drive
On 01/28/2018 05:56 AM, Joe Perches wrote:
> commit 321737416c72d ("tty: serial: msm: Move header file into driver")
> removed the .h file, update the patterns.
>
> Signed-off-by: Joe Perches
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a member of Code
Replace my codeaurora.org address with my kernel.org address so
that emails don't bounce.
Signed-off-by: Stephen Boyd
---
MAINTAINERS | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c90687ec8fc6..35b26c121bc2 100644
--- a/MAINTA
On 12/14, Will Deacon wrote:
> On Wed, Dec 13, 2017 at 02:19:37PM -0800, Stephen Boyd wrote:
> > The Kryo CPUs are also affected by the Falkor 1003 errata, so
> > we need to do the same workaround on Kryo CPUs. The MIDR is
> > slightly more complicated here, where the PART num
Some pinctrl drivers can use the gpiochip irq valid information
to figure out if certain gpios are exposed to the kernel for
usage or not. Expose this API so we can use it in the
pinmux_ops::request ops.
Signed-off-by: Stephen Boyd
---
drivers/gpio/gpiolib.c | 5 +++--
include/linux/gpio
don't blow up easily.
Stephen Boyd (3):
gpiolib: Export gpiochip_irqchip_irq_valid() to drivers
dt-bindings: pinctrl: Add a ngpios-ranges property
pinctrl: qcom: Don't allow protected pins to be requested
.../bindings/pinctrl/qcom,msm8996-pinctrl.txt | 6 ++
dr
available pins and set
the irq valid bits for gpiolib to know what to consider 'valid'.
This should avoid any issues with gpiolib. Furthermore, implement
the pinmux_ops::request function so that pinmux can also make
sure to not use pins that are unavailable.
Signed-off-by: St
able to know what
pins to avoid reading/writing.
Cc:
Signed-off-by: Stephen Boyd
---
I stuck this inside msm8996, but maybe it can go somewhere more generic?
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a
On 01/03, Geert Uytterhoeven wrote:
> Currently the virtual "clk_flags" file in debugfs shows the numeric
> value of the top-level framework flags for the specified clock.
> Hence the user must manually interpret these values.
>
> Moreover, on big-endian 64-bit systems, the wrong half of the value
On 01/08, Viresh Kumar wrote:
> On 05-01-18, 14:19, Stephen Boyd wrote:
> > On 12/29, Viresh Kumar wrote:
>
> > Could you please point to Kevin's comments and also include the
>
> https://lkml.kernel.org/r/m2r30i4w35@baylibre.com
Ok. That thread was months ago.
On Fri, Mar 9, 2018 at 1:33 PM, Lina Iyer wrote:
> Hi Stephen,
>
> I will address all the comments in the next spin of the patch. Here are
> some responses to the questions.
>
> On Tue, Mar 06 2018 at 12:45 -0700, Stephen Boyd wrote:
>>
>> Quoting
Quoting Eddie James (2018-03-08 12:57:18)
> Here are two fixes for the Aspeed clock driver. The first fixes the is_enabled
> clock function to account for different clock gates getting disabled with
> either 0s or 1s. The second patch addresses some issue found with the LPC
> controller clock if it
On Mon, Mar 12, 2018 at 7:12 AM, Rajendra Nayak wrote:
> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Doug Anderson
Reviewed-by: Stephen Boyd
Quoting Thierry Reding (2018-03-12 00:04:30)
> On Fri, Mar 09, 2018 at 09:33:06AM -0800, Stephen Boyd wrote:
> >
> > Are you going to send us a PR at some point?
>
> Yes, I was going to let the patches cook a little in linux-next and send
> a PR by the end of the we
Quoting Lina Iyer (2018-02-26 09:58:01)
> diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c
> new file mode 100644
> index ..0792a2a98fc9
> --- /dev/null
> +++ b/drivers/soc/qcom/cmd-db.c
> @@ -0,0 +1,319 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright (c)
Quoting Lina Iyer (2018-02-26 09:58:02)
> diff --git a/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
> b/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
> new file mode 100644
> index ..5737ed2ac6e8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/cmd-db.tx
Quoting Lina Iyer (2018-03-02 08:43:08)
> Add controller driver for QCOM SoCs that have hardware based shared
> resource management. The hardware IP known as RSC (Resource State
> Coordinator) houses multiple Direct Resource Voter (DRV) for different
> execution levels. A DRV is a unique voter on t
Quoting Lina Iyer (2018-03-06 08:21:40)
> On Mon, Mar 05 2018 at 11:42 -0700, Stephen Boyd wrote:
> >Quoting Lina Iyer (2018-02-26 09:58:01)
>
> >> +}
> >> +EXPORT_SYMBOL(cmd_db_ready);
> >> +
> >> +static u64 cmd_db_get_u64_id(const char *id)
>
Quoting Lina Iyer (2018-03-06 08:56:19)
> On Tue, Mar 06 2018 at 09:21 -0700, Lina Iyer wrote:
> >On Mon, Mar 05 2018 at 11:42 -0700, Stephen Boyd wrote:
> >>Quoting Lina Iyer (2018-02-26 09:58:01)
> >>>+size_t cmd_db_read_aux_data_len(const char *id
Quoting Lina Iyer (2018-03-02 08:43:09)
> Add device binding documentation for Qualcomm Technology Inc's RPMH RSC
> driver. The hardware block is used for communicating resource state
s/driver/hardware/
> requests for shared resources.
>
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Lina Iye
Quoting tali.per...@gmail.com (2018-03-20 06:40:49)
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 71ec41e6364f..353e94f2c25a 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -21,6 +21,7 @@ endif
> obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
>
Quoting Kunihiko Hayashi (2018-03-30 02:44:14)
> Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
> and these are mandatory to activate the ethernet controller. This adds
> support for the clock lines.
>
> Signed-off-by: Kunihiko Hayashi
> ---
Applied to clk-next
Quoting Kunihiko Hayashi (2018-03-30 02:44:13)
> Add clock control for SATA controller on UniPhier SoCs. This adds
> support for PXs2, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi
> ---
Applied to clk-next
Quoting Kunihiko Hayashi (2018-03-30 02:44:12)
> Add clock control for PCIe controller on UniPhier SoCs. This adds
> support for Pro5, LD20 and PXs3.
>
> Signed-off-by: Kunihiko Hayashi
> ---
Applied to clk-next
Quoting Amit Nischal (2018-04-03 05:24:41)
> On 2018-03-20 06:12, Stephen Boyd wrote:
> > Quoting Amit Nischal (2018-03-07 23:18:15)
> >> +};
> >> +
> >> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
> >> + .cmd_rcgr = 0x1600c,
> >&g
Quoting Taniya Das (2018-04-02 03:33:26)
>
> >
> >> +
> >> +#include "common.h"
> >> +#include "clk-regmap.h"
> >> +
> >> +#define CLK_RPMH_ARC_EN_OFFSET 0
> >> +#define CLK_RPMH_VRM_EN_OFFSET 4
> >> +#define CLK_RPMH_VRM_OFF_VAL 0
> >> +#define CLK_RPMH_VRM_ON_VAL 1
> >> +#define CLK_RPMH_APPS_R
Quoting Taniya Das (2018-03-28 23:17:53)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh.txt
> b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt
> new file mode 100644
> index 000..8222c88
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt
Can
Quoting Taniya Das (2018-04-02 03:45:44)
> From: Amit Nischal
>
> For some gdscs, it might take longer time up to 500us for
> updating their status. So add support for the same by
> defining a new flag 'GDS_TIMEOUT' to mark such gdsc in
> order to poll their status for longer timeout value.
>
>
Quoting Taniya Das (2018-04-02 03:45:45)
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index e89584e..e0c83ba 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -83,6 +88,38 @@ static int gdsc_poll_status(struct gdsc *sc, unsigned int
> reg, bool en)
>
Quoting Sekhar Nori (2018-04-06 02:37:03)
>
> Can you please check that and confirm there is no issue with genpd and
> using CLK_OF_DECLARE() to initialize clocks?
>
> Unless you report an issue back, or Mike and Stephen have ideas about
> how to handle the dependency between PSC/PLL derived ti
Quoting Abel Vesa (2018-03-27 23:46:35)
> From: Peter Chen
>
> Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
> which is the output of USBOTG2 PHY.
>
> Signed-off-by: Peter Chen
> Signed-off-by: Irina Tirdea
> Signed-off-by: Abel Vesa
> ---
Applied to clk-next
Quoting Abel Vesa (2018-03-27 23:46:37)
> From: Anson Huang
>
> DRAM PLL is a audio/video type PLL, need to correct
> it to get correct ops of PLL.
>
> There is a test_div placed before DRAM PLL's gate, so
> add this test div clk.
>
> Signed-off-by: Anson Huang
> Signed-off-by: Irina Tirdea
>
Quoting Abel Vesa (2018-03-27 23:46:39)
> From: Dong Aisheng
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the
> clock
> is still not on.
>
> Acked-by: Ranjani Vaidyanathan
> Signed-of
Quoting Abel Vesa (2018-03-27 23:46:38)
> From: Anson Huang
>
> Design team change the ahb's clk parent options but
> did NOT update the DOC accordingly in time, so the
> AHB/IPG's clk rate in clk tree is incorrect, AHB is
> 67.5MHz and IPG is 33.75MHz, but using scope to
> monitor them, they are
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