On 10/15, Jon Mason wrote:
> The PLL loop filter/gain can be located in a separate register on some
> SoCs. Split these off into a separate variable, so that an offset can
> be added if necessary. Also, make the necessary modifications to the
> Cygnus and NSP drivers for this change.
>
> Signed-
On 10/15, Jon Mason wrote:
> Some PLLs have separate registers for Status and Control. The means the
> pll_base needs to be split into 2 new variables, so that those PLLs can
> specify device tree registers for those independently. Also, add a new
> driver flag to identify this presence of the sp
On 10/15, Scott Branden wrote:
> On 15-10-15 02:15 PM, Ray Jui wrote:
> >On 10/15/2015 2:10 PM, Jon Mason wrote:
> >>On Thu, Oct 15, 2015 at 02:04:09PM -0700, Scott Branden wrote:
> >>>On 15-10-15 01:55 PM, Ray Jui wrote:
> On 10/15/2015 1:40 PM, Scott Branden wrote:
>
> If using CONFI
On 10/15, Jon Mason wrote:
> The Broadcom Northstar 2 SoC is architected under the iProc
> architecture. It has the following PLLs: GENPLL SCR, GENPLL SW,
> LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
>
> Signed-off-by: Jon Mason
> ---
Applied to clk-iproc
--
Qualcomm Innovati
On 10/15, Jon Mason wrote:
> Document the device tree bindings for Broadcom Northstar Plus
> architecture based clock controller
>
> Signed-off-by: Jon Mason
> ---
Applied to clk-iproc
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On 10/15, Jon Mason wrote:
> Document the device tree bindings for Broadcom Northstar 2 architecture
> based clock controller
>
> Signed-off-by: Jon Mason
> ---
Applied to clk-iproc
--
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-
On 09/02/2015 09:47 AM, Bartlomiej Zolnierkiewicz wrote:
> Add suspend frequency support and set it to the boot frequency,
> this matches what the old exynos-cpufreq driver has been doing.
>
> This patch fixes suspend/resume support on Exynos4412 based
> Trats2 board and reboot hang on Exynos4412 b
On 08/03, Georgi Djakov wrote:
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> new file mode 100644
> index ..e564673ec3a5
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -0,0 +1,165 @@
> +/*
> + * Copyright (c) 2015, Linaro Limited
> + * Cop
Signed-off-by: Stephen Boyd
---
Changes since v1:
* Moved to before the smem big endian patch
drivers/soc/qcom/smd.c| 30 +-
drivers/soc/qcom/smem.c | 72 +++
include/linux/soc/qcom/smem.h | 2 +-
3 files changed, 48
The smd rpm structures are always in little endian, but this
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson
Cc: Andy Gross
Signed-off-by: Stephen Boyd
---
Changes from v1
and
word based tx/rx structures in a "channel pair" structure that
describes the layout of memory and reduces the number of pointers
in the smd channel structure by two.
Reviewed-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
Changes from v1:
* Renamed structures smd_channel_
The smd structures are always in little endian, but the smd
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
Changes from v1:
* hdr and
patches can go through arm-soc, and the last patch Mark can pick
up anytime. All patches tested on apq8074 dragonboard.
I've already written the patches to add __ioread32_copy(), but I'm
holding them until -rc1 drops because I'd rather not involve even
more people in this series just
The contents of smem are always in little endian, but the smem
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
Changes since v1:
* Rebased on
The smd rpm structures are always in little endian, but this
driver is not capable of being used on big endian CPUs. Annotate
the little endian data members and update the code to do the
proper byte swapping.
Cc: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
Changes from v1:
* New patch
We already have a function to do this and it silences some sparse
warnings along the way.
Reviewed-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
No changes
drivers/soc/qcom/smd.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/qcom/smd.c b
more clang friendly.
Cc: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
Changes from v1:
* New patch
drivers/soc/qcom/smd-rpm.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c
On 08/03, Georgi Djakov wrote:
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> new file mode 100644
> index ..bd0fd0cd50dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
low this, fix them.
>
> Signed-off-by: Viresh Kumar
Reviewed-by: Stephen Boyd
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On 09/02, Leo Yan wrote:
> The previous code, kernel builds Hi6220's common clock driver and stub
> clock driver together. Stub clock driver has introduced the dependency
> with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock
> driver due ARM64's defconfig have not enabled CONFIG_MAI
On 09/03, Tomeu Vizoso wrote:
> On 5 August 2015 at 15:09, Tomeu Vizoso wrote:
> >
> > Could this patch be removed from linux-next in the meantime?
>
> Stephen, Mike,
>
> the Tegra portion of this patch is wrong because it registers some
> clocks with a dev_id of "(null)", which is really inconv
On 09/03, Georgi Djakov wrote:
> Hi Stephen,
>
> On 09/02/2015 11:31 PM, Stephen Boyd wrote:
> > On 08/03, Georgi Djakov wrote:
> >> diff --git a/drivers/clk/qcom/clk-smd-rpm.c
> >> b/drivers/clk/qcom/clk-smd-rpm.c
> >> new file mode 100644
> >
On 07/20, Andy Gross wrote:
> This patch creates a platform driver for the SCM so that we can adequately
> manage resources. This removes clients having to carry the necessary
> clocks to use the SCM resources.
>
> Signed-off-by: Andy Gross
> ---
It would be nice if we could use this platform d
On 09/03, Gilad Avidov wrote:
> + supported by HW. Default (minimum supported) is 128.
> +
> +Example V1 PMIC-Arbiter:
>
> spmi {
> compatible = "qcom,spmi-pmic-arb";
> @@ -62,4 +66,32 @@ Example:
>
> interrupt-controller;
> #
On 09/04, Gilad Avidov wrote:
> On Thu, 3 Sep 2015 17:16:30 -0700
> Stephen Boyd wrote:
>
> > On 09/03, Gilad Avidov wrote:
> > > + supported by HW. Default (minimum
> > > supported) is 128. +
> > > +Example V1 PMIC-Arbiter:
> &g
On 10/18/2015 03:21 PM, Paul Gortmaker wrote:
> The Kconfig currently controlling compilation of this code is:
>
> drivers/tty/serial/Kconfig:config SERIAL_MSM
> drivers/tty/serial/Kconfig: bool "MSM on-chip serial port support"
>
> ...meaning that it currently is not being built as a module by
On 10/18, Viresh Kumar wrote:
> Add debugfs_create_ulong() for the users of type 'unsigned long'. These
> will be 32 bits long on a 32 bit machine and 64 bits long on a 64 bit
> machine.
>
> Signed-off-by: Viresh Kumar
> ---
Reviewed-by: Stephen Boyd
--
Qualcomm
series that has
dts changes I guess that means it should go through arm-soc:
Acked-by: Stephen Boyd
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m
Cc: Stephen Warren
Acked-by: Thierry Reding
Cc: Alexandre Courbot
Acked-by: Linus Walleij
Acked-by: Sudeep Holla
Cc: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Mark Rutland
Cc:
Cc:
Cc:
Cc:
Signed-off-by: Stephen Boyd
---
Collected the acks and resent.
arch/arm/kernel/psci_smp.c
On 10/18, Geliang Tang wrote:
> s/regsiter/register/
>
> Signed-off-by: Geliang Tang
> ---
Applied to clk-next
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On 10/16, Ray Jui wrote:
> From: Simran Rai
>
> This patch affects the clocks that use fractional ndivider in their
> PLL output frequency calculation. Instead of 2^20 divide factor, the
> clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
> integer shift with 2^20 factor.
>
>
On 10/19/2015 02:55 PM, Ray Jui wrote:
>
>
> On 15-10-19 02:49 PM, Stephen Boyd wrote:
>> On 10/16, Ray Jui wrote:
>>> From: Simran Rai
>>>
>>> This patch affects the clocks that use fractional ndivider in their
>>> PLL output frequency calculat
Drive by nitpicks
On 10/21, Brijesh Singh wrote:
> diff --git a/drivers/edac/cortex_arm64_edac.c
> b/drivers/edac/cortex_arm64_edac.c
> new file mode 100644
> index 000..c37bb94
> --- /dev/null
> +++ b/drivers/edac/cortex_arm64_edac.c
> +
> +#define L1_CACHE 0
> +#define L2_C
that cast away the const to avoid
the warnings.
Cc: David Howells
Signed-off-by: Stephen Boyd
---
arch/frv/include/asm/io.h | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h
index 70dfbea8c8d7..8062fc7
Cc: Hauke Mehrtens
Cc: Rafał Miłecki
Cc: Paul Walmsley
Cc: linux-m...@linux-mips.org
Cc: David Howells
Cc: linux-...@vger.kernel.org
Stephen Boyd (4):
frv: io: Accept const void pointers for read{b,w,l}()
lib: iomap_copy: Add __ioread32_copy()
soc: qcom: smd: Use __ioread32_copy() inste
Now that we have a generic library function for this, replace the
open-coded instance.
Cc: Hauke Mehrtens
Cc: Rafał Miłecki
Cc: Paul Walmsley
Cc: linux-m...@linux-mips.org
Signed-off-by: Stephen Boyd
---
drivers/firmware/broadcom/bcm47xx_nvram.c | 11 +++
1 file changed, 3 insertions
Some drivers need to read data out of iomem areas 32-bits at a
time. Add an API to do this.
Cc: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
include/linux/io.h | 1 +
lib/iomap_copy.c | 21 +
2 files changed, 22 insertions(+)
diff --git a/include/linux/io.h b/include
Now that we have a generic library function for this, replace the
open-coded instance.
Cc: Bjorn Andersson
Signed-off-by: Stephen Boyd
---
drivers/soc/qcom/smd.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/qcom/smd.c b/drivers/soc/qcom/smd.c
On 10/26, Javier Martinez Canillas wrote:
> Commit 4a7748c3d641 ("clk: Allow drivers to build if COMPILE_TEST is
> enabled") allowed clk drives to be compile tested on other archs but
s/drives/drivers/
> the COMMON_CLK_VERSATILE was only enabled on platforms that already
> selected OF support so
7; [-Werror=implicit-function-declaration]
Silence it by providing stubs APIs for of_clk_parent_fill().
Throw in a stub for of_clk_get_parent_count() too because we're
in the area.
Reported-by: kbuild test robot
Cc: Javier Martinez Canillas
Signed-off-by: Stephen Boyd
---
include
trees. Future bootloaders may be
updated to look at the compatible field instead of looking for
the table of contents image. For non-updateable bootloaders, a
new dtbTool program will parse the compatible string and generate
a QCDT image from it.
Signed-off-by: Stephen Boyd
---
Documentation/devic
through the board's compatible string.
[1]
http://lkml.kernel.org/g/1425503602-24916-1-git-send-email-ga...@codeaurora.org
Stephen Boyd (3):
devicetree: bindings: Document qcom board compatible format
arm64: dts: qcom: Make msm8916-mtp compatible string compliant
arm: dts: qcom: U
The ifc6540 is an sbc (single board computer) board, so update
the compatible field accordingly.
Signed-off-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
b/arch/arm
This compatible string isn't compliant with the format for
subtypes. Replace it with a compliant compatible type.
Signed-off-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mt
On 10/26/2015 08:41 AM, Yaniv Gardi wrote:
> Tnis patch fixes the following compilation warnings:
> ...ufs-qcom.c:1201:40:
> warning: incorrect type in argument 1 (different address spaces)
> ...ufs-qcom.c:1201:40:
> expected void const *ptr
> ...ufs-qcom.c:1201:40:
> got void [no
On 10/20, Georgi Djakov wrote:
> Remove the hard-coded clock rate from the driver and set the XO
> parent to the on-board XO oscillator that is defined in the DT.
>
> Signed-off-by: Georgi Djakov
> ---
> drivers/clk/qcom/gcc-msm8916.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On 10/20, Georgi Djakov wrote:
> We are moving the sleep clock to the DT. While all patches
> are merged, we will ignore sleep_clk_src registration errors.
> By ignoring this error, the msm8916 boards will continue booting
> during this transition period, otherwise the clock controller
> initializa
We want to put the XO board clocks into the dt files. Add an API
to do this generically. This also makes a place for us to handle
the case where the RPM driver is enabled or disabled.
Cc: Georgi Djakov
Signed-off-by: Stephen Boyd
---
I'm also thinking that maybe we should register the
the consumers of the crystals and the actual
clock if desired. And finally, it helps us transition the GCC
driver to use RPM clocks when the configuration is enabled.
Cc: Georgi Djakov
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 19 +++
1 file changed, 11 insert
clk: qcom: mmcc-8960: Add DSI related clocks")
Cc: Archit Taneja
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/mmcc-msm8960.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 397f5df6422a..00e36
These clocks are fixed rate board sources that should be in DT.
Add them.
Cc: Georgi Djakov
Signed-off-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts
can later share the regmap across several drivers without
> exporting a new specific API or a global void __iomem * variable.
>
> Signed-off-by: Boris Brezillon
> Signed-off-by: Alexandre Belloni
> ---
Acked-by: Stephen Boyd
--
Qualcomm Innovation Center, Inc. is a membe
On 10/01, Rajendra Nayak wrote:
> On 09/24/2015 12:39 AM, Stephen Boyd wrote:
> >The oxili_cx GDSC is inside the power domain of the oxili GDSC.
> >Add the dependency so that the CX domain can properly power up.
> >
> >Reported-by: Rob Clark
> >Cc: Rajendra Naya
On 10/01, Paul Osmialowski wrote:
> Hi Stephen,
>
> On Wed, 30 Sep 2015, Stephen Boyd wrote:
>
> > In the pinctrl node we would have
> >
> > pinctrl {
> > compatible = "fsl,kenetis70-pinctrl";
> > reg =
On 10/01, Paul Osmialowski wrote:
> From: Paul Osmialowski
>
> These two functions are added to ease management of clocks obtained
> from OF device nodes.
>
> They are particulary useful while iterating over DT subnodes using e.g.
> for_each_child_of_node(dev->of_node, child) in order do get res
On 10/01, Stephen Boyd wrote:
> On 10/01, Rajendra Nayak wrote:
> > On 09/24/2015 12:39 AM, Stephen Boyd wrote:
> > >+
> > >+ ret = pm_genpd_add_subdomain(&oxili_gdsc.pd, &oxilicx_gdsc.pd);
> >
> > We'll need pm_genpd_add_subdomain() to be EX
The oxili_cx GDSC is inside the power domain of the oxili GDSC.
Add the dependency so that the CX domain can properly power up.
Reported-by: Rob Clark
Cc: Rajendra Nayak
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/mmcc-msm8974.c | 11 ++-
1 file changed, 10 insertions(+), 1
Export these symbols so they can be used in loadable kernel
modules.
Cc: Rob Clark
Cc: Rajendra Nayak
Cc: Rafael J. Wysocki
Cc: Kevin Hilman
Cc: Ulf Hansson
Signed-off-by: Stephen Boyd
---
drivers/base/power/domain.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/base/power
I'd like to take these patches through clk tree for v4.4, so PM
maintainers please ack patch 1.
Changes from v1:
* New patch to export symbols
* Remove subdomain on driver remove
Cc: Rob Clark
Cc: Rajendra Nayak
Cc: Rafael J. Wysocki
Cc: Kevin Hilman
Cc: Ulf Hansson
Stephen Bo
On 09/30, Daniel Kurtz wrote:
> Hi Mike,
>
> On Tue, Sep 22, 2015 at 5:53 PM, James Liao wrote:
> > This is a collection of new Mediatek clocks support and fixes. These
> > patches come from Joe [1], Pi-cheng [2] and me [3], including clock
> > support for subsystems, CPU, GPT and some minor fixe
On 09/24, Andrzej Hajda wrote:
> The function can return negative value.
>
> The problem has been detected using proposed semantic patch
> scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].
>
> [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107
>
> Signed-off-by: Andrzej Hajda
On 08/31, Victorien Vedrine wrote:
> On drivers/clk/mxs/clk-frac.c, the function clk_frac_round_rate returned a bad
> result. The division before multiplication computes a wrong value ; the
> calculation is inverted to fix the problem. The second issue is that the exact
> rate have decimals and the
On 09/22, Jisheng Zhang wrote:
> diff --git a/drivers/clk/berlin/pll.c b/drivers/clk/berlin/pll.c
> new file mode 100644
> index 000..9aad0b6
> --- /dev/null
> +++ b/drivers/clk/berlin/pll.c
> @@ -0,0 +1,119 @@
> +
> +#define to_berlin_pll(hw) container_of(hw, struct berlin_pll, hw)
> +
>
On 09/22, Jisheng Zhang wrote:
> +
> +static u8 clk_div[] = {1, 2, 4, 6, 8, 12, 1, 1};
> +
> +static unsigned long berlin_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 val, divider;
> + struct berlin_clk *clk = to_berlin_c
On 09/22, Jisheng Zhang wrote:
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clk.h"
> +
> +#define CLK_SOURCE_MAX 5
> +
> +static struct clk_onecell_data gateclk_data;
> +static struct clk_onecell_data clk_data;
> +
> +static DEFINE_SPIN
On 09/22, Jisheng Zhang wrote:
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +The berlin4ct clock subsystem generates and supplies clock to various
> +controllers within the berlin4ct SoC. The berlin4ct contains 3 clock
On 09/21, Andrzej Hajda wrote:
> With unsigned values underflow in loops can occur resulting in
> theoretically infinite loops.
>
> The problem has been detected using proposed semantic patch
> scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
>
> [1]: http://permalink.gmane.org/gmane
On 09/17, Mike Looijmans wrote:
> This patch adds the driver and devicetree documentation for the
> Silicon Labs SI514 clock generator chip. This is an I2C controlled
> oscilator capable of generating clock signals ranging from 100kHz
s/oscilator/oscillator/
> to 250MHz.
>
> Signed-off-by: Mike
On 09/04, Shawn Lin wrote:
> mmc host controller's IO input/output timing is unpredictable if
> bootloader execute tuning for HS200 mode. It might make kernel failed
> to initialize mmc card in identification mode. The root cause is
> tuning phase and degree setting for HS200 mode in bootloader are
On 09/29, Martin Kepplinger wrote:
> This simplifies the given function by getting rid of the manual
> sign extension as well as saving an absolute value in an extra
> variable.
>
> Signed-off-by: Martin Kepplinger
> ---
Applied to clk-next
--
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On 09/28, Eric Anholt wrote:
> +
> +static const char *bcm2835_clock_per_parents[] = {
> +static const char *bcm2835_clock_vpu_parents[] = {
> +static const char *bcm2835_clock_osc_parents[] = {
Can these parent arrays be const char * const ?
> + "gnd",
> + "xosc",
> + "testdebug0",
>
On 09/28, Eric Anholt wrote:
> clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
> drivers are going in there so let's follow them.
>
> Signed-off-by: Eric Anholt
> Acked-by: Stephen Warren
> ---
Applied to clk-bcm2385 and merged into clk-next.
--
Qualcomm Innovation Center,
On 09/28, Eric Anholt wrote:
> Previously we've only supported a few fixed clocks based on
> assumptions about how the firmware sets up the clocks, but this
> binding will let us control the actual (audio power domain) clock
> manager.
>
> Signed-off-by: Eric Anholt
> Acked-by: Stephen Warren
>
On 09/10, Eric Anholt wrote:
> diff --git a/drivers/clk/bcm/clk-bcm2835-aux.c
> b/drivers/clk/bcm/clk-bcm2835-aux.c
> new file mode 100644
> index 000..1efa6fb
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-bcm2835-aux.c
> @@ -0,0 +1,80 @@
> +/*
> + * Copyright (C) 2015 Broadcom
> + *
> + * This
On 09/22, Andy Shevchenko wrote:
> Rename function parameter to be more explicit what it is for. This also makes
> it in align with struct clk_ops.
>
> There is no functional change.
>
> Reviewed-by: Heikki Krogerus
> Signed-off-by: Andy Shevchenko
> ---
Applied to clk-next
--
Qualcomm Innov
On 09/22, Andy Shevchenko wrote:
> The patch adds mwidth and nwidth fields to the struct clk_fractional_divider
> for further usage. While here, use GENMASK() instead of open coding this
> functionality.
>
> Reviewed-by: Heikki Krogerus
> Signed-off-by: Andy Shevchenko
> ---
Applied to clk-next
On 09/22, Andy Shevchenko wrote:
> The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when
> it
> will be switched to rational base approximation algorithm.
>
> Reviewed-by: Heiko Stuebner
> Signed-off-by: Andy Shevchenko
> ---
Applied to clk-next
--
Qualcomm Innovation
On 09/22, Andy Shevchenko wrote:
> We have couple of standard but rare used baudrates which are not supported by
> 1,8432MHz reference frequency. Besides that user can potentially ask for any
> baudrate (via BOTHER flag) and we currently don't fully support that. Since
> clk-fractional-divider is m
On 09/22, Andy Shevchenko wrote:
> This patch converts the code to use rational best approximation algorithm
> which
> is much more precise.
>
> Suggested-by: Stephen Boyd
> Reviewed-by: Heikki Krogerus
> Signed-off-by: Andy Shevchenko
> ---
Applied to clk-next
On 09/15, Kuninori Morimoto wrote:
> +
> +static int cs2000_clk_register(struct cs2000_priv *priv)
> +{
> + struct device *dev = priv_to_dev(priv);
> + struct device_node *np = dev->of_node;
> + struct clk_init_data init;
> + const char *name = np->name;
> + struct clk *clk;
> +
On 10/02, Mike Looijmans wrote:
> On 02-10-15 01:34, Stephen Boyd wrote:
> >>+ - clock-output-names: From common clock bindings. Recommended to be
> >>"si514".
> >>+ - clock-frequency: Output frequency to generate. This defines the output
> >>+
On 10/02, Eddie Huang wrote:
> On Thu, 2015-10-01 at 12:29 -0700, Stephen Boyd wrote:
> > On 09/30, Daniel Kurtz wrote:
> > > Hi Mike,
> > >
> > > On Tue, Sep 22, 2015 at 5:53 PM, James Liao
> > > wrote:
> > > > This is a c
On 10/02, Kuninori Morimoto wrote:
>
> Hi Stephen
>
> Thank you for your review
>
> > > + init.parent_names = parent_names;
> > > + init.num_parents= ARRAY_SIZE(parent_names);
> > > +
> > > + priv->hw.init = &init;
> > > +
> > > + clk = clk_register(NULL, &priv->hw);
> >
> > How a
On 09/29, Suman Anna wrote:
> diff --git a/drivers/clk/ti/clkt_dflt.c b/drivers/clk/ti/clkt_dflt.c
> index 90d7d8a21c49..1ddc288fce4e 100644
> --- a/drivers/clk/ti/clkt_dflt.c
> +++ b/drivers/clk/ti/clkt_dflt.c
> @@ -222,7 +222,7 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
> }
>
On 10/01, James Liao wrote:
> This is a collection of new Mediatek clocks support and fixes. These
> patches come from Joe [1] and me [2], including clock
> support for subsystems, GPT and some minor fixes.
>
> [1] https://patchwork.kernel.org/patch/6777041/
> [2] https://lkml.org/lkml/2015/8/10/1
On 10/02, Mike Looijmans wrote:
> This patch adds the driver and devicetree documentation for the
> Silicon Labs SI514 clock generator chip. This is an I2C controlled
> oscillator capable of generating clock signals ranging from 100kHz
> to 250MHz.
>
> Signed-off-by: Mike Looijmans
> ---
Applied
On 08/24, Gabriel Fernandez wrote:
> Change A9 PLL rate, as per requirement from the cpufreq framework,
> for DVFS. For rate change, the A9 clock needs to be temporarily sourced
> from PLL external to A9 and then sourced back to A9-PLL
>
> Signed-off-by: Pankaj Dev
> Signed-off-by: Gabriel Fernan
On 08/24, Gabriel Fernandez wrote:
> The patch adds support for enable/disable of the Clockgen PLLs.
> clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
>
> Signed-off-by: Pankaj Dev
> Signed-off-by: Gabriel Fernandez
> ---
Applied to clk-next
--
Qualcomm Innovation
On 08/24, Gabriel Fernandez wrote:
> Add support for new PLL-type for stih418 A9-PLL.
>
> Signed-off-by: Gabriel Fernandez
> ---
I assume this will go through arm-soc?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscri
On 08/24, Gabriel Fernandez wrote:
> Add support for new PLL-type for stih418 A9-PLL.
> Currently the 407_A9_PLL type being used, it is corrected with this patch
> 4600c28 PLL allows to reach higher frequencies
> so its programming algorithm is extended.
>
> Signed-off-by: Pankaj Dev
> Signed-off
Quoting Balakrishna Godavarthi (2018-08-02 06:25:12)
> This patch enables regulators for the Qualcomm Bluetooth wcn3990
> controller.
>
> Signed-off-by: Balakrishna Godavarthi
> Reviewed-by: Rob Herring
> ---
Reviewed-by: Stephen Boyd
Quoting Amit Nischal (2018-07-30 00:20:52)
> On 2018-07-26 22:52, Stephen Boyd wrote:
> > Quoting Amit Nischal (2018-07-23 04:26:33)
> >> diff --git a/drivers/clk/qcom/camcc-sdm845.c
> >> b/drivers/clk/qcom/camcc-sdm845.c
> >> new file mode 100644
> >&
Quoting Amit Nischal (2018-07-30 02:22:20)
> diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
> new file mode 100644
> index 000..702ca66
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-sdm845.c
> @@ -0,0 +1,1744 @@
> + },
> +};
> +
> +static const struct freq
Quoting Amit Daniel Kachhap (2018-07-30 22:55:55)
> This fix rounds the clock rate properly by using quotient and not
> remainder in the calculation. This issue was found while testing HDMI
> in the Juno platform.
>
> Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
> Acked-by
Quoting Steve Longerbeam (2018-07-18 10:56:51)
>
>
> On 07/06/2018 11:23 AM, Stephen Boyd wrote:
> > Quoting Steve Longerbeam (2018-05-31 18:59:17)
> >> Add checks in the .round_rate and .set_rate ops for zero requested
> >> rate or zero parent rate. If eit
nting to a backup clock.
>
> Signed-off-by: Dmitry Osipenko
> Acked-by: Peter De Schrijver
> ---
Acked-by: Stephen Boyd
Quoting Dmitry Osipenko (2018-07-24 09:42:20)
> Ensure that direct PLLM sourcing is turned off for EMC as we don't support
> that configuration in the clk driver.
>
> Signed-off-by: Dmitry Osipenko
> Acked-by: Peter De Schrijver
> ---
Acked-by: Stephen Boyd
Quoting Michal Simek (2018-07-30 05:50:42)
> On 26.7.2018 18:36, Stephen Boyd wrote:
> > Quoting Michal Simek (2018-07-25 02:51:14)
> >> On 24.7.2018 20:14, Jolly Shah wrote:
> >>>>> create mode 100644 drivers/firmware/xilinx/zynqmp-debug.h
> >>&g
Quoting Amit Nischal (2018-07-30 04:28:56)
> On 2018-07-25 12:28, Stephen Boyd wrote:
> >
> > Ok. Sounds good! Is the rate range call really needed? It can't be
> > determined in the PLL code with some table or avoided by making sure
> > GPU
> > uses OP
Quoting skan...@codeaurora.org (2018-08-03 12:52:48)
> On 2018-08-03 12:40, Evan Green wrote:
> > Hi Taniya,
> >
> > On Tue, Jul 24, 2018 at 3:44 AM Taniya Das wrote:
> >>
> >> + if (src)
> >> + c->table[i].frequency = c->xo_rate * lval /
> >> 1000;
> >> +
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