by the
AOSS QMP node and replace them with generic qmp_send interface instead.
Signed-off-by: Sibi Sankar
---
drivers/remoteproc/qcom_q6v5.c | 57 +-
drivers/remoteproc/qcom_q6v5.h | 7 +++-
drivers/remoteproc/qcom_q6v5_adsp.c | 7 +++-
drivers/remoteproc
Use the Qualcomm Mailbox Protocol (QMP) binding to control the load
state resources on SC7280 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot
Add Qualcomm Mailbox Protocol (QMP) binding to replace the power domains
exposed by the AOSS QMP node.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree
Use the Qualcomm Mailbox Protocol (QMP) binding to control the load
state resources on SC7180 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff
Use the Qualcomm Mailbox Protocol (QMP) binding to control the load
state resources on SM8150 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++--
1 file changed, 14 insertions
Use the Qualcomm Mailbox Protocol (QMP) binding to control the load
state resources on SDM845 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
Delete unused power-domain definitions exposed by AOSS QMP.
Signed-off-by: Sibi Sankar
---
include/dt-bindings/power/qcom-aoss-qmp.h | 14 --
1 file changed, 14 deletions(-)
delete mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h
diff --git a/include/dt-bindings/power/qcom
Use the Qualcomm Mailbox Protocol (QMP) binding to control the load
state resources on SM8350 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 --
1 file changed, 16 insertions
Use the Qualcomm Mailbox Protocol (QMP) binding to control the load
state resources on SM8250 SoCs and drop deprecated power-domains exposed
by AOSS QMP node.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 +++---
1 file changed, 11 insertions(+), 11
On 2021-03-24 12:19, Sibi Sankar wrote:
On 2021-03-24 03:36, Stephen Boyd wrote:
Quoting Bjorn Andersson (2021-03-13 20:16:39)
On Sat 13 Mar 15:46 CST 2021, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-03-08 21:51:51)
> > Add miscellaneous nodes to boot the Wireless Processor Sub
On 2021-03-14 03:07, Stephen Boyd wrote:
Quoting Sibi Sankar (2021-03-08 21:51:49)
Add PDC Global reset controller bindings for SC7280 SoCs.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4
include/dt-bindings/reset/qcom,sdm845-pdc.h
Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support
frequencies upto 2.5 GHz.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom
Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
since the gold cores only support frequencies upto 2.1 GHz.
Signed-off-by: Sibi Sankar
---
V2:
* Updated the lite ddr/l3 cpufreq map to have better power numbers with
similar perf.
arch/arm64/boot/dts/qcom/sc7180
On 2021-03-10 12:58, Rakesh Pillai wrote:
Add WPSS PIL loading support for SC7280 SoCs.
Signed-off-by: Rakesh Pillai
---
.../bindings/remoteproc/qcom,hexagon-v56.txt | 35
--
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git
a/Documentation/devicetree/bi
On 2021-03-10 12:58, Rakesh Pillai wrote:
Add support for PIL loading of WPSS processor for SC7280
WPSS boot will be requested by the wifi driver and hence
disable auto-boot for WPSS. Also add a separate shutdown
sequence handler for WPSS.
Signed-off-by: Rakesh Pillai
---
drivers/remoteproc/qc
On 2021-03-10 13:07, Rakesh Pillai wrote:
Add the WPSS remoteproc node in dts for
PIL loading.
Signed-off-by: Rakesh Pillai
---
- This change is dependent on the below patch series
1) https://lore.kernel.org/patchwork/project/lkml/list/?series=487403
2) https://lore.kernel.org/patchwork/project
Add WPSS remote processor client index to Inter-Processor Communication
Controller (IPCC) block.
Signed-off-by: Sibi Sankar
---
include/dt-bindings/mailbox/qcom-ipcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h
b/include/dt-bindings/mailbox/qcom
Update max processor count to reflect the number of co-processors on
SC7280 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/smem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index cc4e0655a47b..4fb5aeeb0843 100644
Add PDC Global reset controller bindings for SC7280 SoCs.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4
include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/Documentation
Add PDC Global reset signals for Wireless Processor Subsystem (WPSS)
on SC7280 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/reset/reset-qcom-pdc.c | 62 ++
1 file changed, 51 insertions(+), 11 deletions(-)
diff --git a/drivers/reset/reset-qcom-pdc.c b
Add AOSS reset controller bindings for SC7280 SoCs.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
b/Documentation/devicetree
This series enables miscellaneous hardware blocks to boot Wireless
Processor Subsystem (WPSS) on SC7280 SoC.
[1] https://lore.kernel.org/patchwork/cover/1389010/
The series depends on ^^
Sibi Sankar (6):
soc: qcom: smem: Update max processor count
dt-bindings: mailbox: Add WPSS client index
Add miscellaneous nodes to boot the Wireless Processor Subsystem on
SC7280 SoCs.
Signed-off-by: Sibi Sankar
---
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^
arch/arm64/boot/dts/qcom/sc7280.dtsi | 143
On 2021-02-27 19:26, Sai Prakash Ranjan wrote:
On 2021-02-27 00:16, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
On 2021-02-26 01:11, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
>> Add a DT node for the AOSS QMP on SC7280 SoC.
>>
>> Signed-off-
On 3/13/19 2:30 PM, Georgi Djakov wrote:
Here is a proposal to extend the OPP bindings with bandwidth based on
a previous discussion [1].
Every functional block on a SoC can contribute to the system power
efficiency by expressing its own bandwidth needs (to memory or other SoC
modules). This
Hey Philipp,
Thanks for the review!
On 2019-08-26 14:06, Philipp Zabel wrote:
On Sat, 2019-08-24 at 20:54 +0530, Sibi Sankar wrote:
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 4 ++--
1
Hey Stephen,
Thanks for the review!
On 2019-08-30 11:02, Stephen Boyd wrote:
Quoting Sibi Sankar (2019-08-24 08:24:10)
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 4 ++--
Can you
On some Qualcomm SoCs, Operating State Manager (OSM) controls the
resources of scaling L3 caches. Add a driver to handle bandwidth
requests to OSM L3 from CPU/GPU.
Signed-off-by: Sibi Sankar
---
drivers/interconnect/qcom/Kconfig | 7 +
drivers/interconnect/qcom/Makefile | 2 +
drivers
This patch series aims to add Operating State Manager (OSM) L3
interconnect provider support on SDM845 SoCs to handle bandwidth
requests from CPU to scale L3 caches.
v2:
* addressed review comments from Evan
* dropped unused gpu icc node on SDM845 SoC
Sibi Sankar (2):
dt-bindings
Add bindings for Operating State Manager (OSM) L3 interconnect provider
on SDM845 SoCs.
Signed-off-by: Sibi Sankar
---
.../bindings/interconnect/qcom,osm-l3.yaml| 56 +++
.../dt-bindings/interconnect/qcom,osm-l3.h| 12
2 files changed, 68 insertions(+)
create mode
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
b/Documentation
This patch series adds PDC Global and AOSS reset support on SC7180 SoCs.
Sibi Sankar (4):
dt-bindings: reset: aoss: Add AOSS reset binding for SC7180 SoCs
reset: qcom: aoss: Add support for SC7180 SoCs
dt-bindings: reset: pdc: Add PDC Global binding for SC7180 SoCs
reset: qcom: pdc: Add
Add AOSS reset support for SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/reset/reset-qcom-aoss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c
index 36db967504507..a400db93eb7d2 100644
--- a/drivers/reset/reset-qcom
Add PCD Global support for SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/reset/reset-qcom-pdc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
index ab74bccd4a5b5..d876e48f05524 100644
--- a/drivers/reset/reset-qcom
Add SC7180 PDC global to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
b/Documentation
5-mss: Vote for rpmh power domains")
Signed-off-by: Sibi Sankar
---
drivers/remoteproc/qcom_q6v5_mss.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c
b/drivers/remoteproc/qcom_q6v5_mss.c
index 8fcf9d28dd731..de919f2e8b949 100644
---
, I missed
removing prev_cc.
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
Hey Philipp,
Thanks for the review!
On 2019-08-21 16:02, Philipp Zabel wrote:
On Wed, 2019-08-21 at 15:24 +0530, Sibi Sankar wrote:
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 3 ++-
1
Convert AOSS reset bindings to yaml and add SC7180 AOSS reset to the list
of possible bindings.
Signed-off-by: Sibi Sankar
---
.../bindings/reset/qcom,aoss-reset.txt| 52 ---
.../bindings/reset/qcom,aoss-reset.yaml | 47 +
2 files changed, 47
Convert PDC Global bindings to yaml and add SC7180 PDC global to the list
of possible bindings.
Signed-off-by: Sibi Sankar
---
.../bindings/reset/qcom,pdc-global.txt| 52 ---
.../bindings/reset/qcom,pdc-global.yaml | 47 +
2 files changed, 47
This patch series converts PDC Global and AOSS reset bindings to yaml
and adds support on SC7180 SoCs.
v3:
* Convert to yaml bindings
v2:
* Addressed Philipp's review comments
Sibi Sankar (2):
dt-bindings: reset: aoss: Convert AOSS reset bindings to yaml
dt-bindings: reset: pdc: Co
This patch series adds PDC Global and AOSS reset support on SC7180 SoCs.
v2:
* Addressed Philipp's review comments
Sibi Sankar (2):
dt-bindings: reset: aoss: Add AOSS reset binding for SC7180 SoCs
dt-bindings: reset: pdc: Add PDC Global binding for SC7180 SoCs
Documentation/devic
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
b/Documentation
Add SC7180 PDC global to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
b/Documentation
Add SC7180 AOSS reset to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt
b/Documentation
This patch series adds PDC Global and AOSS reset support on SC7180 SoCs.
v2:
* Addressed Philipp's review comments
Sibi Sankar (2):
dt-bindings: reset: aoss: Add AOSS reset binding for SC7180 SoCs
dt-bindings: reset: pdc: Add PDC Global binding for SC7180 SoCs
Documentation/devic
Add SC7180 PDC global to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.txt
b/Documentation
Hey Georgi,
On 2019-09-27 04:46, Georgi Djakov wrote:
Hi Sibi,
On 8/21/19 02:11, Sibi Sankar wrote:
Add bindings for Operating State Manager (OSM) L3 interconnect
provider
on SDM845 SoCs.
Signed-off-by: Sibi Sankar
---
.../bindings/interconnect/qcom,osm-l3.yaml| 56
subsystem. A single regmap doesn't seem correct either.
Why isn't a single regmap correct? The PDC driver should be able to use
it to read/write into this register space. The lock on the regmap will
need to be changed to a raw lock though for RT. Otherwise it looks OK
to
me.
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
king power-controller.. Bjorn?
aoss_qmp registers both pd and
clock providers.
--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar
---
v2:
* Address Chanwoo's review comments
This patch is a re-work of:
https://patchwork.kernel.org/patch/10553171/
This patch depends on Saravana's add required-opps support series:
https://patchwork.kernel.org/cove
Hey Saravana,
Thanks for taking time to post out this series.
On 6/26/19 3:03 AM, Saravana Kannan wrote:
A Device-A can have a (minimum) performance requirement on another
Device-B to be able to function correctly. This performance requirement
on Device-B can also change based on the current per
Hey Saravana,
Thanks for taking time to post out this series.
On 6/26/19 3:03 AM, Saravana Kannan wrote:
A Device-A can have a (minimum) performance requirement on another
Device-B to be able to function correctly. This performance requirement
on Device-B can also change based on the current per
Hey Saravana,
https://patchwork.kernel.org/patch/10850815/
There was already a discussion ^^ on how bandwidth bindings were to be
named.
On 7/3/19 6:40 AM, Saravana Kannan wrote:
Interconnects often quantify their performance points in terms of
bandwidth. So, add opp-peak-KBps (required) and op
Hey Saravana,
On 7/3/19 6:40 AM, Saravana Kannan wrote:
Not all devices quantify their performance points in terms of frequency.
Devices like interconnects quantify their performance points in terms of
bandwidth. We need a way to represent these bandwidth levels in OPP. So,
add support for parsi
Hey Saravana,
On 6/26/19 3:03 AM, Saravana Kannan wrote:
The OPP table can be used often in devfreq. Trying to get it each time can
be expensive, so cache it in the devfreq struct.
Signed-off-by: Saravana Kannan
---
drivers/devfreq/devfreq.c | 6 ++
include/linux/devfreq.h | 1 +
2 f
Hey Saravana,
On 6/18/19 2:48 AM, Saravana Kannan wrote:
On Mon, Jun 17, 2019 at 8:44 AM Georgi Djakov wrote:
Hi Saravana,
On 6/14/19 07:17, Saravana Kannan wrote:
Add a icc_create_devfreq() and icc_remove_devfreq() to create and remove
devfreq devices for interconnect paths. A driver can c
reg = <0x0 0x8082 0x0 0x2>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
--
-- Sibi Sankar --
Qualcomm Inn
45-cdsp-pas:
qcom,sm8150-adsp-pas:
qcom,sm8150-cdsp-pas:
+ qcom,sm8250-adsp-pas:
Looks like adsp also uses lcx and lmx
similar to slpi, the rest looks good
Reviewed-by: Sibi Sankar
+ qcom,sm8250-cdsp-pas:
must be "cx", "load_state&qu
quot;load_state",
+ NULL
+ },
+ .proxy_pd_names = (char*[]){
+ "cx",
+ "mx",
you may want to name it as lcx, lmx.
The remaining looks good!
Reviewed-by: Sibi Sankar
+ NULL
+ },
+ .ssr_name
On 2019-10-18 11:27, Bjorn Andersson wrote:
Specify the firmware-name for the adsp, cdsp and mpss and enable the
nodes.
Signed-off-by: Bjorn Andersson
Reviewed-by: Sibi Sankar
---
.../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 14 ++
1 file changed, 14 insertions
core prohibits probe deferal past late initcall.
Signed-off-by: Bjorn Andersson
Reviewed-by: Sibi Sankar
---
arch/arm64/configs/defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/configs/defconfig
b/arch/arm64/configs/defconfig
index c9a867ac32d4..42f042ba1039
Update max processor count to reflect the number of
co-processors on SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/smem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index f27c00d82ae49..bef8502625f96
Add compatible for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
b/Documentation/devicetree/bindings/firmware/qcom
Add SM8150 and SC7180 APSS shared to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
b
This patch series adds SCM, APSS shared mailbox and QMP AOSS PD/clock
support on SM8150 and SC7180 SoCs.
Sibi Sankar (6):
soc: qcom: smem: Update max processor count
dt-bindings: firmware: scm: Add SM8150 and SC7180 support
dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
Add SM8150 and SC7180 AOSS QMP to the list of possible bindings.
Signed-off-by: Sibi Sankar
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
b
Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index
Add AOSS QMP support for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/qcom_aoss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 5f885196f4d0f..e2f8c7c9a5a0a 100644
--- a/drivers/soc/qcom
Hey Bjorn,
Thanks for the review!
On 2019-07-29 21:08, Bjorn Andersson wrote:
On Mon 29 Jul 05:06 PDT 2019, Sibi Sankar wrote:
This patch series adds SCM, APSS shared mailbox and QMP AOSS PD/clock
support on SM8150 and SC7180 SoCs.
Thanks Sibi, this looks good.
Could you please update the
On 2019-01-18 04:35, Doug Anderson wrote:
Hi,
On Mon, Jan 14, 2019 at 11:22 AM Sibi Sankar
wrote:
+ mss_pil: remoteproc@408 {
+ compatible = "qcom,sdm845-mss-pil";
+ reg = <0x0408 0x408>, <0x0418 0x4
we are planning to start/stop mss through
rmtfs.
Acked-by: Sibi Sankar
---
drivers/remoteproc/qcom_q6v5_pil.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c
b/drivers/remoteproc/qcom_q6v5_pil.c
index cbbafdcaaecb..719ee96445b3 100644
--- a/dri
This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs.
Signed-off-by: Sibi Sankar
Reviewed-by: Douglas Anderson
---
v6:
* Drop unused mbox-names property
* Add mss_pil label
* Rebased to Andy's for-next
v5:
* Use qmp_aop updated dt binding
v3:
* with shutdown-ack irq red
Add support for parsing "firmware-name" dt bindings which specifies
the relative paths of mba/modem/pas image as strings. Fallback to
the default paths for mba/modem/pas image on -EINVAL.
Signed-off-by: Sibi Sankar
---
v3:
* Fixed minor code style issues
* Add comments for firmware
On 2019-01-19 00:05, Brian Norris wrote:
On Thu, Jan 17, 2019 at 11:04 PM Sibi Sankar
wrote:
On 2018-05-29 09:50, Bjorn Andersson wrote:
> On Thu 24 May 12:21 PDT 2018, Ramon Fried wrote:
Whoa, bringing up a 7-month old patch? Nice.
>> Sometimes that rmtfs userspace module is no
Hi Brian,
Thanks for the review
On 2019-01-19 02:34, Brian Norris wrote:
Hi Sibi,
On Fri, Jan 18, 2019 at 11:46 AM Sibi Sankar
wrote:
On 2019-01-19 00:05, Brian Norris wrote:
> On Thu, Jan 17, 2019 at 11:04 PM Sibi Sankar
>> After experimenting with in kernel solutions for
y from the mailing list post) it had clock properties.
I presume that the clock should be there, so let's add it.
Tested-by: Sibi Sankar
Fixes: be7019103469 ("dts: arm64/sdm845: Add WCN3990 WLAN module device
node")
Signed-off-by: Douglas Anderson
[bjorn: Add also the require
:
Hi,
I agree this approach absolutely.
Just I add some comments. Please check it.
On 19. 3. 29. 오전 12:28, Sibi Sankar wrote:
From: Saravana Kannan
Many CPU architectures have caches that can scale independent of the
CPUs. Frequency scaling of the caches is necessary to make sure the
cache
is
From: Bjorn Andersson
QCS404 uses individual resource type magic for each power-domain, so
adjust the macros slightly to make them reusable for this.
Signed-off-by: Bjorn Andersson
[sibi: Extend rpmpd corner pair to a generic rpmpd pair]
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom
rpmpd max state varies across SoCs and SoC families, add support
in the driver to make it SoC/SoC family specific
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom
From: Bjorn Andersson
Add RPM power domain bindings for the qcs404 family of SoC
Signed-off-by: Bjorn Andersson
Reviewed-by: Rob Herring
[sibis: Add supported rpmpd states for qcs404]
Signed-off-by: Sibi Sankar
---
.../devicetree/bindings/power/qcom,rpmpd.txt | 1 +
include/dt-bindings
From: Bjorn Andersson
Add the shared cx/mx and the low-power-island's cx and mx power-domains
found on QCS404.
Signed-off-by: Bjorn Andersson
[sibi: Fixup corner/vfc with vlfl/vfl]
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 52 +++-
1
From: Bjorn Andersson
Add the rpmpd node on the qcs404 and define the available levels.
Signed-off-by: Bjorn Andersson
[sibis: fixup available levels]
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 55
1 file changed, 55 insertions(+)
diff
r get/set performance
state")
Reviewed-by: Marc Gonzalez
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 005326050c23..235d01870dd8 100644
--- a/drivers/soc/qc
Add RPM power domain bindings for the msm8998 family of SoC
Reviewed-by: Rob Herring
Signed-off-by: Sibi Sankar
---
.../devicetree/bindings/power/qcom,rpmpd.txt | 1 +
include/dt-bindings/power/qcom-rpmpd.h | 12
2 files changed, 13 insertions(+)
diff --git
: qcom: rpmpd: Add QCS404 power-domains
arm64: dts: qcom: qcs404: Add rpmpd node
Sibi Sankar (5):
soc: qcom: rpmpd: fixup rpmpd set performance state
soc: qcom: rpmpd: Add support to set rpmpd state to max
dt-bindings: power: Add rpm power domain bindings for msm8998
soc: qcom: rpmpd: Add
Add the rpmpd node on the msm8998 and define the available levels.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 51 +++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64/boot/dts/qcom/msm8998.dtsi
Add the shared cx/mx and sensor sub-system's cx and mx
power-domains found on MSM8998.
Signed-off-by: Sibi Sankar
---
drivers/soc/qcom/rpmpd.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
Hey Bjorn,
On 5/1/19 10:07 AM, Bjorn Andersson wrote:
The Always On Subsystem (AOSS) Qualcomm Messaging Protocol (QMP) driver
is used to communicate with the AOSS for certain side-channel requests,
that are not available through the RPMh interface.
The communication is a very simple synchronous
[Sibi: Integrated cpu-freqmap governor into passive_governor]
Signed-off-by: Sibi Sankar
---
drivers/devfreq/Kconfig| 4 +
drivers/devfreq/governor_passive.c | 276 -
include/linux/devfreq.h| 43 -
3 files changed, 315 insertions(
Export 'dev_pm_opp_find_opp_of_np' and 'of_parse_required_nodes'
as it will be used by passive governor to parse and auto-populate
mapping specified using the required-opps property.
Signed-off-by: Sibi Sankar
---
drivers/opp/of.c | 13 +++--
include
q: Add cpu based scaling support to passive_governor
PM / devfreq: Add devfreq driver for interconnect bandwidth voting
Sibi Sankar (7):
OPP: Add and export helpers to get avg/peak bw
OPP: Export a number of helpers to prevent code duplication
dt-bindings: devfreq: Add bindings for devfre
Add and export helpers 'dev_pm_opp_get_avg_bw()' and
'dev_pm_opp_get_peak_bw()' that can be used to get the
average and peak bandwidth values read from device tree
when present.
Signed-off-by: Sibi Sankar
---
drivers/opp/core.c | 38 +
Add dt-bindings support for a generic interconnect bandwidth voting
devfreq driver.
Signed-off-by: Sibi Sankar
---
.../devicetree/bindings/devfreq/icbw.txt | 146 ++
1 file changed, 146 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/icbw.txt
ff-by: Saravana Kannan
[Sibi: cleanup and added passive governor support]
Signed-off-by: Sibi Sankar
---
drivers/devfreq/Kconfig| 15
drivers/devfreq/Makefile | 1 +
drivers/devfreq/devfreq_icbw.c | 132 +
3 files changed, 148 insertions(+)
c
Add and export 'dev_pm_opp_update_voltage' to find and update voltage
of an opp for a given frequency. This will be useful to update the opps
with voltages read back from firmware.
Signed-off-by: Sibi Sankar
---
drivers/opp/core.c | 62 +
Add a OPP tables for the cpu nodes.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 182 +++
1 file changed, 182 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cd8ac481381b
Add nodes to enable DDR devfreq driver on SDM845 SoC.
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index
Add support to parse and update OPP tables attached to the cpu nodes.
Signed-off-by: Sibi Sankar
---
drivers/cpufreq/qcom-cpufreq-hw.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom
Hey Georgi,
On 4/23/19 6:58 PM, Georgi Djakov wrote:
This is the same as the traditional of_icc_get() function, but the
difference is that it takes index as an argument, instead of name.
Signed-off-by: Georgi Djakov
---
drivers/interconnect/core.c | 45
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