Hi Mike,
I came across your "[PATCH v2 0/5] clk: dt: bindings for mux, divider &
gate clocks" email from 16 Jun 2013. The DT bindings for simple clock
multiplexers would be very helpful for a board I am working on. Do you
see any chance to get it into mainline?
Many thanks in advance!
Regard
The divider calculation for multisynth 6 and 7 differs from the
calculation for multisynth 0-5.
For MS6 and MS7, set MSx_P1 directly, MSx_P1=divide value
[AN619, p. 6].
Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4
Signed-off-by: Sergej Sawazki
---
drivers
Sebastian,
thanks for your reply, please find my comments below:
On 06.04.2015 18:43, Sebastian Hesselbarth wrote:
> On 06.04.2015 16:25, Sergej Sawazki wrote:
>> The divider calculation for multisynth 6 and 7 differs from the
>> calculation for multisynth 0-5.
>>
>>
The divider calculation for multisynth 6 and 7 differs from the
calculation for multisynth 0-5.
For MS6 and MS7, set MSx_P1 directly, MSx_P1=divide value
[AN619, p. 6].
Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4
Signed-off-by: Sergej Sawazki
---
drivers
MS6 and MS7 do not have the MSx_P3 field. Do the 'params.p3 == 0'
check for MS0-M5 only. See [AN619, p. 6] for details.
Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4
Signed-off-by: Sergej Sawazki
---
drivers/clk/clk-si5351.c | 5 ++---
1 file
Hello all,
when I try to read the register values of a i2c ASoC codec through
debugfs, (eg: cat /sys/kernel/debug/regmap/1-001a/registers)
I am getting an WARN_ON at drivers/base/regmap/regmap-debugfs.c:151.
Please see attached dmesg.txt for details.
I did some debugging and found that regmap_re
Am 15. Juni 2015 11:49:22 MESZ, schrieb Mark Brown :
>On Sat, Jun 13, 2015 at 03:21:02PM +0200, Sergej Sawazki wrote:
>
>> I did some debugging and found that regmap_readable(), at regmap-
>> debugfs.c:109, returns "false" for all registers, hence the
>> debugf
On Mon, 15 Jun 2015 15:49:33 +0100, Mark Brown wrote:
On Mon, Jun 15, 2015 at 02:42:30PM +0200, Sergej Sawazki wrote:
Am 15. Juni 2015 11:49:22 MESZ, schrieb Mark Brown :
We need to change that code to special case write only register maps
like this and just skip having a cache for those
Stephen, thanks for the review...
On 21.05.2015 at 21:31 Stephen Boyd wrote:
+static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_gpio_mux *clk = to_clk_gpio_mux(hw);
+
+ if (index > 1)
+ return -EINVAL;
Doesn't seem possible if num_parents
Jyri, thanks for the review...
On 22.05.2015 at 11:13 Jyri Sarha wrote:
On 05/14/15 12:40, Sergej Sawazki wrote:
+Optional properties:
+- enable-gpios : GPIO reference for enabling and disabling the clock.
I guess in theory you should not need the enable functionality here. You
could just
On 15.05.2015 at 11:25 Sebastian Hesselbarth wrote:
Sergej Sawazki (2):
clk: si5351: fix .round_rate for multisynth 6-7
clk: si5351: fix .recalc_rate for multisynth 6-7
Applied both patches to clk-next.
Sergei,
next time please _always_ keep the version numbering on your patches
nable or
disable the clock output.
Signed-off-by: Sergej Sawazki
---
.../devicetree/bindings/clock/gpio-mux-clock.txt | 23 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-gpio-mux.c | 301 +
include/
patch series fixes that.
Patch 1 fixes the divider calculation for multisynth 6 and 7.
Patch 2 fixes the divider re-calculation for multisynth 6 and 7.
Info: Base on branch 'clk-fixes'.
Sergej Sawazki (2):
clk: si5351: fix .round_rate for multisynth 6-7
clk: si5351: fix .recal
MS6 and MS7 do not have the MSx_P3 field. Do the 'params.p3 == 0'
check for MS0-M5 only. See [AN619, p. 6] for details.
Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4
Signed-off-by: Sergej Sawazki
---
drivers/clk/clk-si5351.c | 5 ++---
1 file
The divider calculation for multisynth 6 and 7 differs from the
calculation for multisynth 0-5.
For MS6 and MS7, set MSx_P1 directly, MSx_P1=divide value
[AN619, p. 6].
Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4
Signed-off-by: Sergej Sawazki
---
drivers
Am 22.03.2015 um 18:10 schrieb Michael Turquette:
Quoting Sergej Sawazki (2015-03-19 14:50:50)
Hi Mike,
I came across your "[PATCH v2 0/5] clk: dt: bindings for mux, divider &
gate clocks" email from 16 Jun 2013. The DT bindings for simple clock
multiplexers would be very helpful
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