On 01.08.19 11:55, Uwe Kleine-König wrote:
> On Thu, Aug 01, 2019 at 09:28:33AM +0000, Schrempf Frieder wrote:
>> Hi Uwe,
>>
>> On 01.08.19 10:48, Uwe Kleine-König wrote:
>>> On Thu, Aug 01, 2019 at 08:18:05AM +, Schrempf Frieder wrote:
>>>> From: Fri
From: Frieder Schrempf
If CONFIG_GPIOLIB is not enabled, mctrl_gpio_init() and
mctrl_gpio_init_noauto() will currently return an error pointer with
-ENOSYS. As the mctrl GPIOs are usually optional, drivers need to
check for this condition to allow continue probing.
To avoid the need for this che
From: Frieder Schrempf
If CONFIG_GPIOLIB is not enabled, mctrl_gpio_init() and
mctrl_gpio_init_noauto() will currently return an error pointer with
-ENOSYS. As the mctrl GPIOs are usually optional, drivers need to
check for this condition to allow continue probing.
To avoid the need for this che
From: Frieder Schrempf
Now that the mctrl_gpio code returns NULL instead of ERR_PTR(-ENOSYS)
in cases when CONFIG_GPIOLIB is disabled, we can safely remove this
check.
Signed-off-by: Frieder Schrempf
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
From: Frieder Schrempf
Now that the mctrl_gpio code returns NULL instead of ERR_PTR(-ENOSYS)
in cases when CONFIG_GPIOLIB is disabled, we can safely remove this
check.
Signed-off-by: Frieder Schrempf
---
drivers/tty/serial/8250/8250_core.c | 6 ++
1 file changed, 2 insertions(+), 4 deletio
On 01.08.19 22:33, Uwe Kleine-König wrote:
> On Thu, Aug 01, 2019 at 06:45:21PM +0000, Schrempf Frieder wrote:
>> From: Frieder Schrempf
>>
>> If CONFIG_GPIOLIB is not enabled, mctrl_gpio_init() and
>> mctrl_gpio_init_noauto() will currently return an error pointer wi
On 01.08.19 22:39, Uwe Kleine-König wrote:
> On Thu, Aug 01, 2019 at 06:45:24PM +0000, Schrempf Frieder wrote:
>> From: Frieder Schrempf
>>
>> Now that the mctrl_gpio code returns NULL instead of ERR_PTR(-ENOSYS)
>> in cases when CONFIG_GPIOLIB is disabled, we can
From: Frieder Schrempf
Now that the mctrl_gpio code returns NULL instead of ERR_PTR(-ENOSYS)
if CONFIG_GPIOLIB is disabled, we can safely remove this check.
Signed-off-by: Frieder Schrempf
---
Changes in v3
=
* Adjust the commit message and subject line
Changes in v2
=
From: Frieder Schrempf
If CONFIG_GPIOLIB is not enabled, mctrl_gpio_init() and
mctrl_gpio_init_noauto() will currently return an error pointer with
-ENOSYS. As the mctrl GPIOs are usually optional, drivers need to
check for this condition to allow continue probing.
To avoid the need for this che
From: Frieder Schrempf
Now that the mctrl_gpio code returns NULL instead of ERR_PTR(-ENOSYS)
if CONFIG_GPIOLIB is disabled, we can safely remove this check.
Signed-off-by: Frieder Schrempf
---
Changes in v3
=
* Adjust the commit message and subject line
Changes in v2
=
From: Frieder Schrempf
As it is allowed to use the mctrl_gpio_* functions before
initialization (as the 8250 driver does according to 434be0ae7aa7),
it seems appropriate to have a NULL check in all of the functions.
Otherwise the mctrl_gpio_to_gpiod() function is prone to be used
in a context tha
On 26.07.19 08:17, Krzysztof Kozlowski wrote:
> Add vendor prefix for Admatec AG.
We get the displays used with the Kontron eval kits from "admatec GmbH"
in Hamburg, not "Admatec AG" in Switzerland. I think we have to
differentiate here.
I will review patch 2/2 soon...
>
> Signed-off-by: Krzy
On 26.07.19 12:02, Krzysztof Kozlowski wrote:
> On Fri, 26 Jul 2019 at 11:48, Schrempf Frieder
> wrote:
>>
>> On 26.07.19 08:17, Krzysztof Kozlowski wrote:
>>> Add vendor prefix for Admatec AG.
>>
>> We get the displays used with the Kontron eval kits
On 02.08.19 14:12, Uwe Kleine-König wrote:
> On Fri, Aug 02, 2019 at 10:04:10AM +0000, Schrempf Frieder wrote:
>> From: Frieder Schrempf
>>
>> As it is allowed to use the mctrl_gpio_* functions before
>> initialization (as the 8250 driver does according to 434be0a
On 06.08.19 09:45, Uwe Kleine-König wrote:
> Hello Frieder,
>
> On Mon, Aug 05, 2019 at 09:01:39AM +, Schrempf Frieder wrote:
>> On 02.08.19 14:12, Uwe Kleine-König wrote:
>>> On Fri, Aug 02, 2019 at 10:04:10AM +, Schrempf Frieder wrote:
>>>> From:
On 29.07.19 19:20, Krzysztof Kozlowski wrote:
> Add support for i.MX6UL modules from Kontron Electronics GmbH (before
> acquisition: Exceet Electronics) and evalkit boards based on it:
>
> 1. N6310 SOM: i.MX6 UL System-on-Module, a 25x25 mm solderable module
> (LGA pads and pin castellations)
From: Frieder Schrempf
The imx I2C controller is used in some ARM64 SoCs such as i.MX8M.
To make use of it, append ARM64 to the list of dependencies.
Signed-off-by: Frieder Schrempf
---
drivers/i2c/busses/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/b
From: Frieder Schrempf
The FEC ethernet controller is used in some ARM64 SoCs such as i.MX8.
To make use of it, append ARM64 to the list of dependencies.
Signed-off-by: Frieder Schrempf
---
drivers/net/ethernet/freescale/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 07.08.19 14:20, Fabio Estevam wrote:
> Hi Frieder,
>
> On Wed, Aug 7, 2019 at 9:04 AM Schrempf Frieder
> wrote:
>>
>> From: Frieder Schrempf
>>
>> The FEC ethernet controller is used in some ARM64 SoCs such as i.MX8.
>> To make use of it
On 07.08.19 14:09, Alexander Stein wrote:
> On Wednesday, August 7, 2019, 1:44:06 PM CEST Schrempf Frieder wrote:
>> From: Frieder Schrempf
>>
>> The imx I2C controller is used in some ARM64 SoCs such as i.MX8M.
>> To make use of it, append ARM64 to the list of depend
On 08.08.19 19:26, Krzysztof Kozlowski wrote:
> Document the compatible for ANV32E61W EEPROM chip.
This chip is actually not an EEPROM, but a SPI nvSRAM. It can be
interfaced by the at25 driver similar to an EEPROM. This is not the
ideal solution, but it works until there's a proper driver for s
On 20.06.19 03:00, liaoweixiong wrote:
> In case of the last page containing bitflips (ret > 0),
> spinand_mtd_read() will return that number of bitflips for the last
> page. But to me it looks like it should instead return max_bitflips like
> it does when the last page read returns with 0.
>
> Si
On 24.06.19 14:15, liaoweixiong wrote:
> In case of the last page containing bitflips (ret > 0),
> spinand_mtd_read() will return that number of bitflips for the last
> page. But to me it looks like it should instead return max_bitflips like
> it does when the last page read returns with 0.
>
> Si
Hi liaoweixiong,
On 25.06.19 05:08, Greg KH wrote:
> On Tue, Jun 25, 2019 at 09:02:29AM +0800, liaoweixiong wrote:
>> In case of the last page containing bitflips (ret > 0),
>> spinand_mtd_read() will return that number of bitflips for the last
>> page. But to me it looks like it should instead re
Hi Jeff,
On 18.06.19 19:08, Jeff Kletsky wrote:
> From: Jeff Kletsky
>
> Add initial support for Paragon Technology
> PN26G01Ax and PN26G02Ax SPI NAND
>
> Datasheets available at
> http://www.xtxtech.com/upfile/2016082517274590.pdf
> http://www.xtxtech.com/upfile/2016082517282329.pdf
>
On 19.06.19 15:46, Boris Brezillon wrote:
> Hi liaoweixiong,
>
> On Wed, 19 Jun 2019 21:13:24 +0800
> liaoweixiong wrote:
>
>> In function spinand_mtd_read, if the last page to read occurs bitflip,
>> this function will return error value because veriable ret not equal to 0.
>
> Actually, that'
On 25.06.19 13:56, liaoweixiong wrote:
> Oh, i am sorry that i had misunderstanded your letter.
No problem ;)
> Thank you for your document and guidance.
You're welcome!
> On 2019/6/25 PM 3:04, Schrempf Frieder wrote:
>> Hi liaoweixiong,
>>
>> On 25.06.19 05:08
From: Frieder Schrempf
The 1Gb Macronix chip can have a maximum of 20 bad blocks, while
the 2Gb version has twice as many blocks and therefore the maximum
number of bad blocks is 40.
The 4Gb GigaDevice GD5F4GQ4xA has twice as many blocks as its 2Gb
counterpart and therefore a maximum of 80 bad b
On 18.06.19 19:08, Jeff Kletsky wrote:
> From: Jeff Kletsky
>
> Add initial support for Paragon Technology
> PN26G01Ax and PN26G02Ax SPI NAND
>
> Datasheets available at
> http://www.xtxtech.com/upfile/2016082517274590.pdf
> http://www.xtxtech.com/upfile/2016082517282329.pdf
>
> Signed-
On 08.01.19 10:24, Yogesh Narayan Gaur wrote:
> - Add driver for NXP FlexSPI host controller
>
> FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
> which supports two SPI channels and up to 4 external devices.
> Each channel supports Single/Dual/Quad/Octal mode data tran
Hi Lukasz,
On 09.01.19 15:56, Lukasz Majewski wrote:
> Hi Schrempf,
>
>> On 08.01.19 10:24, Yogesh Narayan Gaur wrote:
>>> - Add driver for NXP FlexSPI host controller
>>>
>>>FlexSPI is a flexsible SPI host controller [1], Chapter 30 page
>>> 1475, which supports two SPI channels and up to 4
On 04.03.19 11:58, Miquel Raynal wrote:
> Hi Frieder,
>
> Schrempf Frieder wrote on Mon, 18 Feb
> 2019 10:42:41 +:
>
>> From: Frieder Schrempf
>>
>> The information about where the manufacturer puts the bad block
>> markers inside the bad block and in
On 04.03.19 12:21, Miquel Raynal wrote:
> Hi Schrempf,
>
> Schrempf Frieder wrote on Mon, 18 Feb
> 2019 10:42:45 +:
>
>> From: Frieder Schrempf
>>
>> Currently supported bad block marker positions within the block are:
>> * in first page only
>>
From: Frieder Schrempf
Currently supported bad block marker positions within the block are:
* in first page only
* in last page only
* in first or second page
After some cleanup and preparation in patch 1 and 2, we make it
possible to set NAND_BBM_FIRSTPAGE, NAND_BBM_SECONDPAGE and
NAND_BBM_LAST
From: Frieder Schrempf
To be able to check and set bad block markers in the first and
second page of a block independently of each other, we create
separate flags for both cases.
Previously NAND_BBM_SECONDPAGE meant, that both, the first and the
second page were used. With this patch NAND_BBM_FI
From: Frieder Schrempf
Now that we have moved the information to the chip level, let's
remove all the unused flags and fields.
Signed-off-by: Frieder Schrempf
---
include/linux/mtd/bbm.h | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/include/linux/mtd/bbm.h
From: Frieder Schrempf
It is known that some ESMT SLC NANDs have been shipped
with the factory bad block markers in the first or last page
of the block, instead of the first or second page. To be on
the safe side, let's check all three locations.
Signed-off-by: Frieder Schrempf
Reviewed-by: Bor
From: Frieder Schrempf
The information about where the manufacturer puts the bad block
markers inside the bad block and in the OOB data is stored in
different places. Let's move this information to nand_chip.options
and nand_chip.badblockpos.
As this chip-specific information is not directly rel
From: Frieder Schrempf
The information about where the manufacturer puts the bad block
markers inside the bad block and in the OOB data is stored in
different places. Let's move this information to the chip struct,
as we did it for rawnand.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/nand/
From: Frieder Schrempf
Currently supported bad block marker positions within the block are:
* in first page only
* in last page only
* in first or second page
Some ESMT NANDs are known to have been shipped by the manufacturer
with bad block markers in the first or last page, instead of the
first
From: Frieder Schrempf
According to the datasheet of some Cypress SLC NANDs, the bad
block markers can be in the first, second or last page of a block.
So let's check all three locations.
Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
---
drivers/mtd/nand/raw/nand_amd.c | 8
From: Frieder Schrempf
This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip.
It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x).
It was only tested with a single data line connected, by writing and
reading random data with dd.
Signed-off-by: Frieder Schrempf
---
Cha
From: Frieder Schrempf
This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip.
It is used on i.MX6 boards by Kontron Electronics GmbH
(N60xx, N61xx).
It was only tested with a single data line connected, by writing and
reading random data with dd.
Signed-off-by: Frieder Schrempf
---
Changes
Hi Yogesh,
my comments below are mainly about things I already mentioned in my
review for v5 and about removing or simplifying some unnecessary or
complex code.
Also as I gathered from your conversation with Boris, there's still a
check for the length of the requested memory missing.
On 08.01
On 10.10.2016 17:20, Rob Herring wrote:
> On Fri, Oct 07, 2016 at 09:08:17AM +0000, Schrempf Frieder wrote:
>> This patch adds the documentation for the devicetree bindings to set
>> the volume levels.
>>
>> Signed-off-by: Frieder Schrempf
>> ---
>> Cha
Make the driver accept switching volume levels via sysfs.
This can be helpful if the beep/bell sound intensity needs
to be adapted to the environment of the device.
The volume adjustment is done by changing the duty cycle of
the pwm signal.
This patch adds the sysfs interface with 5 default volum
Thank you Rob for looking at my first kernel contribution.
I come back to it now, as I had some time to process your comments.
On 11.04.2016 17:21, Rob Herring wrote:
> On Thu, Apr 07, 2016 at 03:58:40PM +0000, Schrempf Frieder wrote:
>> Make the driver accept different volume levels
Make the driver accept switching volume levels via sysfs.
This can be helpful if the beep/bell sound intensity needs
to be adapted to the environment of the device.
The number of volume levels available and their values can
be specified via device tree (similar to pwm-backlight).
The volume adjus
This patch adds the devicetree bindings to set the volume levels
and the default volume level.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
- split into 3 separate patches
- make volume properties optional
drivers/input/misc/pwm-beeper.c | 49 ++---
1
This patch adds the documentation for the devicetree bindings to set
the volume levels.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
- split into 3 separate patches
- make volume properties optional
.../devicetree/bindings/input/pwm-beeper.txt | 22 ++
1 file c
Hi,
on our i.MX6UL/ULL boards running mainline kernels, we see an issue with
RS485 collisions on the bus. These are caused by the resetting of the
RTS signal being delayed after each transmission. The TXDC interrupt
takes several milliseconds to trigger and the slave on the bus already
starts
On 27.05.20 13:53, Russell King - ARM Linux admin wrote:
> On Wed, May 27, 2020 at 10:39:12AM +0000, Schrempf Frieder wrote:
>> Hi,
>>
>> on our i.MX6UL/ULL boards running mainline kernels, we see an issue with
>> RS485 collisions on the bus. These are caused by the res
Hi Robin,
On 20.05.20 00:05, Robin Gong wrote:
> Add NXP pca9450 pmic driver.
>
> Signed-off-by: Robin Gong
I rebased and applied on v5.8-rc3 an tested this with our i.MX8MM board
with PCA9450A. It seems to work fine. Below you can find some comments.
Thanks,
Frieder
> ---
> drivers/regula
From: Frieder Schrempf
The MX25R1635F is the smaller sibling of the MX25R3235F that is
already supported. It's only half the size (16Mb).
It was tested on the Kontron Electronics i.MX8MM SoM (N8010)
using raw read and write from and to the mtd device and
the 'flash_erase' command.
Signed-off-by
From: Frieder Schrempf
Allow external SPI ports on Kontron boards to use the spidev driver.
Signed-off-by: Frieder Schrempf
---
drivers/spi/spidev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 59e07675ef86..058b08a3767d 100644
--- a/dri
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8MM including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
Currently there are two SoM models:
* SL i.MX8MM N8010 with 1GB RAM and 8 GB eMMC
* SL i.MX8MM N8011 with 2GB RAM and 8 GB eMMC
The matching base
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8MM including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
SD card,
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
---
Documentation/devicetree/bindings/arm/fsl.yaml | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/ar
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
Changes for v3:
* None
Changes for v2:
* Merge the SoMs and baseboards N8010 and N8011 into a single
configuration (N801X).
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
S
From: Frieder Schrempf
LDO5 has two separate control registers. LDO5CTRL_L is used if the
input signal SD_VSEL is low and LDO5CTRL_H if it is high.
The current driver implementation only uses LDO5CTRL_H. To make this
work on boards that have SD_VSEL connected to a GPIO, we add support
for specify
From: Frieder Schrempf
In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.
Signed-off-by: Frieder Schrempf
---
.../dts/freescale/imx8mm-kontron-n8
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
Changes for v4:
* Rebase on next-20201001
* Enhance SoM and board description
Changes for v3:
* None
Changes for v2:
* Merge
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
S
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
S
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
Changes for v5:
* None
Changes for v4:
* Rebase on next-20201001
* Enhance SoM and board description
Changes for v3:
* None
From: Frieder Schrempf
The watchdog's WDOG_ANY signal is used to trigger a POR of the SoC,
if a soft reset is issued. As the SoM hardware connects the WDOG_ANY
and the POR signals, the watchdog node itself and the pin
configuration should be part of the common SoM devicetree.
Let's move it from t
From: Frieder Schrempf
The WDOG_ANY signal is connected to the RESET_IN signal of the SoM
and baseboard. It is currently configured as push-pull, which means
that if some external device like a programmer wants to assert the
RESET_IN signal by pulling it to ground, it drives against the high
leve
From: Uwe Kleine-König
commit 1866541492641c02874bf51f9d8712b5510f2c64 upstream
When using RS485 half duplex the Transmitter Complete irq is needed to
determine the moment when the transmitter can be disabled. When using
DMA this irq must only be enabled when DMA has completed to transfer all
da
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
S
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
Currently there are two SoM models:
* SL i.MX8MM N8010 with 1GB RAM and 8 GB eMMC
* SL i.MX8MM N8011 with 2GB RAM and 8 GB eMMC
The match
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
Changes for v2:
* Merge the SoMs and baseboards N8010 and N8011 into a single
configuration (N801X).
* Add Rob's R-b tag
---
On 05.06.19 23:35, Jeff Kletsky wrote:
> From: Jeff Kletsky
>
> These Paragon chips are very similar to other 1Gb/2Gb chips
> in terms of their layout and command timings.
>
> One notable difference is that "Minimum number of valid blocks"
> (Nvb) is 1003 per Gb, rather than the common 1004. As
Hi Peng,
On 01.05.20 14:36, Peng Fan wrote:
>> Subject: Re: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to
>> fix boot on i.MX8MM
>>
>> On 30.04.20 16:35, Lucas Stach wrote:
>>> Am Donnerstag, den 30.04.2020, 12:46 + schrieb Schrempf Fri
On 03.05.20 16:49, Adam Ford wrote:
> On Thu, Apr 30, 2020 at 7:46 AM Schrempf Frieder
> wrote:
>>
>> From: Frieder Schrempf
>>
>> According to the documents, the i.MX8M-Mini features a GC320 and a
>> GCNanoUltra GPU core. Etnaviv detects them as:
>>
&
On 06.05.20 13:45, Frieder Schrempf wrote:
> On 03.05.20 16:49, Adam Ford wrote:
>> On Thu, Apr 30, 2020 at 7:46 AM Schrempf Frieder
>> wrote:
>>>
>>> From: Frieder Schrempf
>>>
>>> According to the documents, the i.MX8M-Mini features a GC320 a
On 08.06.20 17:57, Fabio Estevam wrote:
> On Mon, Jun 8, 2020 at 12:51 PM Fabio Estevam wrote:
>>
>> On Mon, Jun 8, 2020 at 12:12 PM Schrempf Frieder
>> wrote:
>>
>>> if (port->rs485.flags & SER_RS485_ENABLED) {
>>>
From: Uwe Kleine-König
commit 1866541492641c02874bf51f9d8712b5510f2c64 upstream
When using RS485 half duplex the Transmitter Complete irq is needed to
determine the moment when the transmitter can be disabled. When using
DMA this irq must only be enabled when DMA has completed to transfer all
da
On 09.06.20 09:23, Schrempf Frieder wrote:
> From: Uwe Kleine-König
>
> commit 1866541492641c02874bf51f9d8712b5510f2c64 upstream
>
> When using RS485 half duplex the Transmitter Complete irq is needed to
> determine the moment when the transmitter can be disabled. When using
&
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