Fix the size of the buffer allocated to store the in-memory BBT.
This bug was previously hidden by a different bug, that was fixed in
d098093ba06e.
Fixes: 9c3736a3de21 ("mtd: nand: Add core infrastructure to deal with NAND
devices")
Cc:
Signed-off-by: Frieder Schrempf
---
drivers/mtd/nand/bbt.
On 27.11.18 09:22, Boris Brezillon wrote:
> On Tue, 27 Nov 2018 07:44:52 +
> Schrempf Frieder wrote:
>
>> Fix the size of the buffer allocated to store the in-memory BBT.
>> This bug was previously hidden by a different bug, that was fixed in
>> d098093ba06e.
&g
Now that the SPI memory interface was introduced by Boris, it is
possible to move drivers from mtd/spi-nor to the SPI framework in order
to use them for different type of SPI memory chips.
Patch 1 and 2 removes some unused properties from the devicetree and fixes the
reg properties to correctly re
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chips
on separate buses). And it used the order in which
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
1 file changed, 1 d
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
The new driver is already in use and this code is not compiled anymore,
so let's remove it.
Signed-off-by:
The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINE
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 -
1 file changed, 1 dele
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
.../bindings/{mtd/fsl-quadspi.txt => spi/spi-fsl-qspi.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
dif
The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'num-cs' and 'bus-num' were never read by the
driver and can be removed.
The proper
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic SPI messages.
This patch al
Hi Uwe,
I accidentally replied to the MTD list only, missing the other
recipients, earlier today. So here comes the reply again.
On 27.11.18 12:01, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Nov 27, 2018 at 10:24:19AM +, Schrempf Frieder wrote:
>> The FSL QSPI driver will
+Clément Péron
Hi Clément,
FYI, this has already been merged to nand/next.
Regards,
Frieder
On 08.11.18 09:29, Frieder Schrempf wrote:
> Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip.
>
> Signed-off-by: Frieder Schrempf
> ---
> drivers/mtd/nand/spi/Makefile | 2 +-
> dri
Hi Clément,
On 27.11.18 16:18, Clément Péron wrote:
> Hi Frieder,
>
> On Tue, 27 Nov 2018 at 16:08, Schrempf Frieder
> wrote:
>>
>> +Clément Péron
>>
>> Hi Clément,
>>
>> FYI, this has already been merged to nand/next.
> Just want to point th
On 22.11.18 07:48, PETER CHEN wrote:
>
>>
>> On Thu, Oct 18, 2018 at 09:45:04AM +0200, Frieder Schrempf wrote:
>>> Some SOCs in the i.MX6 family have a USB host controller that is only
>>> capable of the HSIC interface and has no on-board PHY.
>>>
>>> To be able to use these controllers, we need
On 27.11.18 11:24, Schrempf Frieder wrote:
> This driver is derived from the SPI NOR driver at
> mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
> of the SPI framework to issue flash memory operations to up to
> four connected flash chips (2 buses with 2 CS eac
Hi Clément,
On 27.11.18 18:02, Clément Péron wrote:
> Hi Frieder,
>
> On Tue, 27 Nov 2018 at 17:42, Schrempf Frieder
> wrote:
>>
>> Hi Clément,
>>
>> On 27.11.18 16:18, Clément Péron wrote:
>>> Hi Frieder,
>>>
>>> On Tue, 27 Nov
When reading the status of the on-chip ECC, the Toshiba chip returns
two different states for reporting corrected bitflips. We should check
for both of them.
Also the datasheet claims that the ECC bytes in OOB should not be
accessed at all, so let's also avoid any read operations on them.
One mor
Hi Miquèl,
On 18.11.18 21:47, Miquel Raynal wrote:
> Hi Schrempf,
>
> Schrempf Frieder wrote on Thu, 8 Nov 2018
> 08:32:11 +:
>
>> Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip.
>>
>> Signed-off-by: Frieder Schrempf
>> ---
>
&g
Hi Boris,
On 28.11.18 13:53, Boris Brezillon wrote:
> On Tue, 27 Nov 2018 16:41:56 +
> Schrempf Frieder wrote:
>
>>>>> +static int tc58cvg2s0h_ooblayout_ecc(struct mtd_info *mtd, int section,
>>>>> + struct mtd_oob_
When reading the status of the on-chip ECC, the Toshiba chip returns
two different states for reporting corrected bitflips. We should check
for both of them.
Also return the free OOB bytes as one contiguous area, instead of
multiple sections.
Suggested-by: Clément Péron
Signed-off-by: Frieder Sc
Hi Boris,
On 28.11.18 15:41, Boris Brezillon wrote:
> On Tue, 27 Nov 2018 07:44:52 +
> Schrempf Frieder wrote:
>
>> Fix the size of the buffer allocated to store the in-memory BBT.
>> This bug was previously hidden by a different bug, that was fixed in
>>
On 28.11.18 16:02, Boris Brezillon wrote:
> On Wed, 28 Nov 2018 14:55:45 +
> Schrempf Frieder wrote:
>
>> Hi Boris,
>>
>> On 28.11.18 15:41, Boris Brezillon wrote:
>>> On Tue, 27 Nov 2018 07:44:52 +
>>> Schrempf Frieder wrote:
>>>
Hi Yogesh,
On 29.11.18 12:38, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
>> -Original Message-----
>> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
>> Sent: Wednesday, November 28, 2018 1:58 PM
>> To: linux-...@lists.infradead.org; boris.brez
Hi Han,
On 29.11.18 17:30, Han Xu wrote:
>
>
>> -Original Message-----
>> From: Schrempf Frieder
>> Sent: Thursday, November 29, 2018 5:54 AM
>> To: Yogesh Narayan Gaur ; linux-
>> m...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
>>
On 28.11.18 16:28, Boris Brezillon wrote:
> On Wed, 28 Nov 2018 15:19:37 +
> Schrempf Frieder wrote:
>
>> On 28.11.18 16:02, Boris Brezillon wrote:
>>> On Wed, 28 Nov 2018 14:55:45 +0000
>>> Schrempf Frieder wrote:
>>>
>>>> Hi Bor
On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
> for me.
Ok, are you sure, that AHB read is working too with this patch?
You are removing the memmap_phy offset from SFAR and the SFXXAD register
values.
Hi Yogesh,
On 15.11.18 14:12, Boris Brezillon wrote:
> On Thu, 15 Nov 2018 11:43:05 +
> Schrempf Frieder wrote:
>
>> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
>>> Hi Frieder,
>>>
>>> With below patch on top of your v5, Read/Write/Erase on CS1
Hi Yogesh,
On 16.11.18 06:41, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
>> -Original Message-----
>> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
>> Sent: Thursday, November 15, 2018 7:32 PM
>> To: Yogesh Narayan Gaur
>
On 16.11.18 10:46, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
>> -Original Message-----
>> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
>> Sent: Friday, November 16, 2018 3:12 PM
>> To: Yogesh Narayan Gaur
>> Cc: Boris Brezillon ;
>&g
On 08.11.18 09:34, Boris Brezillon wrote:
> On Wed, 7 Nov 2018 16:36:13 +
> Schrempf Frieder wrote:
>
>> Hi Olof,
>>
>> On 07.11.18 17:20, Olof Johansson wrote:
>>> On Wed, Nov 7, 2018 at 6:44 AM Frieder Schrempf
>>> wrote:
>>>>
>
On 12.11.18 11:56, Boris Brezillon wrote:
> On Mon, 12 Nov 2018 10:46:45 +
> Schrempf Frieder wrote:
>
>> On 08.11.18 09:34, Boris Brezillon wrote:
>>> On Wed, 7 Nov 2018 16:36:13 +0000
>>> Schrempf Frieder wrote:
>>>
>>>> Hi O
On 13.11.18 08:04, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> Thanks for review.
>
>> -Original Message-
>> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
>> Sent: Wednesday, November 7, 2018 9:52 PM
>> To: Yogesh Narayan Gaur
The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'num-cs' and 'bus-num' were never read by the
driver and can be removed.
The proper
Now that the SPI memory interface was introduced by Boris, it is
possible to move drivers from mtd/spi-nor to the SPI framework in order
to use them for different type of SPI memory chips.
Patch 1 and 2 removes some unused properties from the devicetree and fixes the
reg properties to correctly re
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
.../bindings/{mtd/fsl-quadspi.txt => spi/spi-fsl-qspi.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Documentation/de
The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chips
on separate buses). And it used the order in which
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
The new driver is already in use and this code is not compiled anymore,
so let's remove it.
Signed-off-by:
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 -
1 file changed, 1 dele
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
1 file changed, 1 d
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINE
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic SPI messages.
This patch al
Hi Yogesh,
On 13.11.18 09:22, Yogesh Narayan Gaur wrote:
[...]
>> +
>> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
>> +spi_mem_op *op) {
>> +/*
>> + * We want to avoid needing to invalidate the cache by issueing
>> + * a reset to the AHB and Serial Flash domain, as
Hi Yogesh,
On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> I have tried v5 version of the patch and have observed that Read is failing
> for CS1.
Thanks a lot for doing the test. I really appreciate it.
> In my target 2 flash devices are connected on same bus i.e. A1 -> CS0 and
Hi Yogesh,
On 14.11.18 09:50, Frieder Schrempf wrote:
> Hi Yogesh,
>
> On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
>> Hi Frieder,
>>
>> I have tried v5 version of the patch and have observed that Read is
>> failing for CS1.
>
> Thanks a lot for doing the test. I really appreciate it.
>
>> In
On 14.11.18 11:43, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> [..]
>>>
>>> Ok, I will have a look at what could make the chip selection fail in
>>> case of AHB read.
>>
>> Could you try with this change applied:
>>
>> @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q,
>>
Hi Yogesh,
I've had a closer look at your v5. See my comments below.
On 16.11.18 12:13, Yogesh Narayan Gaur wrote:
> - Add driver for NXP FlexSPI host controller
>
> (0) What is the FlexSPI controller?
> FlexSPI is a flexsible SPI host controller which supports two SPI
> channels and up to 4
On 07.12.18 06:46, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
>> -Original Message-----
>> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
>> Sent: Tuesday, December 4, 2018 7:45 PM
>> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com;
Hi Miquèl,
On 07.12.18 09:00, Miquel Raynal wrote:
> Hi Schrempf, Clément,
>
> Schrempf Frieder wrote on Mon, 3 Dec 2018
> 08:01:38 +:
>
>> From: Frieder Schrempf
>>
>> When reading the status of the on-chip ECC, the Toshiba chip returns
>> two d
From: Frieder Schrempf
When reading the status of the on-chip ECC, the Toshiba chip returns
two different states for reporting corrected bitflips. We should check
for both of them.
Also return the free OOB bytes as one contiguous area, instead of
multiple sections.
Suggested-by: Clément Péron
Hi Han,
On 03.12.18 21:54, Han Xu wrote:
[...]
>>>
>>> Hi Schrempf, I am reviewing and testing on some i.MX platforms, please
>> hold on for a while for the result.
>>
>> Okay, thanks! I'm looking forward to see the results.
>
> Hi Schrempf, I am good with the patch set(with warning fix) and it w
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic SPI
From: Frieder Schrempf
The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'num-cs' and 'bus-num' were never read by the
driver and ca
From: Frieder Schrempf
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
.../bindings/{mtd/fsl-quadspi.txt => spi/spi-fsl-qspi.txt} | 0
1 file changed, 0 insertion
From: Frieder Schrempf
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-
From: Frieder Schrempf
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
The new driver is already in use and this code is not compiled anymore,
so let's re
From: Frieder Schrempf
The FSL QSPI driver will be moved to the SPI framework and it then
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chi
From: Frieder Schrempf
Now that the SPI memory interface was introduced by Boris, it is
possible to move drivers from mtd/spi-nor to the SPI framework in order
to use them for different type of SPI memory chips.
Patch 1 and 2 removes some unused properties from the devicetree and fixes the
reg p
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1
From: Frieder Schrempf
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chips
on separate buses). And it
+ Shawn, Sascha
On 10.12.18 17:31, Schrempf Frieder wrote:
> Hi FSL/ARM maintainers,
>
> On 10.12.18 17:26, Schrempf Frieder wrote:
>> From: Frieder Schrempf
>>
>> We have prepared a new driver for the FSL QSPI controller that works under
>> the SPI framework. T
+ linux-rt-users
On 17.12.18 11:42, Frieder Schrempf wrote:
> Hi,
>
> I have tried to boot a 4.14-Kernel with the RT-patches and
> PREEMPT_RT_FULL on an i.MX6UL board. Unfortunately the boot stalls at
> some point and never finishes.
>
> I did some bisecting and found out, that reverting this
Hi Sebastian,
On 19.12.18 12:36, Sebastian Andrzej Siewior wrote:
> On 2018-12-19 07:50:17 [+], Schrempf Frieder wrote:
>> + linux-rt-users
>>
>> On 17.12.18 11:42, Frieder Schrempf wrote:
>>> Hi,
>>>
>>> I have tried to boot a 4.14-Kernel w
On 19.12.18 14:46, Frieder Schrempf wrote:
> Hi Sebastian,
>
> On 19.12.18 12:36, Sebastian Andrzej Siewior wrote:
>> On 2018-12-19 07:50:17 [+0000], Schrempf Frieder wrote:
>>> + linux-rt-users
>>>
>>> On 17.12.18 11:42, Frieder Schrempf wrote:
>
>On Thu, Dec 13, 2018 at 09:45:04AM +0000, Schrempf Frieder wrote:
>> + Shawn, Sascha
>>
>> On 10.12.18 17:31, Schrempf Frieder wrote:
>> > Hi FSL/ARM maintainers,
>> >
>> > On 10.12.18 17:26, Schrempf Frieder wrote:
>> >> From: Frieder
Hi Han,
On 14.12.18 18:05, Han Xu wrote:
>
>
>> -Original Message-----
>> From: Schrempf Frieder
>> Sent: Tuesday, December 4, 2018 8:15 AM
>> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
>> s...@vger.kernel.org; Mar
Hi,
I have tried to boot a 4.14-Kernel with the RT-patches and
PREEMPT_RT_FULL on an i.MX6UL board. Unfortunately the boot stalls at
some point and never finishes.
I did some bisecting and found out, that reverting this change: [1],
makes the board boot correctly.
Can anyone help to come up w
From: Frieder Schrempf
Currently supported bad block marker positions within the block are:
* in first page only
* in last page only
* in first or second page
Some ESMT NANDs are known to have been shipped by the manufacturer
with bad block markers in the first or last page, instead of the
first
From: Frieder Schrempf
According to the datasheet of some Cypress SLC NANDs, the bad
block markers can be in the first, second or last page of a block.
So let's check all three locations.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/nand/raw/nand_amd.c | 8 +++-
1 file changed, 7 insert
From: Frieder Schrempf
It is known that some ESMT SLC NANDs have been shipped
with the factory bad block markers in the first or last page
of the block, instead of the first or second page. To be on
the safe side, let's check all three locations.
Signed-off-by: Frieder Schrempf
---
drivers/mtd
From: Frieder Schrempf
Currently supported bad block marker positions within the block are:
* in first page only
* in last page only
* in first or second page
Some ESMT NANDs are known to have been shipped by the manufacturer
with bad block markers in the first or last page, instead of the
first
Hi Yogesh, Boris,
On 10.12.18 11:19, Boris Brezillon wrote:
> On Mon, 10 Dec 2018 09:41:51 +
> Yogesh Narayan Gaur wrote:
>
+/* Instead of busy looping invoke readl_poll_timeout functionality.
+*/ static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
+
Hi Yogesh,
On 10.12.18 10:41, Yogesh Narayan Gaur wrote:
[...]>>> +
>>> +static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
>>> +const struct spi_mem_op *op)
>>> +{
>>> + void __iomem *base = f->iobase;
>>> + u32 lutval[4] = {};
>>> + int lutidx = 1, i;
>>> +
>>
From: Frieder Schrempf
We will move the FSL QSPI driver to the SPI framework soon. To
prepare and to make sure the full buswidth is used (as it is with
the current driver), let's add the right properties.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4
From: Frieder Schrempf
The current driver does not use the reg properties, but we will
add a new driver soon. To make sure we have a consistent scheme,
let's fix the reg properties here.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4 ++--
arch/arm/boot/dts/imx6s
From: Frieder Schrempf
The properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi-flash-chipselects' were never read by the driver
and can be removed.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arc
From: Frieder Schrempf
We have prepared a new driver for the FSL QSPI controller that works under
the SPI framework. The current devicetrees are broken because they use an
inconsistent scheme for assigning the reg properties.
As, in contrast to the current driver, the new driver will use the reg
From: Frieder Schrempf
We will move the FSL QSPI driver to the SPI framework soon. To
prepare and to make sure the full buswidth is used (as it is with
the current driver), let's add the right properties.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts |
From: Frieder Schrempf
The properties 'num-cs' and 'bus-num' were never read by the driver
and can be removed.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 1 -
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 --
arch/arm64/boot/dts/freescale/fs
Hi FSL/ARM maintainers,
On 10.12.18 17:26, Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> We have prepared a new driver for the FSL QSPI controller that works under
> the SPI framework. The current devicetrees are broken because they use an
> inconsistent scheme for as
On 20.12.18 14:59, Boris Brezillon wrote:
> On Mon, 17 Dec 2018 15:49:07 +
> Schrempf Frieder wrote:
>
>> From: Frieder Schrempf
>>
>> Currently supported bad block marker positions within the block are:
>> * in first page only
>> * in last page only
From: Frieder Schrempf
Now that the SPI memory interface was introduced by Boris, it is
possible to move drivers from mtd/spi-nor to the SPI framework in order
to use them for different type of SPI memory chips.
Patch 1 adds the driver for the Freescale QSPI controller to the SPI
framework. Toge
From: Frieder Schrempf
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
The new driver is already in use and this code is not compiled anymore,
so let's re
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |
From: Frieder Schrempf
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-
From: Frieder Schrempf
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
.../bindings/{mtd/fsl-quadspi.txt => spi/spi-fsl-qspi.txt} | 0
1 file changed, 0 insertion
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic SPI
From: Frieder Schrempf
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chips
on separate buses). And it
Hi Yogesh,
I didn't have time to look at all of the code, but nevertheless here are
some comments.
On 23.10.18 10:56, Yogesh Narayan Gaur wrote:
> - Add driver for NXP FlexSPI host controller
>
> (0) What is the FlexSPI controller?
> FlexSPI is a flexsible SPI host controller which supports t
Hi Olof,
On 07.11.18 17:20, Olof Johansson wrote:
> On Wed, Nov 7, 2018 at 6:44 AM Frieder Schrempf
> wrote:
>>
>> From: Frieder Schrempf
>>
>> The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
>> at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
>>
>> Signed-o
Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c| 1 +
drivers/mtd/nand/spi/toshiba.c | 136
include/linux/mtd/spinand.h| 1 +
4
On 08.11.18 09:41, Boris Brezillon wrote:
> On Wed, 7 Nov 2018 15:43:20 +0100
> Frieder Schrempf wrote:
>
>> From: Frieder Schrempf
>>
>> Adjust the documentation of the new SPI memory interface based
>> driver to reflect the new drivers settings.
>>
>> The "old" driver was using the "fsl,qspi-
On 08.11.18 09:37, Boris Brezillon wrote:
> On Wed, 7 Nov 2018 15:43:19 +0100
> Frieder Schrempf wrote:
>
>> From: Frieder Schrempf
>>
>> Move the documentation of the old SPI NOR driver to the place of the new
>> SPI memory interface based driver.
>>
>> Signed-off-by: Frieder Schrempf
>> ---
From: Frieder Schrempf
Currently supported bad block marker positions within the block are:
* in first page only
* in last page only
* in first or second page
After some cleanup and preparation in patches 1 to 4 we make it
possible to set NAND_BBM_FIRSTPAGE, NAND_BBM_SECONDPAGE and
NAND_BBM_LAST
From: Frieder Schrempf
To be able to check and set bad block markers in the first and
second page of a block independently of each other, we create
separate flags for both cases.
Previously NAND_BBM_SECONDPAGE meant, that both, the first and the
second page were used. With this patch NAND_BBM_FI
From: Frieder Schrempf
The information about where the manufacturer puts the bad block
markers inside the bad block and in the OOB data is stored in
different places. Let's move this information to nand_chip.options
and nand_chip.badblockpos.
As this chip-specific information is not directly rel
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