all
reset lines with index greater than 0 are considered valid.
Signed-off-by: Sander Vanheule
---
This patch was tested on a TP-Link EAP235-Wall, with an MT7621DA SoC.
The bootloader on this device would leave reset line 2 ("mcm") asserted,
which caused the internal switch to be unr
ous code style clean-ups
Changes in v2:
- Clarify structure and usage of IMR registers
- Added Linus' Reviewed-by tags
Sander Vanheule (2):
dt-bindings: gpio: Binding for Realtek Otto GPIO
gpio: Add Realtek Otto GPIO support
.../bindings/gpio/realtek,otto-gpio.yaml | 78
drivers
devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).
Signed-off-by: Sande
nd enabling the interrupt
controller may result in uncaught interrupts.
Signed-off-by: Sander Vanheule
Reviewed-by: Linus Walleij
---
.../bindings/gpio/realtek,otto-gpio.yaml | 78 +++
1 file changed, 78 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gp
On Wed, 2021-03-24 at 22:22 +0100, Sander Vanheule wrote:
> +static inline u8 read_u8_reg(void __iomem* reg, unsigned int port)
> +{
> + return ioread8(reg + port);
> +}
> +
> +static inline void write_u8_reg(void __iomem* reg, unsigned int port,
> u8 value)
> +{
Hi Andy,
Thanks for the review. I'll address the style comments in a v3. Some
further comments and discussion below.
On Wed, 2021-03-17 at 15:08 +0200, Andy Shevchenko wrote:
> On Mon, Mar 15, 2021 at 11:11 PM Sander Vanheule <
> san...@svanheule.net> wrote:
> > +
On Fri, 2021-03-19 at 19:57 +0200, Andy Shevchenko wrote:
> On Fri, Mar 19, 2021 at 5:51 PM Sander Vanheule
> wrote:
> > On Wed, 2021-03-17 at 15:08 +0200, Andy Shevchenko wrote:
> > > On Mon, Mar 15, 2021 at 11:11 PM Sander Vanheule <
> >
On Fri, 2021-03-19 at 23:24 +0200, Andy Shevchenko wrote:
> On Fri, Mar 19, 2021 at 11:20 PM Sander Vanheule <
> san...@svanheule.net> wrote:
> > On Fri, 2021-03-19 at 19:57 +0200, Andy Shevchenko wrote:
> > > On Fri, Mar 19, 2021 at 5:51 PM Sander Vanheule
> > >
aw u32 registers
- Use 'line' name for gpiochip, 'port' and 'pin' names for hardware
- Renamed DT bindings file
- Dropped fallback-only DT compatible
- Various code style clean-ups
Changes in v2:
- Clarify structure and usage of IMR registers
- Added Linus' Reviewed-by
devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).
Signed-off-by: Sande
nd enabling the interrupt
controller may result in uncaught interrupts.
Signed-off-by: Sander Vanheule
Reviewed-by: Linus Walleij
Reviewed-by: Rob Herring
---
.../bindings/gpio/realtek,otto-gpio.yaml | 78 +++
1 file changed, 78 insertions(+)
create mode 100644
Documenta
nd enabling the interrupt
controller may result in uncaught interrupts.
Signed-off-by: Sander Vanheule
Reviewed-by: Linus Walleij
Reviewed-by: Rob Herring
---
.../bindings/gpio/realtek,otto-gpio.yaml | 78 +++
1 file changed, 78 insertions(+)
create mode 100644
Documenta
le
- Various code style clean-ups
Changes in v2:
- Clarify structure and usage of IMR registers
- Added Linus' Reviewed-by tags
Sander Vanheule (2):
dt-bindings: gpio: Binding for Realtek Otto GPIO
gpio: Add Realtek Otto GPIO support
.../bindings/gpio/realtek,otto-gpio.yaml | 78 +
devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).
Signed-off-by: Sande
On Wed, 2021-03-31 at 09:49 +0200, Bartosz Golaszewski wrote:
> On Tue, Mar 30, 2021 at 7:48 PM Sander Vanheule
> wrote:
> >
> > Add support for the GPIO controller employed by Realtek in multiple
> > series of MIPS SoCs. These include the supported RTL838x and
> >
GPIO ports have been tested on a Zyxel GS1900-8 (RTL8380), and Zyxel
GS1900-48 (RTL8393). Furthermore, the GPIO ports and interrupt controller have
been tested on a Netgear GS110TPPv1 (RTL8381).
Changes in v2:
- Clarify structure and usage of IMR registers
Sander Vanheule (2):
dt-bindings: gp
devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).
Signed-off-by: Sande
nd enabling the interrupt
controller may result in uncaught interrupts.
Signed-off-by: Sander Vanheule
Reviewed-by: Linus Walleij
---
.../bindings/gpio/gpio-realtek-otto.yaml | 80 +++
1 file changed, 80 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gp
On Mon, 2021-03-15 at 16:10 +0100, Linus Walleij wrote:
> On Mon, Mar 15, 2021 at 9:26 AM Sander Vanheule
> wrote:
>
> > Realtek MIPS SoCs (platform name Otto) have GPIO controllers with
> > up to
> > 64 GPIOs, divided over two banks. Each bank has a set of registers
Hi Andy,
Thank you for clarifying your remarks. I'll support for building as a
module, and have implemented the gpio_irq_chip->init_hw() callback.
On Mon, 2021-03-29 at 13:26 +0300, Andy Shevchenko wrote:
> On Fri, Mar 26, 2021 at 11:11 PM Sander Vanheule <
> san...@svanheule.n
hip, 'port' and 'pin' names for hardware
- Renamed DT bindings file
- Dropped fallback-only DT compatible
- Various code style clean-ups
Changes in v2:
- Clarify structure and usage of IMR registers
- Added Linus' Reviewed-by tags
Sander Vanheule (2):
dt-bindings: gpio: Bi
nd enabling the interrupt
controller may result in uncaught interrupts.
Signed-off-by: Sander Vanheule
Reviewed-by: Linus Walleij
---
.../bindings/gpio/realtek,otto-gpio.yaml | 78 +++
1 file changed, 78 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gp
devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).
Signed-off-by: Sande
Hi Andy,
Replies inline below.
On Fri, 2021-03-26 at 20:19 +0200, Andy Shevchenko wrote:
> On Fri, Mar 26, 2021 at 2:05 PM Sander Vanheule
> wrote:
>
> > +config GPIO_REALTEK_OTTO
> > + bool "Realtek Otto GPIO support"
>
> Why not module?
This dr
devicetree-compatible
'realtek,otto-gpio'. This allows for quick support of GPIO banks in
which the byte order would be unknown. In this case, the port ordering
in the IMR registers may not match the reversed order in the other
registers (DCBA, and BA-DC or DC-BA).
Signed-off-by: Sande
GPIO ports have been tested on a Zyxel GS1900-8 (RTL8380M), and
Zyxel GS1900-48 (RTL8393M). Furthermore, the GPIO ports and interrupt
controller have been tested on a Netgear GS110TPPv1 (RTL8381M).
Sander Vanheule (2):
dt-bindings: gpio: Binding for Realtek Otto GPIO
gpio: Add Realtek Ot
nd enabling the interrupt
controller may result in uncaught interrupts.
Signed-off-by: Sander Vanheule
---
.../bindings/gpio/gpio-realtek-otto.yaml | 80 +++
1 file changed, 80 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gpio/gpio-realtek-otto.yam
27 matches
Mail list logo
