Patch 2 adds the pstore support for viewing the logs.
Patch 3 adds dynamic debug support to filter the register readl/writel access.
Sai Prakash Ranjan (3):
tracing: Add support for logging data to uncached buffer
pstore: Add register readl/writel tracing support
dynamic_debug: Add suppor
/msm-4.9
Modified to support pstore for viewing traces.
Signed-off-by: Sai Prakash Ranjan
---
.../bindings/reserved-memory/ramoops.txt | 7 +-
include/linux/rtb.h | 24 +++
kernel/trace/Kconfig | 7 +
kernel/trace/Makefile
data:0800d010
gic_handle_irq+0x124/0x128
Output has below 5 fields:
* Log type, Timestamp, Data from caller which is the address of
read/write, Caller ip and Caller name.
Signed-off-by: Sai Prakash Ranjan
---
fs/pstore/Kconfig | 12 +++
fs/pstore/Makefile | 1
ed_logk api to readl/writel definitions for arm64
as of now. This can be extended to arm as well later for tracing.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/include/asm/io.h | 93 +++
include/linux/dynamic_debug.h | 10
kernel/trace/Kconfig |
On 8/27/2018 9:45 PM, Steven Rostedt wrote:
On Sat, 25 Aug 2018 12:54:07 +0530
Sai Prakash Ranjan wrote:
Ftrace does not trace __raw{read,write}{b,l,w,q}() functions. I am not
sure why and how it is filtered out because I do not see any notrace
flag in those functions, maybe that whole
On 8/28/2018 9:32 PM, Steven Rostedt wrote:
On Tue, 28 Aug 2018 18:47:33 +0530
Sai Prakash Ranjan wrote:
On 8/27/2018 9:45 PM, Steven Rostedt wrote:
On Sat, 25 Aug 2018 12:54:07 +0530
Sai Prakash Ranjan wrote:
Ftrace does not trace __raw{read,write}{b,l,w,q}() functions. I am not
sure
On 8/7/2018 10:27 PM, Will Deacon wrote:
On Fri, Aug 03, 2018 at 07:58:44PM +0530, Sai Prakash Ranjan wrote:
Introduce dynamic debug filtering mechanism to register
tracing as dynamic_rtb() which will reduce a lot of
overhead otherwise of tracing all the register reads/writes
in all files.
Now
nted from being flooded with some I/O operations.
This is based on RTB driver in CAF. Link below:
* https://source.codeaurora.org/quic/la/kernel/msm-4.9
Modified to support pstore for viewing traces.
Signed-off-by: Sai Prakash Ranjan
---
.../bindings/reserved-memory/ramoops.txt | 7 +-
/write{b,l,w,q} instead of readl/writel since we will be tracing all
Sai Prakash Ranjan (3):
tracing: Add support for logging data to uncached buffer
pstore: Add register read/write{b,w,l,q} tracing support
dynamic_debug: Add support for dynamic register trace
.../bindings/reserved-memory
data:0800d010
gic_handle_irq+0x124/0x128
Output has below 5 fields:
* Log type, Timestamp, Data from caller which is the address of
read/write{b,w,l,q}, Caller ip and Caller name.
Signed-off-by: Sai Prakash Ranjan
---
fs/pstore/Kconfig | 12 +++
fs/pstore/Makefile | 1 +
fs
ore pstore /sys/fs/pstore
# cat /sys/fs/pstore/rtb-ramoops-0
[LOGK_WRITE] ts:1373030419 data:0d5065a4
qcom_smsm_probe+0x51c/0x668
[LOGK_WRITE] ts:1373360576 data:0d506608
qcom_smsm_probe+0x51c/0x668
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/includ
On 8/24/2018 8:59 PM, Kees Cook wrote:
On Fri, Aug 24, 2018 at 7:45 AM, Sai Prakash Ranjan
wrote:
read/write{b,w,l,q} are typically used for reading from memory
mapped registers, which can cause hangs if accessed
unclocked. Tracing these events can help in debugging
various issues faced during
Hi Bjorn,
On 11/12/2018 1:35 PM, Bjorn Andersson wrote:
The AOSS QMP genpd provider implements control over power-related
resources related to low-power state associated with the remoteprocs in
the system as well as control over a set of clocks related to debug
hardware in the SoC.
Signed-off-b
Hi Bjorn,
On 11/12/2018 1:35 PM, Bjorn Andersson wrote:
The AOSS QMP genpd provider implements control over power-related
resources related to low-power state associated with the remoteprocs in
the system as well as control over a set of clocks related to debug
hardware in the SoC.
Signed-off-b
On 11/13/2018 3:14 PM, Srinivas Kandagatla wrote:
Hi Sai,
On 25/10/18 15:36, saiprakash.ran...@codeaurora.org wrote:
"If I disable dma node and LS-UART0, then I don't see any crash and
ftrace also works fine"
And one more observation is that even without ftrace cmdline, if I use
earlycon and
3.164853] sci_init+0x24/0x3c
<4>[3.164859] do_one_initcall+0x54/0x248
<4>[3.164866] kernel_init_freeable+0x210/0x378
<4>[3.164872] kernel_init+0x18/0x118
<4>[3.164878] ret_from_fork+0x10/0x1c
<0>[3.164884] Code: aa1e03e0 8b2142
On 11/16/2018 9:09 AM, Viresh Kumar wrote:
On Thu, Nov 15, 2018 at 4:23 PM Srinivas Kandagatla
wrote:
Yes, this is not the solution, but it proves that the hand-off between
booloaders and kernel is the issue.
In general there is wider issue with resources hand-off between
bootloader and kerne
On 11/16/2018 4:23 PM, Viresh Kumar wrote:
Hi,
On 16-11-18, 16:16, Sai Prakash Ranjan wrote:
iface clock is shared with other drivers, which may reconfigure
this before the serial driver comes up. This may lead to
crashes like the one below where GCC_BLSP1_AHB_CLK is same across
multiple
about
instrumentation in arch code and was about to respin a v2 patch. I have
replied inline, let me know if any more corrections or improvements can
be done. I would also like if Kees or someone from pstore could comment
on patch 2.
On Fri, 3 Aug 2018 19:58:42 +0530
Sai Prakash Ranjan
On 10/9/2018 4:10 AM, Joel Fernandes wrote:
On Mon, Oct 08, 2018 at 10:36:59AM -0400, Steven Rostedt wrote:
On Mon, 8 Oct 2018 19:46:15 +0530
Sai Prakash Ranjan wrote:
Hi Joel,
Sorry for the long delay in updating this thread.
But I just observed one weird behaviour in ftrace-ramoops when I
Hi,
On dragonboard 410c, with "ftrace=function" boot args, the console
output slows down and board resets without any backtrace as below. This
is tested on latest kernel and seems to exist even in older kernels as well.
[2.949164] EINJ: ACPI disabled.
[3.133001] Serial: 8250/16550 dri
On 10/16/2018 5:14 PM, Greg Kroah-Hartman wrote:
On Tue, Oct 16, 2018 at 05:08:25PM +0530, Sai Prakash Ranjan wrote:
Hi,
On dragonboard 410c, with "ftrace=function" boot args, the console output
slows down and board resets without any backtrace as below. This is tested
on latest
On 10/16/2018 8:59 PM, Steven Rostedt wrote:
On Tue, 16 Oct 2018 17:08:25 +0530
Sai Prakash Ranjan wrote:
Hi,
On dragonboard 410c, with "ftrace=function" boot args, the console
output slows down and board resets without any backtrace as below. This
is tested on latest kernel an
On 10/16/2018 10:27 PM, Steven Rostedt wrote:
OK, can you add to the command line:
ftrace=function ftrace_filter=*schedule*
to see if it's a specific function that may be causing the issue (but
hopefully it's not one of the scheduling functions that caused it).
Target boots fine with this
On 10/16/2018 11:18 PM, Steven Rostedt wrote:
On Tue, 16 Oct 2018 23:06:24 +0530
Sai Prakash Ranjan wrote:
On 10/16/2018 10:27 PM, Steven Rostedt wrote:
OK, can you add to the command line:
ftrace=function ftrace_filter=*schedule*
to see if it's a specific function that may be ca
On 10/16/2018 11:46 PM, Steven Rostedt wrote:
[ Removed ivan.iva...@linaro.org due to getting mail delivery errors ]
On Tue, 16 Oct 2018 23:35:00 +0530
Sai Prakash Ranjan wrote:
Ok got it, this sounds fun. I'll give it a try.
Awesome, I'm looking forward to seeing what you co
On 10/17/2018 12:11 AM, Steven Rostedt wrote:
On Tue, 16 Oct 2018 23:55:14 +0530
Sai Prakash Ranjan wrote:
On 10/16/2018 11:46 PM, Steven Rostedt wrote:
[ Removed ivan.iva...@linaro.org due to getting mail delivery errors ]
On Tue, 16 Oct 2018 23:35:00 +0530
Sai Prakash Ranjan wrote
On 10/17/2018 12:33 AM, Steven Rostedt wrote:
On Wed, 17 Oct 2018 00:31:03 +0530
Sai Prakash Ranjan wrote:
Haa seems like you are right! With "ftrace=function
ftrace_filter=msm_read" , I can trigger the crash, but
sadly "ftrace_notrace=msm_read" also crashes.
So t
On 10/17/2018 12:46 AM, Steven Rostedt wrote:
On Tue, 16 Oct 2018 15:15:16 -0400
Steven Rostedt wrote:
I'd like to see the full command line as well. I bet if you remove the
qcom,msm-uartdm from the command line, and had just ftrace=function, it
may also boot fine too. Can you try that?
Note
On 10/17/2018 2:21 AM, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2018-10-16 12:35:57)
On 10/17/2018 12:45 AM, Steven Rostedt wrote:
On Wed, 17 Oct 2018 00:36:05 +0530
Sai Prakash Ranjan wrote:
On 10/17/2018 12:33 AM, Steven Rostedt wrote:
On Wed, 17 Oct 2018 00:31:03 +0530
Sai
On 10/17/2018 3:43 PM, Joel Fernandes wrote:
Hi Kees,
On Tue, Oct 16, 2018 at 10:02:53AM -0700, Kees Cook wrote:
On Tue, Oct 16, 2018 at 8:29 AM, Steven Rostedt wrote:
On Tue, 16 Oct 2018 17:08:25 +0530
Sai Prakash Ranjan wrote:
One more thing is for pstore dmesg-ramoops, I had to change
On 10/17/2018 4:39 AM, Joel Fernandes wrote:
On Tue, Oct 16, 2018 at 05:08:25PM +0530, Sai Prakash Ranjan wrote:
Hi,
On dragonboard 410c, with "ftrace=function" boot args, the console output
slows down and board resets without any backtrace as below. This is tested
on latest kernel
On 10/17/2018 5:08 PM, Sai Prakash Ranjan wrote:
What do you think about the (untested) patch below? It seems to me
that it
should solve the issue of missing early crash dumps, but I have not
tested it
yet. Sai, would you mind trying it out and let me know if you can see the
early crash
done at the same time?
Otherwise looks good to me,
Reviewed-by: Joel Fernandes (Google)
Tested this on top of Joel's patch, works fine on getting early crash
pstore dmesg logs, thanks.
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 9/26/2018 3:16 PM, Sai Prakash Ranjan wrote:
On 9/26/2018 2:55 AM, Joel Fernandes wrote:
On Sat, Sep 8, 2018 at 1:28 PM Sai Prakash Ranjan
wrote:
Add the kernel command line tp_pstore option that will have
tracepoints go to persistent ram buffer as well as to the
trace buffer for further
On 10/18/2018 8:03 AM, Steven Rostedt wrote:
On Wed, 17 Oct 2018 00:36:05 +0530
Sai Prakash Ranjan wrote:
On 10/17/2018 12:33 AM, Steven Rostedt wrote:
On Wed, 17 Oct 2018 00:31:03 +0530
Sai Prakash Ranjan wrote:
Haa seems like you are right! With "ftrace=function
ftrace_f
On 10/19/2018 9:47 AM, Joel Fernandes wrote:
On Thu, Oct 18, 2018 at 09:17:06AM -0400, Steven Rostedt wrote:
On Thu, 18 Oct 2018 10:51:18 +0530
Sai Prakash Ranjan wrote:
So something else is causing an issue besides just msm_read.
Can you do an objdump -dr of the entire vmlinux binary and
On 10/19/2018 7:21 PM, Steven Rostedt wrote:
On Fri, 19 Oct 2018 12:24:05 +0530
Sai Prakash Ranjan wrote:
Anyone see any problems here?
This seems sane to me, he says in the other thread that he put 'notrace' to
the msm serial functions (which AIUI should prevent ftrace instrument
On 10/20/2018 10:55 AM, Joel Fernandes wrote:
On Sun, Sep 09, 2018 at 01:57:01AM +0530, Sai Prakash Ranjan wrote:
Hi,
This patch series adds Event tracing support to pstore and is continuation
to the RFC patch introduced to add a new tracing facility for register
accesses called Register Trace
On 10/20/2018 9:57 PM, Joel Fernandes wrote:
On Sat, Oct 20, 2018 at 12:02:37PM +0530, Sai Prakash Ranjan wrote:
On 10/20/2018 10:55 AM, Joel Fernandes wrote:
On Sun, Sep 09, 2018 at 01:57:01AM +0530, Sai Prakash Ranjan wrote:
Hi,
This patch series adds Event tracing support to pstore and is
On 10/21/2018 9:16 AM, Sai Prakash Ranjan wrote:
On 10/20/2018 9:57 PM, Joel Fernandes wrote:
On Sat, Oct 20, 2018 at 12:02:37PM +0530, Sai Prakash Ranjan wrote:
On 10/20/2018 10:55 AM, Joel Fernandes wrote:
On Sun, Sep 09, 2018 at 01:57:01AM +0530, Sai Prakash Ranjan wrote:
Hi,
This patch
On 9/9/2018 1:57 AM, Sai Prakash Ranjan wrote:
Currently pstore has function trace support which can be
used to get the function call chain with limited data.
Event tracing has extra data which is useful to debug wide
variety of issues and is heavily used across the kernel.
Adding this support
On 9/16/2018 7:25 PM, Joel Fernandes wrote:
Sorry for the top post. I've been wanting to do this as well for some
time. It's quite useful. I am out of office this week and away from work
machine. I will take a look at your patches next week once I'm back at
work. Thanks.
Best,
J
Cool, than
On 9/17/2018 11:15 AM, Rob Herring wrote:
On Sun, 9 Sep 2018 01:57:02 +0530, Sai Prakash Ranjan wrote:
Add an optional property called event-size to reserve
log buffer for trace events.
Signed-off-by: Sai Prakash Ranjan
---
.../devicetree/bindings/reserved-memory/ramoops.txt| 7
On 9/17/2018 8:24 PM, Kees Cook wrote:
On Sun, Sep 16, 2018 at 6:55 AM, Joel Fernandes wrote:
On Sun, Sep 16, 2018, 12:08 AM Sai Prakash Ranjan
wrote:
On 9/9/2018 1:57 AM, Sai Prakash Ranjan wrote:
Currently pstore has function trace support which can be
used to get the function call chain
On 9/17/2018 11:08 PM, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2018-09-11 03:46:01)
On 9/9/2018 1:57 AM, Sai Prakash Ranjan wrote:
+void notrace pstore_event_call(struct trace_event_buffer *fbuffer)
+{
+ struct trace_iterator *iter;
+ struct trace_seq *s;
+ struct
an explicit initialization is not needed.
Reported-by: Sai Prakash Ranjan
Suggested-by: Evan Green
Signed-off-by: Matthias Kaehlcke
---
drivers/tty/sysrq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index 06ed20dd0
On 9/18/2018 4:34 AM, Steven Rostedt wrote:
On Sun, 16 Sep 2018 12:37:52 +0530
Sai Prakash Ranjan wrote:
Hi,
Anyone here?
You also just caught me from coming back from a trip. I'm looking at
your patches now.
-- Steve
Thanks Steve, I just thought you guys might have missed the
are initialized
with zero/NULL in C, therefore an explicit initialization is not needed.
Reported-by: Sai Prakash Ranjan
Suggested-by: Evan Green
Signed-off-by: Matthias Kaehlcke
---
drivers/tty/sysrq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/sysrq
On 9/18/2018 5:09 AM, Steven Rostedt wrote:
On Sun, 9 Sep 2018 01:57:06 +0530
Sai Prakash Ranjan wrote:
The new asm-generic/io-instrumented.h will keep arch code
clean and separate from instrumented version which traces
io register accesses. This instrumented header can later
be included in
On 9/18/2018 12:50 PM, Greg Kroah-Hartman wrote:
On Tue, Sep 18, 2018 at 12:28:39PM +0530, Sai Prakash Ranjan wrote:
On 9/18/2018 11:41 AM, Jiri Slaby wrote:
On 09/17/2018, 11:33 PM, Matthias Kaehlcke wrote:
sysrq_handle_crash() dereferences a NULL pointer on purpose to force
an exception
On 9/18/2018 2:47 PM, Greg Kroah-Hartman wrote:
On Tue, Sep 18, 2018 at 02:35:02PM +0530, Sai Prakash Ranjan wrote:
On 9/18/2018 12:50 PM, Greg Kroah-Hartman wrote:
On Tue, Sep 18, 2018 at 12:28:39PM +0530, Sai Prakash Ranjan wrote:
On 9/18/2018 11:41 AM, Jiri Slaby wrote:
On 09/17/2018, 11
On 9/18/2018 5:17 PM, Will Deacon wrote:
On Tue, Sep 18, 2018 at 12:40:57PM +0530, Sai Prakash Ranjan wrote:
On 9/18/2018 5:09 AM, Steven Rostedt wrote:
On Sun, 9 Sep 2018 01:57:06 +0530
Sai Prakash Ranjan wrote:
The new asm-generic/io-instrumented.h will keep arch code
clean and separate
On 9/18/2018 5:04 AM, Steven Rostedt wrote:
It looks like pstore_event_call() gets called from a trace event. You
can't call kmalloc() from one. One thing is that kmalloc has
tracepoints itself. You trace those you just entered an infinite loop.
Ok will remove it in v2. But any alternative w
On 9/19/2018 2:14 AM, Steven Rostedt wrote:
On Tue, 18 Sep 2018 23:22:48 +0530
Sai Prakash Ranjan wrote:
On 9/18/2018 5:04 AM, Steven Rostedt wrote:
It looks like pstore_event_call() gets called from a trace event. You
can't call kmalloc() from one. One thing is that kmalloc has
tracep
As per interrupt documentation for SM8250 SoC, the polarity
for level triggered PMU interrupt is low, fix this.
Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1
Fix PMU interrupt polarity for SM8250 and SM8350 SoCs and the timer
interrupt property for SM8250 SoC.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
arm64: dts: qcom: sm8250
timer interrupt to be EL2 physical
timer interrupt (10 in this case).
Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.
Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350
SoC")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2
On 4/16/2019 8:30 PM, Alexander Shishkin wrote:
Sai Prakash Ranjan writes:
From: Mulu He
Bitmap allocation works on array of unsigned longs and
for stm master allocation when the number of software
channels is 32, 4 bytes are allocated and there is a out of
bound access at the first 8 bytes
Add ETM PIDs for Cortex-A55 and Cortex-A78 to the list of
supported ETMs.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers/hwtracing
to linaro coresight repo,
https://git.linaro.org/kernel/coresight.git, I have now updated
the remote to a proper kernel.org coresight repo and will post
the updated patchset.
Thanks,
Sai
On Fri, 12 Feb 2021 at 17:23, Sai Prakash Ranjan
wrote:
Add ETM PIDs for Cortex-A55 and Cortex-A78 to
Add ETM PID for Cortex-A78 to the list of supported ETMs.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v2:
* Rebased on top of coresight/next from kernel.org coresight repo.
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
Hi,
Thanks for taking a look, comments inline.
On 2021-02-23 01:44, Doug Anderson wrote:
Hi,
On Fri, Jan 29, 2021 at 11:08 AM Sai Prakash Ranjan
wrote:
@@ -1202,6 +1207,13 @@ void etm4_config_trace_mode(struct etmv4_config
*config)
/* excluding kernel AND user space doesn't
Hi Peter,
On 2021-02-02 11:41, Sai Prakash Ranjan wrote:
Hi Peter,
On 2021-02-01 19:11, Peter Zijlstra wrote:
On Mon, Feb 01, 2021 at 01:11:04PM +0530, Sai Prakash Ranjan wrote:
Ok I suppose you mean CONFIG_SECURITY_LOCKDOWN_LSM? But I don't see
how this new config has to depend on
ed-by: Al Grant
Tested-by: Denis Nikitin
Link:
https://lore.kernel.org/lkml/20201015124522.1876-1-saiprakash.ran...@codeaurora.org/
Signed-off-by: Sai Prakash Ranjan
---
init/Kconfig | 12
kernel/events/core.c | 6 ++
2 files changed, 18 insertions(+)
diff --git a/init
Prakash Ranjan
---
tools/perf/util/evsel.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index c26ea82220bd..09cc0349f883 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2630,7 +2630,8 @@ int
xcluding kernel mode for
ARM Coresight ETM{4,3}XX sysfs mode using the newly introduced generic
config.
[1] https://lwn.net/Articles/796866/
Sai Prakash Ranjan (4):
perf/core: Add support to exclude kernel mode instruction tracing
perf evsel: Print warning for excluding kernel mode instruct
kernel and
userspace tracing enabled by default.
Tested-by: Denis Nikitin
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 +-
.../hwtracing/coresight/coresight-etm4x-sysfs.c| 3 ++-
2 files changed, 15 insertions(+), 2 deletions(-)
diff
kernel and
userspace tracing enabled by default.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm3x-core.c | 11 +++
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 3 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing
On 2021-01-31 22:33, Jorge Ramirez-Ortiz, Foundries wrote:
On 28/01/21, Sai Prakash Ranjan wrote:
On 2021-01-28 13:49, Jorge Ramirez-Ortiz, Foundries wrote:
> On 26/01/21, Sai Prakash Ranjan wrote:
> > As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1)
> > of w
Hi Peter,
On 2021-01-30 01:00, Peter Zijlstra wrote:
On Sat, Jan 30, 2021 at 12:35:10AM +0530, Sai Prakash Ranjan wrote:
Here the idea is to protect such important information from all users
including root users since root privileges does not have to mean full
control over the kernel [1] and
Hi Peter,
On 2021-02-01 19:11, Peter Zijlstra wrote:
On Mon, Feb 01, 2021 at 01:11:04PM +0530, Sai Prakash Ranjan wrote:
Ok I suppose you mean CONFIG_SECURITY_LOCKDOWN_LSM? But I don't see
how this new config has to depend on that? This can work independently
whether complete lockdo
On 2021-02-01 23:50, Jordan Crouse wrote:
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
>
> On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-01-29 14:35, Will Deacon wrote:
> > >
On 2021-02-01 23:50, Jordan Crouse wrote:
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
>
> On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-01-29 14:35, Will Deacon wrote:
> > >
On 2021-02-04 03:16, Will Deacon wrote:
On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
On 2021-02-01 23:50, Jordan Crouse wrote:
> On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> > On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
> > > On Fr
size=4096 unmapped_size=4096
After:
map: IOMMU: dev=1d84000.ufshc iova=0x000fffa88000
paddr=0x0001063db000 size=4096
unmap: IOMMU: dev=1d84000.ufshc iova=0x000fffa88000 size=4096
unmapped_size=4096
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/iommu.c| 8
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts
This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP
and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
[1] https://lore.kernel.org/patchwork/cover/1379842/
Sai Prakash Ranjan (9):
dt-bindings: arm: msm: Add LLCC for SC7280
Add LLCC configuration data for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 8403a77b59fe..15a36dcab990 100644
--- a
Add LLCC compatible for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
b/Documentation/devicetree/bindings/arm/msm/qcom
Add the IPCC DT node which is used to send and receive IPC
signals with remoteprocs for SC7280 SoC.
Cc: Manivannan Sadhasivam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 65c1e0f2fb56
Add SC7280 AOSS QMP compatible to the list of possible bindings.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
b/Documentation
Add IPCC compatible for SC7280 SoC.
Cc: Manivannan Sadhasivam
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
b/Documentation/devicetree
Add AOSS QMP support for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/qcom_aoss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 53acb9423bd6..934fcc4d2b05 100644
--- a/drivers/soc/qcom/qcom_aoss.c
Add coresight components found on SC7280 SoC.
Cc: Mathieu Poirier
Cc: Suzuki K Poulose
Cc: Mike Leach
Cc: Leo Yan
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 489 +++
1 file changed, 489 insertions(+)
diff --git a/arch/arm64/boot/dts
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU compatible
iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier
drivers/iommu
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
---
Its either this or we add a new compatible
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
On 2021-02-26 01:11, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64
On 2021-02-26 01:07, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Reviewed-by: Stephen Boyd
On 2021-02-25 23:36, Jordan Crouse wrote:
On Thu, Feb 25, 2021 at 03:54:10PM +0530, Sai Prakash Ranjan wrote:
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such a
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Changes in v2:
* Add a comment to make sure this order is not changed in future (Jordan)
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qco
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current logic picks one of:
> 1) is the compatible mentioned in qcom_smmu_impl_of_match[]
> 2) is the compatible an adreno
> 3) no quirks needed
>
> The change flips the order of the
On 2021-02-27 00:16, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
On 2021-02-26 01:11, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
>> Add a DT node for the AOSS QMP on SC7280 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan
On 2021-02-27 00:15, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
On 2021-02-26 01:07, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
>> Add a DT node for Last level cache (aka. system cache)
>> controller which provides contro
Add a flag to check whether TMC ETR/ETF is enabled or not.
This is later used in shutdown callback to determine if
we require to disable ETR/ETF.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-tmc.c | 2 ++
drivers/hwtracing/coresight/coresight-tmc.h | 2 ++
2 files
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