From: Richard Gong
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
configured from HPS, there needs to be a way for HPS to notify SDM the
location and size of the configuration data. Then SDM will
From: Richard Gong
Add a device tree binding for the Intel Stratix10 service layer driver
Signed-off-by: Richard Gong
---
.../devicetree/bindings/misc/intel-service.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc
From: Richard Gong
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware
which does the FPGA configuration, QSPI, Crypto and warm reset.
When the FPGA is configured from HPS, there needs to be a way
From: Richard Gong
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). SDM is the
hardware which does the FPGA configuration, QSPI, Crypto and warm reset.
When the FPGA is configured from HPS, there needs to be a way
On 01/30/2018 10:57 AM, Rob Herring wrote:
On Tue, Jan 23, 2018 at 01:25:02PM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add a device tree binding for the Intel Stratix10 service layer driver
Signed-off-by: Richard Gong
---
.../devicetree/bindings/misc/intel
Hi Greg,
Many thanks for your reviews.
On 01/25/2018 10:53 AM, Greg KH wrote:
On Thu, Jan 25, 2018 at 10:39:03AM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device
From: Richard Gong
This is the 11th submission of Intel Stratix10 service layer and FPGA
manager driver patches. Starting from 10th submission Stratix10 service
layer driver .c file is moved to drivers/firmware, header files is moved
to include/linux/firmware/intel. And other firmware interface
From: Alan Tull
Add the Stratix10 FPGA manager and a FPGA region to the
device tree.
Signed-off-by: Alan Tull
Signed-off-by: Richard Gong
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
v4: s/fpga-mgr@0/fpga-mgr/ to remove
From: Richard Gong
Add a device tree binding for the Intel Stratix10 service layer driver
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
Reviewed-by: Rob Herring
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-sv
From: Richard Gong
Add new file stratix10-svc.rst
Add stratix10-svc.rst to driver-api/index.rst
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v5: this patch is added in patch set version 5
---
Documentation/driver-api/index.rst | 1 +
Documentation/driver-api/stratix10
From: Richard Gong
This is the 5th submission of Intel stratix10 service layer patches. Intel
Stratix10 FPGA manager, which is 1st Stratix10 service layer client, is
included in this submission.
Stratix10 service layer patches have been reviewed internally by Alan Tull
and other colleagues at
From: Alan Tull
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel Service Driver which
does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.
Signed-off-by: Alan Tull
Signed-off-by: Richard
From: Richard Gong
Enable fpga framework, Stratix 10 SoC FPGA manager and Stratix10
Service Layer
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
v3: no change
v4: s/CONFIG_INTEL_SERVICE/CONFIG_STRATIX10_SERVICE/
add
From: Richard Gong
Some features of the Intel Stratix10 SoC require a level of privilege
higher than the kernel is granted. Such secure features include
FPGA programming. In terms of the ARMv8 architecture, the kernel runs
at Exception Level 1 (EL1), access to the features requires
Exception
From: Alan Tull
Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
Signed-off-by: Alan Tull
Signed-off-by: Richard Gong
Reviewed-by: Rob Herring
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
v4: s/fpga-mgr@0/fpga
From: Richard Gong
Add Intel Stratix10 service layer to the device tree
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
v3: No change
v4: s/service driver
From: Richard Gong
This is the 10th submission of Intel Stratix10 service layer and FPGA
manager driver patches. In this submission I have moved Stratix10 service
layer driver .c file to drivers/firmware and header files to
include/linux/firmware/intel. I have added Stratix10 service layer
From: Richard Gong
Add Intel Stratix10 service layer to the device tree
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
v2: change to put service layer driver node under the firmware node
change compatible to "intel, stratix10-svc"
v3: no ch
From: Richard Gong
Add new file stratix10-svc.rst
Add stratix10-svc.rst to driver-api/index.rst
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v5: this patch is added in patch set version 5
v6: no change
v7: no change
---
Documentation/driver-api/index.rst | 1
From: Alan Tull
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel Service Driver which
does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.
Signed-off-by: Alan Tull
Signed-off-by: Richard
From: Alan Tull
Add the Stratix10 FPGA manager and a FPGA region to the
device tree.
Signed-off-by: Alan Tull
Signed-off-by: Richard Gong
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
v4: s/fpga-mgr@0/fpga-mgr/ to remove
Hi Tom,
On 2/13/21 9:44 AM, Tom Rix wrote:
On 2/9/21 2:20 PM, richard.g...@linux.intel.com wrote:
From: Richard Gong
Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it to 0, which
aligns with the firmware settings.
Fixes: 36847f9e3e56 ("firmware: stratix10-svc: correct rec
From: Richard Gong
Add Intel Stratix10 service layer to the device tree
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
---
arch/arm64/boot/
From: Alan Tull
Add the Stratix10 FPGA manager and a FPGA region to the
device tree.
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/bo
From: Alan Tull
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel Service Driver which
does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.
Signed-off-by: Alan Tull
---
v2: this patch is ad
From: Richard Gong
Add a device tree binding for the Intel Stratix10 service layer driver
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
---
.../binding
From: Alan Tull
Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
---
.../devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 10 ++
1 file changed, 10 insertions(+)
create mode 1006
From: Richard Gong
Enable fpga framework, Stratix 10 SoC FPGA manager, and Intel Service Layer
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
---
arch/arm64/configs/defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a
From: Richard Gong
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). SDM is the
hardware which does the FPGA configuration, QSPI, Crypto and warm reset.
When the FPGA is configured from HPS, there needs to be a way
From: Richard Gong
This is the 2nd submission of Intel service layer patches. Intel Stratix10
FPGA manager, which is 1st service layer client, is included in this submission.
Service layer patches have been reviewed internally by Alan Tull and other
colleagues at Intel.
Intel Stratix10 SoC is
From: Richard Gong
Add a device tree binding for the Intel Stratix10 service layer driver
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
v3:
From: Richard Gong
This is the 3rd submission of Intel service layer patches. Intel Stratix10
FPGA manager, which is 1st service layer client, is included in this submission.
Service layer patches have been reviewed internally by Alan Tull and other
colleagues at Intel.
Intel Stratix10 SoC is
From: Richard Gong
Add Intel Stratix10 service layer to the device tree
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
v3: No change
---
arch/arm64/boot/
From: Richard Gong
Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
processor system (HPS) and Secure Device Manager (SDM). SDM is the
hardware which does the FPGA configuration, QSPI, Crypto and warm reset.
In order to configure the FPGA from HPS, there needs to be a
From: Richard Gong
Enable fpga framework, Stratix 10 SoC FPGA manager, and Intel Service Layer
Signed-off-by: Richard Gong
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
v3: no change
---
arch/arm64/configs/defconfig | 5 +
1 file changed, 5 insertions
From: Alan Tull
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel Service Driver which
does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.
Signed-off-by: Alan Tull
---
v2: this patch is ad
From: Alan Tull
Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
---
.../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 17 +
From: Alan Tull
Add the Stratix10 FPGA manager and a FPGA region to the
device tree.
Signed-off-by: Alan Tull
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12
1 fi
From: Richard Gong
Enable FPGA framework, Intel Stratix10 SoC FPGA manager, Stratix10
service layer, and Altera Freeze Bridge drivers.
Intel Stratix10 service layer driver was added with commit 7ca5ce896524
("firmware: add Intel Stratix10 service layer driver").
Intel Stratix10 ser
From: Richard Gong
Add a log for user to know FPGA configuration is successful
Signed-off-by: Richard Gong
---
drivers/fpga/fpga-mgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index c386681..559e046 100644
--- a/drivers/fpga/fpga
Hi Moritz,
On 4/3/19 9:20 AM, Moritz Fischer wrote:
Hi Richard,
On Tue, Apr 02, 2019 at 05:25:43PM -0500, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add a log for user to know FPGA configuration is successful
Signed-off-by: Richard Gong
---
drivers/fpga/fpga-mgr.c | 1 +
1
From: Richard Gong
Add a device tree binding for the Intel Stratix10 remote system
update (RSU) driver
Signed-off-by: Richard Gong
Reviewed-by: Alan Tull
---
.../bindings/firmware/intel,stratix10-rsu.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644
From: Richard Gong
This is the 1st submission of Intel Stratix10 remote system update (RSU)
driver, which includes 6 patches below:
patch #1 - extend Intel Stratix10 service layer to support RSU
notify feature.
patch #2 - add Intel Stratix10 remote system
From: Richard Gong
Extend Intel Stratix10 service layer to support RSU notify feature.
RSU is used to provide our customers with protection against loading bad
bitstream onto their devices when those devices are booting from flash
RSU notify provides users with an API to notify the firmware of
From: Richard Gong
Add Intel Stratix10 remote system update to the device tree
Signed-off-by: Richard Gong
Reviewed-by: Alan Tull
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
b
From: Richard Gong
The Intel Remote System Update (RSU) driver exposes interfaces access
through the Intel Service Layer to user space via sysfs interface.
The RSU interfaces report and control some of the optional RSU features
on Intel Stratix 10 SoC.
The RSU feature provides a way for
From: Richard Gong
Add myself as maintainer for the newly created Intel Stratix10
firmware drivers.
Signed-off-by: Richard Gong
Reviewed-by: Alan Tull
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4cf3cbf..d7054f5 100644
--- a
From: Richard Gong
Describe Intel Stratix10 Remote System Update (RSU) device attributes
Signed-off-by: Richard Gong
Reviewed-by: Alan Tull
---
.../testing/sysfs-devices-platform-stratix10-rsu | 78 ++
1 file changed, 78 insertions(+)
create mode 100644
Documentation
From: Richard Gong
Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it to 0, which
aligns with the firmware settings.
Cc: # 5.9+
Fixes: 36847f9e3e56 ("firmware: stratix10-svc: correct reconfig flag and
timeout values")
Signed-off-by: Richard Gong
---
v3: correct the missi
Hi Moritz,
On 2/1/21 10:27 PM, Moritz Fischer wrote:
On Mon, Feb 01, 2021 at 09:21:58AM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add authenticate-fpga-config property for FPGA bitstream authentication,
which makes sure a signed bitstream has valid signatures.
Signed
From: Richard Gong
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA manager driver, one of Intel service layer
driver's client, can decide whether to handle the newly added bitstream
authentication function based on the retrieved fir
From: Richard Gong
Add authenticate-fpga-config property to support FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures.
Signed-off-by: Richard Gong
---
v4: add additional checks to make sure *only* authenticate
v3: no change
v2: changed in alphabetical
From: Richard Gong
Add authenticate-fpga-config property for FPGA bitstream authentication,
which makes sure a signed bitstream has valid signatures.
Signed-off-by: Richard Gong
---
v4: explain authenticate-fpga-config flag further
v3: no change
v2: put authenticate-fpga-config above partial
From: Richard Gong
Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream
authentication feature. Authenticating a bitstream is to make sure a signed
bitstream has the valid signatures.
Except for the actual configuration of the device, the bitstream
authentication works the
From: Richard Gong
Extend FPGA manager driver to support FPGA bitstream authentication on
Intel SocFPGA platforms.
Signed-off-by: Richard Gong
---
v4: s/FPGA_MGR_BITSTREM_AUTHENTICATION/FPGA_MGR_BITSTREAM_AUTHENTICATE
v3: add handle to retriev the firmware version to keep driver
back
From: Richard Gong
Add FPGA_MGR_BITSTREAM_AUTHENTICATE flag for FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures.
Except for the actual configuration of the device, the authentication works
the same way as FPGA configuration does. If the authentication
From: Richard Gong
This is 4th submission of Intel service layer and FPGA patches.
This submission includes additional changes for Intel service layer driver
to get the firmware version running at FPGA SoC device. Then FPGA manager
driver, one of Intel service layer driver's client, can d
From: Richard Gong
This is 5th submission of Intel service layer and FPGA patches, which
includes the missing standalone patch in the 4th submission.
This submission includes additional changes for Intel service layer driver
to get the firmware version running at FPGA SoC device. Then FPGA
From: Richard Gong
Add authenticate-fpga-config property for FPGA bitstream authentication,
which makes sure a signed bitstream has valid signatures.
Signed-off-by: Richard Gong
---
v5: rewrite the description to highlight two things with
authenticate-fpga-config flag
v4: explain
From: Richard Gong
Clean up COMMAND_RECONFIG_FLAG_PARTIAL flag by resetting it to 0, which
aligns with the firmware settings.
Fixes: 36847f9e3e56 ("firmware: stratix10-svc: correct reconfig flag and
timeout values")
Signed-off-by: Richard Gong
---
v5: new add, add the missing standa
From: Richard Gong
Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream
authentication feature. Authenticating a bitstream is to make sure a signed
bitstream has the valid signatures.
Except for the actual configuration of the device, the bitstream
authentication works the
From: Richard Gong
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA manager driver, one of Intel service layer
driver's client, can decide whether to handle the newly added bitstream
authentication function based on the retrieved fir
From: Richard Gong
Extend FPGA manager driver to support FPGA bitstream authentication on
Intel SocFPGA platforms.
Signed-off-by: Richard Gong
---
v5: no change
v4: s/FPGA_MGR_BITSTREM_AUTHENTICATION/FPGA_MGR_BITSTREAM_AUTHENTICATE
v3: add handle to retriev the firmware version to keep driver
From: Richard Gong
Add FPGA_MGR_BITSTREAM_AUTHENTICATE flag for FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures.
Except for the actual configuration of the device, the authentication works
the same way as FPGA configuration does. If the authentication
From: Richard Gong
Add authenticate-fpga-config property to support FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures.
Signed-off-by: Richard Gong
---
v5: no change
v4: add additional checks to make sure *only* authenticate
v3: no change
v2: changed in
-f...@vger.kernel.org; linux-kernel@vger.kernel.org
Cc: Gong, Richard
Subject: [PATCHv5 0/7] Extend Intel service layer, FPGA manager and region
From: Richard Gong
This is 5th submission of Intel service layer and FPGA patches, which includes
the missing standalone patch in the 4th submission
Hi Moritz,
On 5/31/20 2:49 PM, Moritz Fischer wrote:
On Fri, May 29, 2020 at 08:15:15AM -0500, Richard Gong wrote:
Hi Moritz,
Sorry for asking.
When you get chance, can you review my version 2 patch submitted on
05/15/20?
Regards,
Richard
On 5/15/20 9:35 AM, richard.g...@linux.intel.com
From: Richard Gong
I followed the process to register or request a valid IOCTL number/letter,
but I got the delivery failure status notification.
Cypto service driver and service layer driver patches have been reviewed
internally by colleagues at Intel.
Intel SoCFPGA is composed of a 64 bit
From: Richard Gong
Extend Intel service layer driver to support new crypto services on
Intel SoCFPGA platforms.
The crypto services include security certificate, image boot validation,
security key cancellation, get provision data, random number generation,
advance encrtption standard (AES
From: Richard Gong
Add Intel FPGA crypto service (FCS) driver to support new crypto services
on Intel SoCFPGA platforms.
The crypto services include security certificate, image boot validation,
security key cancellation, get provision data, random number generation,
advance encrtption standard
I will move them to drivers/misc.
Regards,
Richard
On 8/11/20 7:34 PM, Herbert Xu wrote:
On Tue, Aug 11, 2020 at 08:56:22AM -0500, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add Intel FPGA crypto service (FCS) driver to support new crypto services
on Intel SoCFPGA platforms
tristate "Intel Stratix10 Service Layer"
- depends on ARCH_INTEL_SOCFPGA && HAVE_ARM_SMCCC
+ depends on ARCH_INTEL_SOCFPGA && ARM64 && HAVE_ARM_SMCCC
default n
help
Intel Stratix10 service layer runs at privileged exception level,
Acked-by: Richard Gong
Regards,
Richard
, 2021 4:20 PM
To: m...@kernel.org; t...@redhat.com; gre...@linuxfoundation.org;
linux-f...@vger.kernel.org; linux-kernel@vger.kernel.org
Cc: Gong, Richard
Subject: [PATCHv5 0/7] Extend Intel service layer, FPGA manager and region
From: Richard Gong
This is 5th submission of Intel service layer
From: Richard Gong
Hi Greg,
Please take this stratix10-svc patch, which has been reviewed on the
mailing list and applied cleanly on current linux-next and
char-misc-testing.
Thanks,
Richard
Richard Gong (1):
firmware: stratix10-svc: extend SVC driver to get the firmware version
drivers
From: Richard Gong
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA manager driver, one of Intel service layer
driver's client, can decide whether to handle the newly added bitstream
authentication function based on the retrieved fir
Hi David,
On 3/30/21 9:19 AM, David Laight wrote:
From: richard.g...@linux.intel.com
Sent: 30 March 2021 15:33
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA manager driver, one of Intel service layer
driver's client, can decide whether t
Hi Moritz,
On 3/30/21 11:15 AM, Moritz Fischer wrote:
Hi Richard,
On Tue, Mar 30, 2021 at 09:33:05AM -0500, richard.g...@linux.intel.com wrote:
From: Richard Gong
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA manager driver, one of
Hi Tom,
On 3/19/21 4:22 PM, Richard Gong wrote:
Hi Moritz,
Thanks for approving the 1st patch of my version 5 patchest, which submitted on
02/09/21.
This change
e23bd83368af ("firmware: stratix10-svc: fix kernel-doc markups")
This patch e23bd83368af is not from my versi
On 3/22/21 3:26 AM, Krzysztof Kozlowski wrote:
On 21/03/2021 22:09, Arnd Bergmann wrote:
On Sun, Mar 21, 2021 at 7:46 PM Krzysztof Kozlowski
wrote:
The Stratix10 service layer and RCU drivers are useful only on
Stratix10, so on ARMv8. Compile testing the RCU driver on 32-bit ARM
fails:
On 3/22/21 7:41 AM, Krzysztof Kozlowski wrote:
On 22/03/2021 13:58, Richard Gong wrote:
On 3/22/21 3:26 AM, Krzysztof Kozlowski wrote:
On 21/03/2021 22:09, Arnd Bergmann wrote:
On Sun, Mar 21, 2021 at 7:46 PM Krzysztof Kozlowski
wrote:
The Stratix10 service layer and RCU drivers are
Hi Tom,
On 3/22/21 8:53 AM, Tom Rix wrote:
On 3/21/21 2:05 PM, Richard Gong wrote:
Hi Tom >>
On 3/19/21 4:22 PM, Richard Gong wrote:
Hi Moritz,
Thanks for approving the 1st patch of my version 5 patchest, which submitted on
02/09/21.
This change
e23bd83368af (&qu
diff --git a/MAINTAINERS b/MAINTAINERS
index 67b104202602..00828de0a7bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9266,6 +9266,7 @@ F:tools/power/x86/intel-speed-select/
INTEL STRATIX10 FIRMWARE DRIVERS
M:Richard Gong
+R: Tom RixL: linux-kernel@vger.kernel.or
-kernel@vger.kernel.org
Cc: Gong, Richard
Subject: [PATCHv5 0/7] Extend Intel service layer, FPGA manager and region
From: Richard Gong
This is 5th submission of Intel service layer and FPGA patches, which includes
the missing standalone patch in the 4th submission.
This submission includes
On 11/16/20 8:24 PM, Xu Yilun wrote:
On Mon, Nov 16, 2020 at 08:14:52AM -0600, Richard Gong wrote:
Hi Yilun,
On 11/15/20 8:47 PM, Xu Yilun wrote:
On Sun, Nov 15, 2020 at 11:21:06AM -0800, Moritz Fischer wrote:
Hi Richard,
On Thu, Nov 12, 2020 at 12:06:42PM -0600, richard.g
On 11/17/20 11:47 PM, Xu Yilun wrote:
On Tue, Nov 17, 2020 at 09:39:55AM -0600, Richard Gong wrote:
On 11/16/20 8:24 PM, Xu Yilun wrote:
On Mon, Nov 16, 2020 at 08:14:52AM -0600, Richard Gong wrote:
Hi Yilun,
On 11/15/20 8:47 PM, Xu Yilun wrote:
On Sun, Nov 15, 2020 at 11:21:06AM
From: Richard Gong
Add FPGA_MGR_BITSTREM_AUTHENTICATION flag for FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures.
Except for the actual configuration of the device, the authentication works
the same way as FPGA configuration does. If the authentication
From: Richard Gong
Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream
authentication feature. Authenticating a bistream is to make sure a signed
bitstream has the valid signatures.
Except for the actual configuration of the device, the bitstream
authentication works the
From: Richard Gong
Add authenticate-fpga-config property to support FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures.
Signed-off-by: Richard Gong
---
v2: changed in alphabetical order
---
drivers/fpga/of-fpga-region.c | 3 +++
1 file changed, 3
From: Richard Gong
Add authenticate-fpga-config property for FPGA bitstream authentication,
which makes sure a signed bitstream has valid signatures.
Signed-off-by: Richard Gong
---
v2: put authenticate-fpga-config above partial-fpga-config
update commit messages
---
Documentation
From: Richard Gong
Extend FPGA manager driver to support FPGA bitstream authentication on
Intel SocFPGA platforms.
Signed-off-by: Richard Gong
---
v2: use flag defined in stratix10-svc driver
---
drivers/fpga/stratix10-soc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/fpga
From: Richard Gong
This is 2nd submission of Intel service layer and FPGA patches.
The customer wants to verify that a FPGA bitstream can be started properly
before saving the bitstream to the QSPI flash memory.
Bitstream authentication makes sure a signed bitstream has valid signatures.
The
Hi Moritz,
On 11/18/20 9:30 AM, Moritz Fischer wrote:
On Wed, Nov 18, 2020 at 08:29:09AM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream
authentication feature. Authenticating a bistream is to make sure a
Hi Moritz,
Sorry for late reply, I was out last week.
On 11/21/20 7:10 PM, Moritz Fischer wrote:
Richard,
On Wed, Nov 18, 2020 at 12:16:09PM -0600, Richard Gong wrote:
-#define COMMAND_RECONFIG_FLAG_PARTIAL 1
+#define COMMAND_RECONFIG_FLAG_PARTIAL 0
+#define
Hi Moritz,
On 11/30/20 10:31 PM, Moritz Fischer wrote:
Hi Richard,
On Mon, Nov 30, 2020 at 12:55:44PM -0600, Richard Gong wrote:
Hi Moritz,
Sorry for late reply, I was out last week.
No worries, usually I'm late with replies ;-)
On 11/21/20 7:10 PM, Moritz Fischer wrote:
Richard
Hi Moritz,
On 12/1/20 1:19 PM, Moritz Fischer wrote:
Hi Richard,
On Tue, Dec 01, 2020 at 01:30:16PM -0600, Richard Gong wrote:
Can U-Boot determine whether it's the new or old flow? Can you set a
different compatible value in your device-tree, to disambiguate
behaviors?
The boot fl
Hi Tom,
On 1/25/21 4:56 PM, Tom Rix wrote:
On 1/25/21 12:56 PM, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add COMMAND_AUTHENTICATE_BITSTREAM command flag for new added bitstream
authentication feature. Authenticating a bitstream is to make sure a signed
bitstream has the valid
Hi Moritz,
Thanks for your reviews!
On 1/25/21 11:01 PM, Moritz Fischer wrote:
Hi Richard,
On Mon, Jan 25, 2021 at 02:56:24PM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Extend Intel service layer driver to get the firmware version running at
FPGA device. Therefore FPGA
Hi Moritz,
On 1/25/21 11:04 PM, Moritz Fischer wrote:
On Mon, Jan 25, 2021 at 02:56:25PM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add FPGA_MGR_BITSTREM_AUTHENTICATION flag for FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures
On 1/25/21 11:05 PM, Moritz Fischer wrote:
On Mon, Jan 25, 2021 at 02:56:27PM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add authenticate-fpga-config property for FPGA bitstream authentication,
which makes sure a signed bitstream has valid signatures.
Signed-off-by
Hi Moritz,
On 1/25/21 11:10 PM, Moritz Fischer wrote:
On Mon, Jan 25, 2021 at 02:56:26PM -0600, richard.g...@linux.intel.com wrote:
From: Richard Gong
Add authenticate-fpga-config property to support FPGA bitstream
authentication, which makes sure a signed bitstream has valid signatures
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