Hi,
I am trying to use GNU global for kernel source browsing but have run
into a problem when using "gtags" target in Makefile. The index
files(GTAGS, GSYMS, GPATH, GRTAGS) don't work and on further
investigation turned out to be 16kb each in size. My command line is -
make ARCH=arm CROSS_COMPIL
Michal Marek writes:
> On 8.7.2013 19:22, Punit Agrawal wrote:
>> Hi,
>>
>> I am trying to use GNU global for kernel source browsing but have run
>> into a problem when using "gtags" target in Makefile. The index
>> files(GTAGS, GSYMS, GPATH, GRTAGS)
Christoffer Dall writes:
> On Tue, Sep 06, 2016 at 04:22:17PM +0100, Punit Agrawal wrote:
>> Christoffer Dall writes:
>>
>> > On Tue, Sep 06, 2016 at 12:07:59PM +0100, Punit Agrawal wrote:
>> >> Christoffer Dall writes:
>> >>
>> >&g
: tlbflush.h: add __tlbi() macro
arm64/kvm: hyp: tlb: use __tlbi() helper
Punit Agrawal (5):
perf/trace: Add notification for perf trace events
KVM: Track the pid of the VM process
KVM: arm/arm64: Register perf trace event notifier
arm64: KVM: Handle trappable TLB instructions
arm64: KVM
specific
contexts (e.g., virtual machines).
Signed-off-by: Punit Agrawal
Cc: Steven Rostedt
Cc: Ingo Molnar
---
include/linux/trace_events.h| 3 +++
kernel/trace/trace_event_perf.c | 24
2 files changed, 27 insertions(+)
diff --git a/include/linux/trace_events.h b
Register a notifier to track state changes of perf trace events.
The notifier will enable taking appropriate action for trace events
targeting VM.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
---
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kvm/arm.c
for a specific virtual machine.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
---
arch/arm64/kvm/perf_trace.c | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/kvm/perf_trace.c b/arch/arm64/kvm/perf_trace.c
index 1cafbc9
-off-by: Mark Rutland
Cc: Marc Zyngier
[ rename tlbi -> __tlbi, convert additional sites, update commit log ]
Signed-off-by: Punit Agrawal
Acked-by: Christoffer Dall
---
arch/arm64/kvm/hyp/tlb.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/
The ARMv8 architecture allows trapping of TLB maintenane instructions
from EL0/EL1 to higher exception levels. On encountering a trappable TLB
instruction in a guest, an exception is taken to EL2.
Add functionality to handle emulating the TLB instructions.
Signed-off-by: Punit Agrawal
Cc
existing tlbflush.h code is moved over to use the helper.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Marc Zyngier
[ rename helper to __tlbi, update comment and commit log ]
Signed-off-by: Punit Agrawal
Reviewed-by: Will Deacon
---
arch/arm64/include/asm/tlbflush.h | 34
: Punit Agrawal
Cc: Paolo Bonzini
Cc: "Radim Krčmář"
Cc: Christoffer Dall
Cc: Marc Zyngier
---
include/linux/kvm_host.h | 1 +
virt/kvm/kvm_main.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 9c28b4d..7c42c94 10
Punit Agrawal writes:
> Add a mechanism to notify listeners about perf trace event state
> changes. This enables listeners to take actions requiring the event
> context (e.g., attached process).
>
> The notification mechanism can be used to reduce trace point based
> pro
Will Deacon writes:
> On Fri, Aug 26, 2016 at 10:37:08AM +0100, Punit Agrawal wrote:
>> > Will Deacon writes:
>> >> The easiest thing to do is just TLBI VMALLE1IS for all trapped operations,
>> >> but you might want to see how that performs.
>> >
>
Will Deacon writes:
> Hi Punit,
>
> On Tue, Aug 16, 2016 at 11:45:11AM +0100, Punit Agrawal wrote:
>> The ARMv8 architecture allows trapping of TLB maintenane instructions
>> from EL0/EL1 to higher exception levels. On encountering a trappable TLB
>> instruction in a g
Punit Agrawal writes:
> Will Deacon writes:
>
>> Hi Punit,
>>
>> On Tue, Aug 16, 2016 at 11:45:11AM +0100, Punit Agrawal wrote:
>>> The ARMv8 architecture allows trapping of TLB maintenane instructions
>>> from EL0/EL1 to higher exception levels. On en
the firmware provides this
table and if it is not present skip any log output. The existing
behaviour is preserved in all other cases.
Suggested-by: Borislav Petkov
Signed-off-by: Punit Agrawal
Cc: Borislav Petkov
Cc: James Morse
---
drivers/acpi/apei/ghes.c | 4 ++--
drivers/acpi/apei
"Luck, Tony" writes:
> On Tue, Aug 15, 2017 at 11:22:06AM +0100, Punit Agrawal wrote:
>> There is already a bert driver which prints the error record. Would it
>> make sense to integrate the character device there instead of creating a
>> new driver?
>
> L
"Luck, Tony" writes:
>> One thing I missed commenting on in the previous version -
>>
>> Have you thought of exposing the error records via /sys/firmware/acpi?
>> The tables are already exposed there and as BERT is part of ACPI
>> logically that's a better fit compared to a misc device.
>
> That
Andrew Morton writes:
> On Mon, 19 Jun 2017 18:01:37 +0100 Punit Agrawal
> wrote:
>
>> This is v5 of the patchset to update the hugetlb code to support
>> contiguous hugepages. Previous version of the patchset can be found at
>> [0].
>
> Dumb question: is t
Andrew Morton writes:
> On Tue, 20 Jun 2017 14:39:57 +0100 Punit Agrawal
> wrote:
>
>>
>> The architecture supports two flavours of hugepages -
>>
>> * Block mappings at the pud/pmd level
>>
>> These are regular hugepages where a pmd or a p
Sudeep Holla writes:
> On 15/09/15 17:50, Punit Agrawal wrote:
>> ARM System Control Processor (SCP) provides an API to query and use
>> the sensors available in the system. Extend the SCPI driver to support
>> sensor messages.
>>
>> Signed-off-by: Punit Agrawa
Mark Rutland writes:
> On Wed, Oct 07, 2015 at 08:22:40PM +0800, Dawei Chien wrote:
>> From: "Dawei.Chien"
>>
>> This power model is base on Intelligent Power Allocation (IPA) technical,
>> requires that the operating-points of the CPUs are registered using the
>> kernel's opp library and the `
thermal_zone_of_sensor_register is documented as returning a pointer
to either a valid thermal_zone_device on success, or a corresponding
ERR_PTR() value.
In contrast, the function returns NULL when THERMAL_OF is configured
off. Fix this.
Signed-off-by: Punit Agrawal
Acked-by: Guenter Roeck
Cc
Punit Agrawal writes:
> The System Control Processor (SCP) provides access to SoC sensors via
> the System Control and Power Interface (SCPI) Message Protocol. Add
> bindings to allow probing of these sensors. Also support referencing
> of the sensors for setting up thermal zones via
Hi,
Mawanda Henry writes:
> SPDX license helps developers and machines to know the license governing
> a particular file hence easing work
>
> Signed-off-by: Mawanda Henry
> ---
> drivers/bus/arm-cci.c | 10 +-
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/b
Michal Hocko writes:
> On Fri 22-06-18 16:58:05, Hanjun Guo wrote:
>> On 2018/6/20 19:51, Punit Agrawal wrote:
>> > Xie XiuQi writes:
>> >
>> >> Hi Lorenzo, Punit,
>> >>
>> >>
>> >> On 2018/6/20 0:32, Lorenzo Pieralisi
Vincent Guittot writes:
> Hi Amit,
>
> On Wed, 22 Aug 2018 at 12:11, Punit Agrawal wrote:
>>
>> Hi Vincent,
>>
>> Thanks for the patch. One comment about the choice of units below.
>>
>> Vincent Guittot writes:
>>
>> > The unit of d
n as there is no benefit from doing so -
the usage of these structures is independent from where the controller
is located.
Signed-off-by: Punit Agrawal
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Lorenzo Pieralisi
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm64/kernel/pci.c | 5 ++-
additional context.
Drop the node local allocation as there is no benefit from doing so -
the usage of these structures is independent from where the controller
is located.
Signed-off-by: Punit Agrawal
Cc: Bjorn Helgaas
Cc: Thomas Gleixner
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
---
arc
atches are based on v4.19-rc1 and has been boot tested on arm64
and compile tested on x86.
Thanks,
Punit
[0] https://www.spinics.net/lists/arm-kernel/msg669746.html
Punit Agrawal (2):
arm64: PCI: Remove node-local allocations when initialising host
controller
x86/PCI: Remove node-local
000)^2 = 10^15 mW
> which is not realistic
>
> With the unit used by the code, the min power is
> min power = 1 * 1000 * 1^2 = 1000uW = 1mW which is far more realistic
>
> Signed-off-by: Vincent Guittot
Acked-by: Punit Agrawal
Thanks for fixing the mismatch.
> ---
>
ang Lui
>>
>> Jiang Liu does not work on the kernel anymore so we won't know
>> anytime soon the reasoning behind commit 965cd0e4a5e5
>>
>> > On 08/01/2018 12:31 PM, Punit Agrawal wrote:
>> > >Memory for host controller data structures is allocated local
Bjorn Helgaas writes:
> On Wed, Aug 08, 2018 at 03:44:03PM +0100, Punit Agrawal wrote:
>> Bjorn Helgaas writes:
>> > On Thu, Aug 2, 2018 at 9:33 AM Lorenzo Pieralisi
>> > wrote:
>> >> On Wed, Aug 01, 2018 at 02:38:51PM -0500, Jeremy Linton wrote:
>
Hi Vincent,
Thanks for the patch. One comment about the choice of units below.
Vincent Guittot writes:
> The unit of dynamic-power-coefficient is described as mW/MHz/uV^2 whereas
> its usage in the code assumes that unit is mW/GHz/V^2
Instead of choosing GHz as the base, I'd prefer to use uW/M
7;m sending the patchset as RFC to get feedback on the code as well as
allow evaluation on real systems.
Thanks,
Punit
[0] https://patchwork.kernel.org/patch/10145339/
Punit Agrawal (4):
arm64: Correct type for PUD macros
KVM: arm64: Support dirty page tracking for PUD hugepages
KVM: arm/
: 084bd29810a56 ("ARM64: mm: HugeTLB support.")
Fixes: 206a2a73a62d3 ("arm64: mm: Create gigabyte kernel logical mappings where
possible")
Signed-off-by: Punit Agrawal
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable-hwdef.h | 6 +++---
1 file changed, 3 insert
compile on arm32.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
---
arch/arm/include/asm/kvm_mmu.h | 9 +
arch/arm64/include/asm/kvm_mmu.h | 10 ++
virt/kvm/arm/mmu.c | 9 ++---
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git
with this patch.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
---
virt/kvm/arm/mmu.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 02eefda5d71e..f02219a91b19 100644
--- a/virt/kvm/arm
sizes in the TLB entries.
Signed-off-by: Punit Agrawal
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Catalin Marinas
---
arch/arm/include/asm/kvm_mmu.h | 10 +
arch/arm/include/asm/pgtable-3level.h | 2 +
arch/arm64/include/asm/kvm_mmu.h | 19 +
arch/arm64/include/asm
Christoffer Dall writes:
> On Thu, Jan 04, 2018 at 06:24:33PM +0000, Punit Agrawal wrote:
>> KVM only supports PMD hugepages at stage 2 but doesn't actually check
>> that the provided hugepage memory pagesize is PMD_SIZE before populating
>> stage 2 entries.
>>
Christoffer Dall writes:
> On Thu, Jan 11, 2018 at 01:01:07PM +0000, Punit Agrawal wrote:
>> Christoffer Dall writes:
>>
>> > On Thu, Jan 04, 2018 at 06:24:33PM +, Punit Agrawal wrote:
>> >> KVM only supports PMD hugepages at stage 2 but doesn'
ating stage 2
mappings that extend beyond the supplied memory.
Fix this by checking for the pagesize of userspace vma before creating
PMD hugepage at stage 2.
Fixes: ad361f093c1e31d ("KVM: ARM: Support hugetlbfs backed huge pages")
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
C
Catalin Marinas writes:
> On Wed, Jan 10, 2018 at 07:07:26PM +0000, Punit Agrawal wrote:
>> The PUD macros (PUD_TABLE_BIT, PUD_TYPE_MASK, PUD_TYPE_SECT) use the
>> pgdval_t even when pudval_t is available. Even though the underlying
>> type for both (u64) is the same it is c
Hi Kirill,
A flyby comment below.
"Kirill A. Shutemov" writes:
> MKTME claims several upper bits of the physical address in a page table
> entry to encode KeyID. It effectively shrinks number of bits for
> physical address. We should exclude KeyID bits from physical addresses.
>
> For instance,
"Kirill A. Shutemov" writes:
> The patch adds new gfp flag to indicate that we're allocating encrypted
> page.
>
> Architectural code may need to do special preparation for encrypted
> pages such as flushing cache to avoid aliasing.
>
> Signed-off-by: Kirill A. Shutemov
> ---
> include/linux/gf
should have exec permission [1/4]
* Fix broken condition to detect THP hugepage [1/4]
* Fix in-correct hunk resulting from a rebase [4/4]
[0] https://www.spinics.net/lists/arm-kernel/msg663562.html
[1] https://www.spinics.net/lists/kvm/msg171065.html
Punit Agrawal (7):
KVM: arm/arm64: Share common code
should have exec permission [1/4]
* Fix broken condition to detect THP hugepage [1/4]
* Fix in-correct hunk resulting from a rebase [4/4]
[0] https://www.spinics.net/lists/arm-kernel/msg663562.html
[1] https://www.spinics.net/lists/kvm/msg171065.html
Punit Agrawal (7):
KVM: arm/arm64: Sha
Jonathan Cameron writes:
[...]
>
> I'll test it when back in the office, but I had a similar issue with
> memory only nodes when I moved the SRAT listing for cpus from the 4
> 4th mode to the 3rd node to fake some memory I could hot unplug.
> This gave a memory only node for the last node on the
Jonathan Cameron writes:
[...]
>
> I'll test it when back in the office, but I had a similar issue with
> memory only nodes when I moved the SRAT listing for cpus from the 4
> 4th mode to the 3rd node to fake some memory I could hot unplug.
> This gave a memory only node for the last node on the
Hi,
Nightly LTP runs are hitting a use-after-free on upstream kernels when
running with 64k pages. There isn't a specific test triggering the
issue. Also, the problem is not encountered with 4k pages.
The boards used for the nightly runs mount their filesystem (Debian
Jessie) via NFS with the fol
orrect hunk resulting from a rebase [4/4]
[0] https://www.spinics.net/lists/arm-kernel/msg628053.html
[1] https://lkml.org/lkml/2018/4/20/566
[2] https://lkml.org/lkml/2018/5/1/133
[3] https://lwn.net/Articles/750176/
Punit Agrawal (4):
KVM: arm/arm64: Share common code in user_mem_abort()
KV
erent pagesizes.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
---
virt/kvm/arm/mmu.c | 69 +++---
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 7f6a944
.
Signed-off-by: Punit Agrawal
Acked-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 5 +
arch/arm64/include/asm/kvm_mmu.h | 5 +
virt/kvm/arm/mmu.c | 7 ---
3 files changed, 14 insertions
.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 19
arch/arm64/include/asm/kvm_mmu.h | 15 ++
arch/arm64/include/asm/pgtable-hwdef.h | 4
code with arm32.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 16
arch/arm64/include/asm/kvm_mmu.h | 10 ++
virt/kvm/arm/mmu.c
Laurent Dufour writes:
> On 08/05/2018 13:04, Punit Agrawal wrote:
>> Hi Laurent,
>>
>> Laurent Dufour writes:
>>
>>> Set ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT which turns on the
>>> Speculative Page Fault handler when building for 64bit.
>>&g
Michal Hocko writes:
> On Tue 19-06-18 20:03:07, Xie XiuQi wrote:
> [...]
>> I tested on a arm board with 128 cores 4 numa nodes, but I set
>> CONFIG_NR_CPUS=72.
>> Then node 3 is not be created, because node 3 has no memory, and no cpu.
>> But some pci device may related to node 3, which be set
Lorenzo Pieralisi writes:
> On Tue, Jun 19, 2018 at 01:52:16PM +0100, Punit Agrawal wrote:
>> Michal Hocko writes:
>>
>> > On Tue 19-06-18 20:03:07, Xie XiuQi wrote:
>> > [...]
>> >> I tested on a arm board with 128 cores 4 numa nodes, but I set
Michal Hocko writes:
> On Tue 19-06-18 15:54:26, Punit Agrawal wrote:
> [...]
>> In terms of $SUBJECT, I wonder if it's worth taking the original patch
>> as a temporary fix (it'll also be easier to backport) while we work on
>> fixing these other issues and e
Xie XiuQi writes:
> Hi Lorenzo, Punit,
>
>
> On 2018/6/20 0:32, Lorenzo Pieralisi wrote:
>> On Tue, Jun 19, 2018 at 04:35:40PM +0100, Punit Agrawal wrote:
>>> Michal Hocko writes:
>>>
>>>> On Tue 19-06-18 15:54:26, Punit Agrawal wrote:
>>
Marc Zyngier writes:
> Hi Punit,
>
> On 05/07/18 15:08, Punit Agrawal wrote:
>> The code for operations such as marking the pfn as dirty, and
>> dcache/icache maintenance during stage 2 fault handling is duplicated
>> between normal pages and PMD hugepages.
>>
Suzuki K Poulose writes:
> Hi Punit,
>
> On 05/07/18 15:08, Punit Agrawal wrote:
>> KVM only supports PMD hugepages at stage 2. Now that the various page
>> handling routines are updated, extend the stage 2 fault handling to
>> map in PUD hugepages.
>>
>> A
e panic because NUMA node
>> > 3 is not a valid node.
>
> Hmm, but this is not a memory-less node. It sounds like a misconfigured
> kernel to me or the broken initialization. Each CPU should have a
> fallback numa node to be used.
>
>> > I triggered this BUG on arm64 platfor
Punit Agrawal writes:
[...]
>
> CONFIG_HAVE_MEMORYLESS node is not enabled on arm64 which means we end
> up returning the original node in the fallback path.
>
> Xie, does the below patch help? I can submit a proper patch if this
> fixes the issue for you.
>
> -- >8
Tsukada-san,
I am not familiar with memcg so can't comment about whether the patchset
is the right way to solve the problem outlined in the cover letter but
had a couple of comments about this patch.
TSUKADA Koutaro writes:
> The current memcg implementation assumes that the compound page is TH
Punit Agrawal writes:
> Tsukada-san,
>
> I am not familiar with memcg so can't comment about whether the patchset
> is the right way to solve the problem outlined in the cover letter but
> had a couple of comments about this patch.
>
> TSUKADA Koutaro writ
Christoffer Dall writes:
> On Tue, Dec 11, 2018 at 05:10:33PM +, Suzuki K Poulose wrote:
>> This series is an update to the PUD hugepage support previously posted
>> at [0]. This patchset adds support for PUD hugepages at stage 2 a
>> feature that is useful on cores that have support for larg
Randy Dunlap writes:
> On 10/8/18 3:03 AM, Punit Agrawal wrote:
>> Arm v8 architecture supports multiple page sizes - 4k, 16k and
>> 64k. Based on the active page size, the Linux port supports
>> corresponding hugepage sizes at PMD and PUD(4k only) levels.
>>
>&
Hi Lukas,
Lukas Braun writes:
> Userspace can create a memslot with memory backed by (transparent)
> hugepages, but with bounds that do not align with hugepages.
> In that case, we cannot map the entire region in the guest as hugepages
> without exposing additional host memory to the guest and p
As I'll no longer be working with Arm, add a mailmap entry so any mail
directed towards me reaches the appropriate mailbox.
Signed-off-by: Punit Agrawal
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index a76be45fef6c..28fecafa6506 100644
--- a/.ma
review tag [4/4]
v1 -> v2:
* Create helper to check if the page should have exec permission [1/4]
* Fix broken condition to detect THP hugepage [1/4]
* Fix in-correct hunk resulting from a rebase [4/4]
[0] https://www.spinics.net/lists/arm-kernel/msg664276.html
[1] https://www.spinics.net/li
gt; Signed-off-by: Mark Rutland
> Signed-off-by: Suzuki K. Poulose
> Cc: Will Deacon
> Cc: Catalin Marinas
> Cc: Punit Agrawal
> ---
> arch/arm64/include/asm/cputype.h |2 +
> arch/arm64/kernel/armv8_deprecated.c | 125
> +-
>
to rectify this?
You're right. The check against PMD_SIZE was lost during the rebase to
v4.9. I should've noticed this before it got sent.
Please send a patch to fix this. Alternately, I can fix this with your
reported by.
Thanks,
Punit
>
> Thanks,
> Ioana Ciornei
>
>>
Christoffer Dall writes:
> On Fri, Apr 20, 2018 at 03:54:06PM +0100, Punit Agrawal wrote:
>> The code for operations such as marking the pfn as dirty, and
>> dcache/icache maintenance during stage 2 fault handling is duplicated
>> between normal pages and PMD hugepag
Christoffer Dall writes:
> On Fri, Apr 20, 2018 at 03:54:09PM +0100, Punit Agrawal wrote:
>> KVM only supports PMD hugepages at stage 2. Extend the stage 2 fault
>> handling to add support for PUD hugepages.
>>
>> Addition of pud hugepage support enables additional
Hi Laurent,
I am looking to add support for speculative page fault handling to
arm64 (effectively porting this patch) and had a few questions.
Apologies if I've missed an obvious explanation for my queries. I'm
jumping in bit late to the discussion.
On Tue, Apr 17, 2018 at 3:33 PM, Laurent Dufour
Hi Laurent,
One nitpick below.
On Tue, Apr 17, 2018 at 3:33 PM, Laurent Dufour
wrote:
> This change is inspired by the Peter's proposal patch [1] which was
> protecting the VMA using SRCU. Unfortunately, SRCU is not scaling well in
> that particular case, and it is introducing major performance
/566
[2] https://lwn.net/Articles/750176/
Punit Agrawal (4):
KVM: arm/arm64: Share common code in user_mem_abort()
KVM: arm/arm64: Introduce helpers to manupulate page table entries
KVM: arm64: Support dirty page tracking for PUD hugepages
KVM: arm64: Add support for PUD hugepages at stage 2
erent pagesizes.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
---
virt/kvm/arm/mmu.c | 66 +++---
1 file changed, 39 insertions(+), 27 deletions(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 7f6a944
entries.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 19
arch/arm64/include/asm/kvm_mmu.h | 15 ++
arch/arm64/include/asm/pgtable-hwdef.h | 4
code with arm32.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 16
arch/arm64/include/asm/kvm_mmu.h | 10 ++
virt/kvm/arm/mmu.c
.
Signed-off-by: Punit Agrawal
Acked-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm/include/asm/kvm_mmu.h | 5 +
arch/arm64/include/asm/kvm_mmu.h | 5 +
virt/kvm/arm/mmu.c | 7 ---
3 files changed, 14 insertions
Hi Suzuki,
Thanks for having a look.
Suzuki K Poulose writes:
> On 01/05/18 11:26, Punit Agrawal wrote:
>> Introduce helpers to abstract architectural handling of the conversion
>> of pfn to page table entries and marking a PMD page table entry as a
>> block entry.
Hi Laurent,
One query below -
Laurent Dufour writes:
[...]
>
> Ebizzy:
> ---
> The test is counting the number of records per second it can manage, the
> higher is the best. I run it like this 'ebizzy -mTRp'. To get consistent
> result I repeated the test 100 times and measure the average
Hi Ganesh,
I was looking at evaluating speculative page fault handling on arm64 and
noticed your patch.
Some comments below -
Ganesh Mahendran writes:
> This patch enables the speculative page fault on the arm64
> architecture.
>
> I completed spf porting in 4.9. From the test result,
> we can
Catalin Marinas writes:
> On Tue, May 01, 2018 at 11:26:59AM +0100, Punit Agrawal wrote:
>> KVM currently supports PMD hugepages at stage 2. Extend the stage 2
>> fault handling to add support for PUD hugepages.
>>
>> Addition of pud hugepage support enables additi
Suzuki K Poulose writes:
> On 05/14/2018 03:43 PM, Punit Agrawal wrote:
>> KVM only supports PMD hugepages at stage 2. Extend the stage 2 fault
>> handling to add support for PUD hugepages.
>>
>> Addition of pud hugepage support enables additional hugepage
>>
Re-factor the code to override the firmware provided frequency domain
information (via PSD) to localise the checks in one function.
No functional change intended.
Signed-off-by: Punit Agrawal
Cc: Wei Huang
---
drivers/cpufreq/acpi-cpufreq.c | 17 +++--
1 file changed, 15
eturn value of the function to bool
Punit Agrawal (2):
cpufreq: acpi-cpufreq: Re-factor overriding ACPI PSD
cpufreq: acpi-cpufreq: Add processor to the ignore PSD override list
drivers/cpufreq/acpi-cpufreq.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
--
2.29.2
verride is not required for Zen3
onwards, it seems that domain information can be trusted even on
certain earlier systems. Update the check, to skip the override for
Zen2 processors known to work without the override.
Signed-off-by: Punit Agrawal
Cc: Wei Huang
---
drivers/cpufreq/acpi-cpu
Borislav Petkov writes:
> On Fri, Dec 11, 2020 at 07:56:40AM +0900, Punit Agrawal wrote:
>> Booting Linux on a Zen2 based processor (family: 0x17, model: 0x60,
>> stepping: 0x1) shows the following message in the logs -
>>
>> acpi_cpufreq: overriding BIOS provide
Borislav Petkov writes:
> On Wed, Dec 09, 2020 at 08:21:48AM +0900, Punit Agrawal wrote:
>> According to the commit log, acd316248205 seems to be only targeted at
>> powernow-K8 -
>
> No, it is not targeted at powernow-k8 - acpi-cpufreq.c is what is used
> on AMD h
Borislav Petkov writes:
> On Mon, Dec 07, 2020 at 04:07:52PM -0600, Wei Huang wrote:
>> I think we shouldn't override zen2 if _PSD is correct. In my opinion,
>> there are two approaches:
>>
>> * Keep override_acpi_psd()
>> Let us keep the original quirk and override_acpi_psd() function. Over
>>
Hi Rafael,
"Rafael J. Wysocki" writes:
> On Fri, Dec 4, 2020 at 11:45 PM Punit Agrawal wrote:
>>
>> Hi Rafael,
>>
>> Punit Agrawal writes:
>>
>> > Hi,
>> >
>> > While looking into Giovanni's patches to enable freque
Hi Wei,
Wei Huang writes:
> On 11/25/20 8:48 AM, Punit Agrawal wrote:
>> Re-factor the code to override the firmware provided frequency domain
>> information (via PSD) to localise the checks in one function.
>>
>> No functional change intended.
>>
>> S
Rob Herring writes:
[...]
>> > + gpio-ranges: true
>>
>> I am not sure I have a good handle on the yaml schema definitions but
>> "gpio-ranges" feels like it should be a list of ranges not a boolean.
>>
>> Something like -
>>
>> gpio-ranges:
>> maxItems: 1
>>
>> feels more appropr
interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> +};
> + };
> +...
FWIW,
Reviewed-by: Punit Agrawal
Thanks,
Punit
performance domains and again when matching cpus
belonging to the same domain.
Drop the unnecessary initialisation.
Signed-off-by: Punit Agrawal
---
drivers/acpi/processor_perflib.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/proce
Hi Rafael,
Punit Agrawal writes:
> Hi,
>
> While looking into Giovanni's patches to enable frequency invariance
> on AMD systems[0], I noticed an issue with initialising frequency
> domain information on a recent AMD APU.
>
> Patch 1 refactors the test to ignore f
4 are somewhat independent and a first step towards
improving the situation with regards to the use of raw identifiers for
AMD processors throughout the kernel.
All feedback welcome.
Thanks,
Punit
[0]
https://lore.kernel.org/linux-acpi/20201112182614.10700-1-ggherdov...@suse.cz/
Punit Agrawal
1 - 100 of 521 matches
Mail list logo
