rom DTS to the driver data is clear for me. I do
not know how to handle a board delay. Could you give me an example how it may
be implemented? Where this board related stuff could be placed?
--
--
Regards
Piotr Sroka
The 08/30/2019 11:46, Miquel Raynal wrote:
EXTERNAL MAIL
Hi Piotr,
Piotr Sroka wrote on Thu, 25 Jul 2019 16:00:12
+0100:
Subject should be: mtd: rawnand:
Last few nits in your driver which overall looks good (see below).
Now I'm waiting for Rob's ack on the bindings. This driver
Hi Miquel
The 08/30/2019 11:46, Miquel Raynal wrote:
EXTERNAL MAIL
Hi Piotr,
Piotr Sroka wrote on Thu, 25 Jul 2019 15:59:55
+0100:
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka
---
Changes for v5:
- replace "_" by "-" in all
The 09/13/2019 14:49, Miquel Raynal wrote:
EXTERNAL MAIL
Hi Piotr,
Piotr Sroka wrote on Wed, 11 Sep 2019 16:04:24
+0100:
Hi Miquel
The 08/30/2019 11:46, Miquel Raynal wrote:
>EXTERNAL MAIL
>
>
>Hi Piotr,
>
>Piotr Sroka wrote on Thu, 25 Jul 2019 15:59:55
>+0100:
>
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.t
Add new Cadence NAND driver to MTD subsystem
Signed-off-by: Piotr Sroka
---
Changes for v6:
- add support for bank addressing modified in HPNFC R013 version
- change type of data_control_supp and is_phy_type_dll from u8 to bool
- fix writing and reading data for HPNFC slave DMA interface
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka
Reviewed-by: Rob Herring
---
Changes for v6:
- add documentation for address-cells and size-cells
- remove not needed space
- put myself as maintainer of the Cadence nand driver bindings
Changes for v5
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.t
Add new Cadence NAND driver to MTD subsystem
Signed-off-by: Piotr Sroka
Reported-by: kbuild test robot
---
Changes for v7:
- replace readls with ioread32_rep and writesl with iowrite32_rep
to avoid compilation errors on parisc architecture
Changes for v6:
- add support for bank addressing
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka
Reviewed-by: Rob Herring
---
Changes for v7:
- none
Changes for v6:
- add documentation for address-cells and size-cells
- remove not needed space
- put myself as maintainer of the Cadence nand driver
kernel version 5.1.
Signed-off-by: Piotr Sroka
---
drivers/mtd/nand/raw/nand_base.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 5c2c30a7dffa..f64e3b6605c6 100644
--- a/drivers/mtd/nand/raw
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.t
The 09/25/2019 16:52, Piotr Sroka wrote:
Driver for Cadence HPNFC NAND flash controller.
HW DMA interface
Page write and page read operations are executed in Command DMA mode.
Commands are defined by DMA descriptors.
In CDMA mode controller own DMA engine is used (Master DMA mode).
Other
-Reply-To: <20190918123115.30510-1-pio...@cadence.com>
References: <20190918123115.30510-1-pio...@cadence.com>
TO: Piotr Sroka
CC: Kazuhiro Kasai , Piotr Sroka , Miquel Raynal , Richard Weinberger , David Woodhouse
, Brian Norris , Marek Vasut , Vignesh Raghavendra , Mauro Carvalho Chehab
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.t
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka
Reviewed-by: Rob Herring
---
Changes for v8:
- none
Changes for v7:
- none
Changes for v6:
- add documentation for address-cells and size-cells
- remove not needed space
- put myself as maintainer of the
Add new Cadence NAND driver to MTD subsystem
Signed-off-by: Piotr Sroka
Reported-by: kbuild test robot
Reported-by: Julia Lawall
---
Changes for v8:
- fix compilation waring in cadence_nand_attach_chip function
- change reallocating DMA common buffer to be done after all chips are
attached
Hello
The 09/19/2019 13:33, Schrempf Frieder wrote:
EXTERNAL MAIL
On 19.09.19 15:18, Miquel Raynal wrote:
Hello,
Schrempf Frieder wrote on Thu, 19 Sep
2019 13:15:08 +:
On 19.09.19 14:58, Miquel Raynal wrote:
Hi Piotr,
Piotr Sroka wrote on Thu, 19 Sep 2019 13:41:35
+0100:
Change
BBM flag is set and page parameter is 0. After that modification
way of discovering factory bad blocks will work similar as in kernel
version 5.1.
Cc: sta...@vger.kernel.org
Fixes: f90da7818b14 (mtd: rawnand: Support bad block markers in first, second
or last page)
Signed-off-by: Piotr Sroka
The 07/09/2019 08:48, Rob Herring wrote:
EXTERNAL MAIL
On Fri, Jun 14, 2019 at 04:13:01PM +0100, Piotr Sroka wrote:
Signed-off-by: Piotr Sroka
---
Changes for v3:
- add unit suffix for board_delay
- move child description to proper place
- remove prefix cadence_ for reg and sdma fields
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
dt-bindings: nand: Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.txt | 48 +
Signed-off-by: Piotr Sroka
---
Changes for v2:
- remove chip dependends parameters from dts bindings
- add names for register ranges in dts bindings
- add generic bindings to describe NAND chip representation
under the NAND controller node
---
.../bindings/mtd/cadence-nand-controller.txt
This patch adds driver for Cadence HPNFC NAND controller.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- create one universal wait function for all events instead of one
function per event.
- split one big function executing nand operations to separate
functions one per each type of
this parameter from cdns_nand.
I'm stopping here, but I think you got the idea: there's a lot of
duplicated code in this driver, try to factor this out or simplify the
logic.
Thans for review. I will try to simplify the rest of code by myself.
Regards,
Piotr Sroka
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
dt-bindings: nand: Add Cadence NAND driver
.../devicetree/bindings/mtd/cadence-nand.txt | 35 +
This patch adds driver for Cadence HPNFC NAND controller.
Signed-off-by: Piotr Sroka
---
drivers/mtd/nand/raw/Kconfig|8 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/cadence_nand.c | 2655 +++
drivers/mtd/nand/raw
Signed-off-by: Piotr Sroka
---
.../devicetree/bindings/mtd/cadence-nand.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand.txt
b
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.txt | 50 +
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka
---
Changes for v5:
- replace "_" by "-" in all properties
- change compatible name from cdns,hpnfc to cdns,hp-nfc
Changes for v4:
- add commit message
Changes for v3:
- add unit su
Add new Cadence NAND driver to MTD subsystem
Signed-off-by: Piotr Sroka
---
Changes for v5:
- fix "ecc config strength" field size
- remove unused macros
- fix address of timing2 register
- add guard for accessing data_control_size register
- simplify the driver by use the same funct
Hi Dmitry
The 06/16/2019 16:42, Dmitry Osipenko wrote:
EXTERNAL MAIL
14.06.2019 18:09, Piotr Sroka пишет:
Commit description is mandatory.
Signed-off-by: Piotr Sroka
---
[snip]
+
+/* Cadnence NAND flash controller capabilities get from driver data. */
+struct cadence_nand_dt_devdata
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.txt | 51 +
Add new Cadence NAND driver to MTD subsystem
Signed-off-by: Piotr Sroka
---
Changes for v4:
- fix comments issues like typos, missing capitals, missing dots etc.
- remove unnecessary PHY options phy_dll_aging and phy_per_bit_deskew
- replace all register access functions to "relaxed&quo
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka
---
Changes for v4:
- add commit message
Changes for v3:
- add unit suffix for board_delay
- move child description to proper place
- remove prefix cadence_ for reg and sdma fields
Changes for v2:
- remove
Hi Miquel
The 05/12/2019 14:24, Miquel Raynal wrote:
EXTERNAL MAIL
EXTERNAL MAIL
Hi Piotr,
Sorry for de delay.
Piotr Sroka wrote on Thu, 21 Mar 2019 09:33:58
+:
The 03/05/2019 19:09, Miquel Raynal wrote:
>EXTERNAL MAIL
>
>
>Hi Piotr,
>
>Piotr Sroka wrote on Tue,
Hi Rob
Thanks for reviwing this.
The 02/22/2019 14:40, Rob Herring wrote:
EXTERNAL MAIL
On Tue, Feb 19, 2019 at 04:19:20PM +, Piotr Sroka wrote:
Signed-off-by: Piotr Sroka
---
Changes for v2:
- remove chip dependends parameters from dts bindings
- add names for register ranges in dts
The 06/27/2019 18:15, Miquel Raynal wrote:
EXTERNAL MAIL
Hi Piotr,
Piotr Sroka wrote on Thu, 6 Jun 2019 16:19:51
+0100:
Hi Miquel
The 05/12/2019 14:24, Miquel Raynal wrote:
>EXTERNAL MAIL
>
>
>EXTERNAL MAIL
>
>
>Hi Piotr,
>
>Sorry for de delay.
>
>Piotr
The 07/01/2019 12:04, Miquel Raynal wrote:
EXTERNAL MAIL
Hi Piotr,
Piotr Sroka wrote on Mon, 1 Jul 2019 10:51:45
+0100:
[...]
>> >> >
>> >> >This driver is way too massive, I am pretty sure it can shrink a
>> >> >little bit more.
>> >&
The 03/05/2019 19:09, Miquel Raynal wrote:
EXTERNAL MAIL
Hi Piotr,
Piotr Sroka wrote on Tue, 19 Feb 2019 16:18:23
+:
This patch adds driver for Cadence HPNFC NAND controller.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- create one universal wait function for all events instead of
DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Add description of new DLL PHY delays.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- file was created in v2. It was a part of driver source file patch.
- most delays were moved from
Add polling for ACK to be sure that data are written to PHY register.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- fix indent
---
Changes for v3:
- none
---
Changes for v4:
- none
---
Changes for v5:
- use driver version from next branch, with applied enhanced strobe feature
support
Use added dev variable for devm_clk_get.
Signed-off-by: Piotr Sroka
---
Changes for v5:
- patch created in v5
---
drivers/mmc/host/sdhci-cadence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index
DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- dts part was removed from this patch
- most delays were moved from dts file
to data associated with an SoC specific compatible
Hi Masahiro
2017-03-21 08:3 AM Masahiro Yamada :
> Hi Piotr,
>
> 2017-03-21 16:01 GMT+09:00 Piotr Sroka :
> >
> > Hi Masahiro
> >
> > 2017-03-21 02:46 AM Masahiro Yamada :
> >> Hi Piotr,
> >>
> >>
> >> 2017-03-20 20:20 GMT+09:
Add polling for ACK to be sure that data are written to PHY register.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- fix indent
---
Changes for v3:
- none
---
drivers/mmc/host/sdhci-cadence.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host
DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- dts part was removed from this patch
- most delays were moved from dts file
to data associated with an SoC specific compatible
DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Add description of new DLL PHY delays.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- file was created in v2. It was a part of driver source file patch.
- most delays were moved from
ut I hope Adrian can advise us.
>
>
>
>
> > So maybe put all delays to dts file would be a better solution? What do you
> > think?
>
> I am OK with DT approach too
> because this way seems simpler, after all.
>
> (My suggestion for data array approach was misleading, sorry.)
>
Thanks for review anyway it was useful. Now decision between DTS and data array
is more clear for me.
Regards
Piotr Sroka
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 17 March, 2017 6:24 PM
> Subject: Re: [v3 3/3] mmc: sdhci-cadence: Update PHY delay configuration
>
>
>
> > @@ -62,10 +66,33 @@
> > */
> > #define SDHCI_CDNS_MAX_TUNING_LOOP 40
> >
> > +s
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 17 March, 2017 6:30 PM
> Subject: Re: [v3 2/3] Documentation: bindings: add description of PHY delays
> for sdhci-cadence
>
> Hi Piotr,
>
> 2017-03-17 21:40 GMT+
DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- dts part was removed from this patch
- most delays were moved from dts file
to data associated with an SoC specific compatible
DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Add description of new DLL PHY delays.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- file was created in v2. It was a part of driver source file patch.
- most delays were moved from
Add polling for ACK to be sure that data are written to PHY register.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- fix indent
---
Changes for v3:
- none
---
Changes for v4:
- none
---
drivers/mmc/host/sdhci-cadence.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff
;
>
> 2017-03-20 20:20 GMT+09:00 Piotr Sroka :
> > DTS properties are used instead of fixed data
> > because PHY settings can be different for different chips/boards.
> >
> > Signed-off-by: Piotr Sroka
>
>
> I found this version is a problem for me
Hi Masahiro
2017-03-21 02:46 AM Masahiro Yamada :
> Hi Piotr,
>
>
> 2017-03-20 20:20 GMT+09:00 Piotr Sroka :
> > DTS properties are used instead of fixed data
> > because PHY settings can be different for different chips/boards.
> >
> > Signed-off-by: Piotr
Hi Masahiro,
> Hi Piotr,
>
> 2017-03-20 17:47 GMT+09:00 Piotr Sroka :
> >
> >>
> >> > @@ -227,6 +267,7 @@ static int sdhci_cdns_probe(struct platform_device
> >> > *pdev)
> >> > struct sdhci_cdns_priv *priv;
> >> >
Hi Masahiro,
Thanks for all of your reviews.
Best Regards
Piotr Sroka
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 06 March, 2017 9:59 PM
> Subject: Re: [v3] mmc: sdhci-cadence: add HS400 enhanced strobe support
>
> Hi P
Hi Masahiro,
> -Original Message-
> Sent: 07 March, 2017 9:03 AM
> To: Piotr Sroka
> Subject: Re: [v2 PATCH 3/3] mmc: sdhci-cadence: Update PHY delay configuration
>
> Hi Piotr,
>
> 2017-03-06 22:39 GMT+09:00 Piotr Sroka :
> > PHY settings can be differe
Hi Masahiro
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 09 March, 2017 3:37 AM
> Subject: Re: [v2 PATCH 3/3] mmc: sdhci-cadence: Update PHY delay configuration
>
> Hi Piotr,
>
> 2017-03-07 20:00 GMT+09:00 Piotr
Add support for HS400ES mode to Cadence SDHCI driver.
Signed-off-by: Piotr Sroka
---
Changes in v2:
- Modify enhanced strobe function to handle disabling
enhanced strobe inside the function.
Do no relay on that mmc_set_ios() is called
immediately after host->ops->hs400_enhanced_
Add support for HS400ES mode to Cadence SDHCI driver.
Signed-off-by: Piotr Sroka
---
Changes in v2:
- Modify enhanced strobe function to handle disabling
enhanced strobe inside the function.
Do no relay on that mmc_set_ios() is called
immediately after host->ops->hs400_enhanced_
Add polling for ACK to be sure that data are written to PHY register.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- fix indent
---
drivers/mmc/host/sdhci-cadence.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc
PHY settings can be different for different platforms and SoCs.
Fixed PHY input delays was replaced with SoC specific compatible data.
DTS properties are used for configuration new PHY DLL delays.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- dts part was removed from this patch
- most delays
Add description of new DLL PHY delays.
Signed-off-by: Piotr Sroka
---
Changes for v2:
- file was created in v2. It was a part of driver source file patch.
- most delays were moved from dts file
to data associated with an SoC specific compatible
- description of delays was updated to be more
Fix the code to avoid changing bus width if HS400ES mode is selected.
Signed-off-by: Piotr Sroka
---
drivers/mmc/core/mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 7fd7228..c7d9c9f 100644
--- a/drivers/mmc/core
Hi Shawn
Thanks for the information.
Best Regards
Piotr Sroka
> -Original Message-
> From: Shawn Lin [mailto:shawn@rock-chips.com]
> Sent: 03 March, 2017 4:43 AM
> Subject: Re: [PATCH] mmc: core: fix changing bus witdh in hs400es mode
>
> Hi Poitr,
>
>
truct sdhci_cdns_priv *priv,
> > +static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
> > u8 addr, u8 data)
>
>
> If you have a chance to submit v2,
> I want the indent of the above line adjusted.
>
Ok thanks. I will fix the indent in v2.
Regards
Piotr Sroka
Add support for HS400ES mode to Cadence SDHCI driver.
Signed-off-by: Piotr Sroka
---
drivers/mmc/host/sdhci-cadence.c | 41 +---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
DTS properties are used instead of fixed data
because PHY settings can be different for different platforms.
Configuration of new three PHY delays were added
Signed-off-by: Piotr Sroka
---
.../devicetree/bindings/mmc/sdhci-cadence.txt | 54 ++
drivers/mmc/host/sdhci-cadence.c
Add polling for ACK to be sure that data are written to PHY register.
Signed-off-by: Piotr Sroka
---
drivers/mmc/host/sdhci-cadence.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 4b0ecb9
> -Original Message-
> From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> Sent: 16 February, 2017 4:10 PM
> Subject: Re: [PATCH 2/2] [2/2] mmc: sdhci-cadence: Update PHY delay
> configuration
>
> On 16 February 2017 at 14:06, Piotr Sroka wrote:
> > DTS pro
tor size. Therefore there is a separate
function for calculating ECC size for each of possible
sector size/step size.
Piotr Sroka (2):
Add new Cadence NAND driver to MTD subsystem
dt-bindings: nand: Add Cadence NAND controller driver
.../bindings/mtd/cadence-nand-controller.txt | 51 +
Signed-off-by: Piotr Sroka
---
Changes for v3:
- remove definitions of unused registres/
- remove configuring registers which are not excpected to be configured in
asynchronous mode
- remove not needed function reading timing registers
- remove information about oob size and write size from
Signed-off-by: Piotr Sroka
---
Changes for v3:
- add unit suffix for board_delay
- move child description to proper place
- remove prefix cadence_ for reg and sdma fields
Changes for v2:
- remove chip dependends parameters from dts bindings
- add names for register ranges in dts bindings
- add
Add calling sdhci_get_of_property function to parse sdhci properties.
Signed-off-by: Piotr Sroka
---
drivers/mmc/host/sdhci-cadence.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 7797e98..19d5698 100644
--- a
Hi Masahiro
2017-03-22 16:30 Masahiro Yamada :
> 2017-03-21 23:33 GMT+09:00 Piotr Sroka :
> > DTS properties are used instead of fixed data
> > because PHY settings can be different for different chips/boards.
> > Add description of new DLL PHY delays.
> >
>
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