generic I2C SCL Falling/Rising
bindings and System clock to compute its timings.
* I2C Device Tree Update
---
Pierre-Yves MORDRET (5):
dt-bindings: i2c-stm32: Document the STM32F7 I2C bindings
i2c: i2c-stm32f4: use generic definition of speed enum
i2c: i2c-stm32f7: add driver
ARM: dts
This patch adds I2C1 support for STM32F746 eval board
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Changes in V2
* Add SCL Rising/Falling time for eval board
---
arch/arm/boot/dts/stm32746g-eval.dts | 8
1 file changed, 8 insertions(+)
diff --
This patch adds the documentation of device tree bindings for STM32F7 I2C
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Change in V2
* Remove i2c-timing binding in order to use generic bindings SCL Rising
and Falling time instead
---
.../devic
This patch adds initial support for the STM32F7 I2C controller.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Changes in V2:
* Remove st,i2c-timing binding usage
* Implement an I2C timings computation algorithm instead of static
values(bin
This patch adds I2C1 support for STM32F746 SoC.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Changes in V2:
* Update I2C SoC device tree with latest Linux version
---
arch/arm/boot/dts/stm32f746.dtsi | 22 ++
1 file changed, 22 inser
This patch uses a more generic definition of speed enum for i2c-stm32f4
driver.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
Reviewed-by: Ludovic BARRE
---
drivers/i2c/busses/i2c-stm32.h | 20
drivers/i2c/busses/i2c-stm32f4.c
org/patch/9980965/
https://patchwork.kernel.org/patch/9980967/
Would you mind to test those ?
Thanks
> 2017-10-12 11:31 GMT+02:00 Pierre Yves MORDRET :
>>
>>
>> On 10/11/2017 01:53 PM, Radoslaw Pietrzyk wrote:
>>> Do not read data on RXNE but on BTF only due to HW
by: Pierre-Yves MORDRET
---
drivers/dma/stm32-mdma.c | 84
1 file changed, 50 insertions(+), 34 deletions(-)
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index d3be6bf..daa1602 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers
ness at your side
I will have to look at it closer.
Nonetheless I prefer to start from something more stable in term of clock before
investigating further.
Please let me know
Regards
> 2017-10-17 15:18 GMT+02:00 Pierre Yves MORDRET :
>>
>>
>> On 10/12/2017 11:55 AM, Radosław P
Acked-by: Pierre-Yves MORDRET
On 08/03/2018 09:19 AM, Huang Shijie wrote:
> Use dmaenginem_async_device_register to simplify the code:
> remove dma_async_device_unregister.
>
> Signed-off-by: Huang Shijie
> ---
> drivers/dma/stm32-mdma.c | 4 +---
> 1 file chang
This patch adds a generic DMA API to implement DMA support for i2c-stm32fx
drivers
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32.c
This patch adds SMBus support for I2C controller embedded in STM32F7 Soc.
All SMBus protocols are implemented except SMBus-specific protocols.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/b
Append new I2C STM32F7 feature set. This includes 10 bit support, slave
support, SMBBus protocols support, DMA Support and eventually an I2C recovery
mechanism.
resend after rebasing on last kernel.
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (6):
i2c: i2c-stm32f7
Feature prevents I2C lock-ups. Mechanism resets I2C state machine
and releases SCL/SDA signals but preserves I2C registers.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 32 +---
1 file
This patch adds DMA support for i2c-stm32f7 driver
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/Makefile | 3 +-
drivers/i2c/busses/i2c-stm32f7.c
This patch adds slave support for I2C controller embedded in STM32F7 SoC
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busses/i2c-stm32f7.c
This patch adds support for 10-bit device address for STM32F7 I2C
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 22 +-
1 file changed, 17 inser
Before assigning returned setup structure check if not null
Fixes: 463a9215f3ca7600b5ff ("i2c: stm32f7: fix setup structure")
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 4
1 file changed, 4
On 03/24/2018 11:43 PM, Wolfram Sang wrote:
> On Wed, Mar 21, 2018 at 05:48:55PM +0100, Pierre-Yves MORDRET wrote:
>> This patch adds support for 10-bit device address for STM32F7 I2C
>>
>> Signed-off-by: M'boumba Cedric Madianga
>> Signed-off-by: Pierre-Yves MOR
On 03/24/2018 11:49 PM, Wolfram Sang wrote:
> On Wed, Mar 21, 2018 at 05:48:57PM +0100, Pierre-Yves MORDRET wrote:
>> This patch adds SMBus support for I2C controller embedded in STM32F7 Soc.
>
>> All SMBus protocols are implemented except SMBus-specific protocols.
>
>
Thanks for the heads-up !
My driver supports DMA, but hardly used in the system.
But it's worth to mentioned it.
On 03/24/2018 11:51 PM, Wolfram Sang wrote:
> On Wed, Mar 21, 2018 at 05:48:58PM +0100, Pierre-Yves MORDRET wrote:
>> This patch adds a generic DMA API to implement D
On 03/24/2018 11:56 PM, Wolfram Sang wrote:
> On Wed, Mar 21, 2018 at 05:49:00PM +0100, Pierre-Yves MORDRET wrote:
>> Feature prevents I2C lock-ups. Mechanism resets I2C state machine
>> and releases SCL/SDA signals but preserves I2C registers.
>>
>> Signed-
On 03/25/2018 08:16 PM, Wolfram Sang wrote:
> On Wed, Mar 21, 2018 at 05:48:56PM +0100, Pierre-Yves MORDRET wrote:
>> This patch adds slave support for I2C controller embedded in STM32F7 SoC
>>
>> Signed-off-by: M'boumba Cedric Madianga
>> Signed-off-by: Pierre-
:
* Provide more details on what have already been implemented and
not implemented for SMBus protocols
* Raise DMA usage threshold
* s/recovery/release/ throughout the patch. Recovery is really
something else.
---
Pierre-Yves MORDRET (6):
i2c: i2c
call, Block write/read and Block write-block read
process call.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* fix Kbuild test robot issue (Unneeded semicolon)
v3:
* Provide more detai
Feature prevents I2C lock-ups. Mechanism resets I2C state machine
and releases SCL/SDA signals but preserves I2C registers.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* Don't use i2c engine recovery mechanism since driver
proc
This patch adds slave support for I2C controller embedded in STM32F7 SoC
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
v3:
---
---
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busse
This patch adds DMA support for i2c-stm32f7 driver
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* fix kbuild test robot issue (format)
v3:
* Raise DMA usage threshold
---
fixup! i2c
This patch adds support for 10-bit device address for STM32F7 I2C
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
v3:
---
---
drivers/i2c/busses/i2c-stm32f7.c | 22 +-
1 file ch
This patch adds a generic DMA API to implement DMA support for i2c-stm32fx
drivers
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
v3:
---
---
drivers/i2c/busses/i2c-stm32.c
Both buffer Transfer Length (TLEN if any) and transfer size have to be
aligned on burst size (burst beats*bus width).
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
---
---
drivers/dma/stm32-mdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Fix an issue with FIFO Size and burst size.
Fix an incomplete allocator for Hardware descriptors: memory badly
allocated.
---
Version history:
v1:
* Initial
v2:
* Fix kbuild warning format: /0x%08x/%pad/
---
Pierre-Yves MORDRET (2):
dmaengine: stm32-mdma: align TLEN and
Only 1 Hw Descriptor is allocated. Loop over required Hw descriptor for
proper allocation.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* Fix kbuild warning format: /0x%08x/%pad/
---
---
drivers/dma/stm32-mdma.c | 90
Hi Robin
On 04/11/2018 05:14 PM, Robin Murphy wrote:
> On 11/04/18 15:44, Pierre-Yves MORDRET wrote:
>> Both buffer Transfer Length (TLEN if any) and transfer size have to be
>> aligned on burst size (burst beats*bus width).
>>
>> Signed-off-by: Pierre-Yves MORDRET
&
On 04/13/2018 01:09 PM, Robin Murphy wrote:
> On 13/04/18 10:45, Pierre Yves MORDRET wrote:
>> Hi Robin
>>
>> On 04/11/2018 05:14 PM, Robin Murphy wrote:
>>> On 11/04/18 15:44, Pierre-Yves MORDRET wrote:
>>>> Both buffer Transfer Length (TLEN if any) an
* use of "offsetof" instead of explicit calculation
---
Pierre-Yves MORDRET (2):
dmaengine: stm32-mdma: align TLEN and buffer length on burst
dmaengine: stm32-mdma: Fix incomplete Hw descriptors allocator
drivers/dma/stm32-mdma.c | 98 -
Only 1 Hw Descriptor is allocated. Loop over required Hw descriptor for
proper allocation.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* Fix kbuild warning format: /0x%08x/%pad/
v3:
* use of "offsetof" instead o
Both buffer Transfer Length (TLEN if any) and transfer size have to be
aligned on burst size (burst beats*bus width).
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
v3:
* Get rid of while loop in favor of computed values
---
---
drivers/dma
think I have to get move this reset out of recovery API.
Please correct me whether I'm wrong
Slave Recovery mechanism is another story to implement in our platform since we
have to deal with GPIOs.
Let me know
Regards
On 03/19/2018 09:51 AM, Pierre Yves MORDRET wrote:
> Yes. Recovery m
Thanks for your quick answer
On 03/20/2018 10:42 AM, Wolfram Sang wrote:
> Hi,
>
>> Looking at the recovery API, this recovery is for slave and nothing else
>> with my
>> case. Therefore I think I have to get move this reset out of recovery API.
>
> Yes, you are correct. You need a custom funct
On 03/20/2018 10:52 AM, Wolfram Sang wrote:
>
>> I do believe the hw can support it, even it looks odd to me having the same
>> I2C
>> in slave and master mode at the same time.
>
> I2C is multi-master, so it is perfectly valid for a device to be master
> and slave. I do have seen designs maki
aster command on going.
IRqs are not separated neither Regs bits. The routing is done though out START
condition.
This driver is not slave-only driver and can act as master if a master command
is issued and slave if registered as such.
Hope it clarifies
Regards
On 03/20/2018 11:17 AM, Pierre Yves MO
Before assigning returned setup structure check if not null
Fixes: 463a9215f3ca7600b5ff ("i2c: stm32f7: fix setup structure")
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* fill "ret" with error statement be
---
Pierre-Yves MORDRET (6):
i2c: i2c-stm32f7: Add 10-bit address support
i2c: i2c-stm32f7: Add slave support
i2c: i2c-stm32f7: Add initial SMBus protocols support
i2c: i2c-stm32: Add generic DMA API
i2c: i2c-stm32f7: Add DMA support
i2c: i2c-stm32f7: Implement I2C recovery mechanism
This patch adds DMA support for i2c-stm32f7 driver
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* fix kbuild test robot issue (format)
---
fixup! i2c: i2c-stm32f7: Add DMA support
---
driver
This patch adds slave support for I2C controller embedded in STM32F7 SoC
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
---
---
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busses/i2c-stm3
This patch adds a generic DMA API to implement DMA support for i2c-stm32fx
drivers
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
---
---
drivers/i2c/busses/i2c-stm32.c
This patch adds support for 10-bit device address for STM32F7 I2C
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
---
---
drivers/i2c/busses/i2c-stm32f7.c | 22 +-
1 file change
This patch adds SMBus support for I2C controller embedded in STM32F7 Soc.
All SMBus protocols are implemented except SMBus-specific protocols.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* fix K
Feature prevents I2C lock-ups. Mechanism resets I2C state machine
and releases SCL/SDA signals but preserves I2C registers.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
v2:
* Don't use i2c engine recovery mechanism since driver
proc
>From now on, DMA bitfield is to manage DMA FIFO Threshold.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/stm32-dma.
When in cyclic mode, the configuration is updated after having started the
DMA hardware (STM32_DMA_SCR_EN) leading to incomplete configuration of
SMxAR registers.
Signed-off-by: Pierre-Yves MORDRET
Signed-off-by: Hugues Fruchet
---
Version history:
v1:
* Initial
---
---
drivers
Update the way Transfer Complete and Half Transfer Complete status are
acknowledge. Even if HTI is not enabled its status is shown when reading
registers, driver has to clear it gently and not raise an error.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
This bitfield intends to address features to be activated within the
driver. Initially the mask was only meant for FIFO Threshold management.
Backward compatibility is preserved but the meaning of this field has been
extended to features instead of only threshold.
Signed-off-by: Pierre-Yves
rst.
Signed-off-by: M'boumba Cedric Madianga
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 204 +---
1 file changed, 175 insertions(+), 29 deletions(-)
diff --git a/drivers/d
Fix typo in a comment and solved reported checkpatch warnings.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma
larly, the function stm32_dma_irq_clear() don't mask the input value
before shifting it, thus an incorrect input value could disable the
interrupts of adjacent channels.
Fixed by masking the input value before using it.
Signed-off-by: Pierre-Yves MORDRET
Signed-off-by: Antonio Borneo
---
Having 0 in item counter register is valid and stands for a "No or Ended
transfer". Therefore valid transfer starts from @+0 to @+0xFFFE leading to
unaligned scatter gather at boundary. Thus it's safer to round down this
value on its FIFO size (16 Bytes).
Signed-off-by: Pier
transfer to match FIFO Size
* Properly mask irq bits to avoid overlaping
* Fix incomplete configuration in cyclic mode
* Fix typo and reported checkpatch warnings
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (8):
dt-bindings: stm32-dma: introduce
-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dmamux.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/stm32-dmamux.c b/drivers/dma/stm32-dmamux.c
index 4dbb30c..b922db9 100644
--- a/drivers/dma/stm32
Both buffer Transfer Length (TLEN if any) and transfer size have to be
aligned on burst size (burst beats*bus width).
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Only 1 Hw Descriptor is allocated. Loop over required Hw descriptor for
proper allocation.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 90 ++--
1 file changed, 56 insertions
Fix an issue with FIFO Size and burst size.
Fix an incomplete allocator for Hardware descriptors: memory badly
allocated.
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (2):
dmaengine: stm32-mdma: align TLEN and buffer length on burst
dmaengine: stm32-mdma: Fix
This serie adds support for M2M transfer triggered by STM32 DMA in order to
transfer data from/to SRAM to/from DDR.
Normally, this mode should not be needed as transferring data from/to DDR
is supported by the STM32 DMA.
However, the STM32 DMA don't have the ability to generate burst transfer
on t
enable reuse to spare descriptors creation on critical UC.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 6b6e63b
From: M'boumba Cedric Madianga
Add one cell to support DMA/MDMA chaining.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
Documentation/devicetree/bindings/dma/stm32-dmamux.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
er is given by the formula:
(2 ^ order) * PAGE_SIZE.
The order is given by those 2 bits.
For cyclic, whether chaining is chosen, any value above 1 can be set :
SRAM buffer size will rely on period size and not on this DT value.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
From: M'boumba Cedric Madianga
This patch adds the description of the 2 properties needed to support M2M
transfer triggered by STM32 DMA when his transfer is complete.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
Documentation/devicetree/bin
Enable client to resubmit already processed descriptors
in order to save descriptor creation time.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 84 +++--
1 file changed, 54
red by HW.
This mode is not really available in dmaengine framework as normally M2M
transfers are triggered by SW.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 131 +--
1 file change
is used for this intermediate buffer
Each DMA channel will be able to define its SRAM needs to achieve chaining
feature : (2 ^ order) * PAGE_SIZE.
For cyclic, SRAM buffer is derived from period length (rounded on
PAGE_SIZE).
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1
er is given by the formula:
(2 ^ order) * PAGE_SIZE.
The order is given by those 2 bits.
For cyclic, whether chaining is chosen, any value above 1 can be set :
SRAM buffer size will rely on period size and not on this DT value.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
From: M'boumba Cedric Madianga
This patch adds the description of the 2 properties needed to support M2M
transfer triggered by STM32 DMA when his transfer is complete.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
v2:
* rework content
v1:
* In
nding content
v1:
* Initial
---
Pierre-Yves MORDRET (3):
dt-bindings: stm32-dma: Add DMA/MDMA chaining support bindings
dt-bindings: stm32-dmamux: Add one cell to support DMA/MDMA chain
dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings
dmaengine: stm32-dma: Add DMA
From: M'boumba Cedric Madianga
Add one cell to support DMA/MDMA chaining.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
v2:
* rework content
v1:
* Initial
---
---
Documentation/devicetree/bindings/dma/stm32-dmamux.txt | 6 +++---
1 file chang
Enable client to resubmit already processed descriptors
in order to save descriptor creation time.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
v2:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 84 +++--
1 file
red by HW.
This mode is not really available in dmaengine framework as normally M2M
transfers are triggered by SW.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
v2:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 131 +
enable reuse to spare descriptors creation on critical UC.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
v2:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32
is used for this intermediate buffer
Each DMA channel will be able to define its SRAM needs to achieve chaining
feature : (2 ^ order) * PAGE_SIZE.
For cyclic, SRAM buffer is derived from period length (rounded on
PAGE_SIZE).
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3
Hello all,
I've submitted a V3 following a KBuild warning.
You can thus drop this V2.
Thanks and sorry for the spamming.
Have a nice weekend.
Regards
On 09/28/2018 10:36 AM, Pierre-Yves MORDRET wrote:
> This serie adds support for M2M transfer triggered by STM32 DMA in order to
> tr
Hi Wolfram,
Sorry for the inconvenience.
I re-submit a v3 right now.
Thanks
On 11/27/18 1:10 PM, Wolfram Sang wrote:
> On Mon, Nov 19, 2018 at 12:04:24PM +0100, Pierre-Yves MORDRET wrote:
>> Use PM Runtime API to enable/disable clock
>>
>> Signed-off-by: Pierre-Yves MORDRET
Use PM Runtime API to enable/disable clock
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v3:
* Rebase
v2:
* missing define
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 144 +++
1 file changed, 101
Use PM Runtime API to enable/disable clock
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 142 +++
1 file changed, 99 insertions(+), 43 deletions(-)
diff --git a/drivers/i2c
Read SYSCFG bindings to set Fast Mode Plus bits if Fast Mode Plus
speed is selected.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 37 ++---
1 file changed, 34 insertions(+), 3
Append optional bindings to update SYSCFG Fast Mode Plus bits if
Fast Mode Plus speed is selected.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
Documentation/devicetree/bindings/i2c/i2c-stm32.txt | 6 ++
1 file changed, 6 insertions(+)
diff
Append optional bindings to update SYSCFG Fast Mode Plus bits if
Fast Mode Plus speed is selected.
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (2):
dt-bindings: i2c-stm32: SYSCFG Fast Mode Plus support for I2C STM32F7
i2c: i2c-stm32f7: SYSCFG Fast Mode Plus
Use pm_runtime engine for clock management purpose.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 58 +++--
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers
Use pm_runtime engine for clock management purpose
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 52 ++--
1 file changed, 46 insertions(+), 6 deletions(-)
diff --git a/drivers
Use pm_runtime engine for clock management purpose for both DMA, DMAMUX and
MDMA
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (3):
dmaengine: stm32-dma: Add PM Runtime support
dmaengine: stm32-dmamux: Add PM Runtime support
dmaengine: stm32-mdma: Add PM Runtime
Use pm_runtime engine for clock management purpose.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dmamux.c | 58 +-
1 file changed, 47 insertions(+), 11 deletions(-)
diff --git a/drivers
For avoiding false FIFO detection, check FIFO Error interrupt is
enabled prior raising any errors.
This will prevent having spurious FIFO error where it shouldn't.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c
Append optional bindings to update SYSCFG Fast Mode Plus bits if
Fast Mode Plus speed is selected.
---
Version history:
v2:
* solve some build issues
v1:
* Initial
---
Pierre-Yves MORDRET (2):
dt-bindings: i2c-stm32: SYSCFG Fast Mode Plus support for I2C STM32F7
i2c
Read SYSCFG bindings to set Fast Mode Plus bits if Fast Mode Plus
speed is selected.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v2:
* Missing header file inclusion
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 38
Append optional bindings to update SYSCFG Fast Mode Plus bits if
Fast Mode Plus speed is selected.
Signed-off-by: Pierre-Yves MORDRET
Reviewed-by: Rob Herring
---
Version history:
v2:
v1:
* Initial
---
---
Documentation/devicetree/bindings/i2c/i2c-stm32.txt | 6 ++
1 file
Use PM Runtime API to enable/disable clock
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v2:
* missing define
v1:
* Initial
---
---
drivers/i2c/busses/i2c-stm32f7.c | 144 +++
1 file changed, 101 insertions(+), 43 deletions
This enables drivers for STM32:
- DMAv2
- DMMAUX
- MDMA
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm
Use pm_runtime engine for clock management purpose.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c | 58 +++--
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers
Use pm_runtime engine for clock management purpose for both DMA, DMAMUX and
MDMA
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (3):
dmaengine: stm32-dma: Add PM Runtime support
dmaengine: stm32-dmamux: Add PM Runtime support
dmaengine: stm32-mdma: Add PM Runtime
For avoiding false FIFO detection, check FIFO Error interrupt is
enabled prior raising any errors.
This will prevent having spurious FIFO error where it shouldn't.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-dma.c
Use pm_runtime engine for clock management purpose
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 52 ++--
1 file changed, 46 insertions(+), 6 deletions(-)
diff --git a/drivers
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