-Original Message-
> From: Michal Marek [mailto:mma...@suse.cz]
> Sent: Monday, December 10, 2012 11:45 AM
> To: Noam Camus
> Cc: linux-kbu...@vger.kernel.org; linux-kernel@vger.kernel.org; Arnd Bergmann
> Subject: Re: Makefile race between jobs
> I see the problem no
From: Noam Camus
Seem like values assigned as absolute number and not and
shift value, i.e. should be 0 for one node (2^0) and 1 for
couple of nodes (2^1)
Signed-off-by: Noam Camus
---
arch/arc/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc
Ping...
-Original Message-
From: Noam Camus
Sent: Monday, July 18, 2016 10:06 AM
To: Pan Xinhui ; de...@googlers.com
Cc: b...@decadent.org.uk; da...@davemloft.net; a...@linux-foundation.org;
linux-kernel@vger.kernel.org
Subject: RE: [PATCH v3] lib/bitmap.c: enhance bitmap syntax
> F
From: Noam Camus
Today there are platforms with many CPUs (up to 4K).
Trying to boot only part of the CPUs may result in too long string.
For example lets take NPS platform that is part of arch/arc.
This platform have SMP system with 256 cores each with
16 HW threads (SMT machine) where HW
> From: Andrew Morton [mailto:a...@linux-foundation.org]
> Sent: Wednesday, September 14, 2016 1:54 AM
>> diff --git a/Documentation/kernel-parameters.txt
>> b/Documentation/kernel-parameters.txt
>> index 623502e..4f1e95b 100644
>> --- a/Documentation/kernel-parameters.txt
>> +++ b/Documentation
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Liav Rehana
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/kernel/entry-compact.S | 22 +++---
1 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry
From: Liav Rehana
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/mm/fault.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm
From: Noam Camus
This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
We override
From: Noam Camus
This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.
We noticed about 10% improvement of execution time with hackbench test.
Signed-off-by: Noam Camus
---
arch/arc/i
From: Noam Camus
Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.
Signed-off-by: Noam Camus
---
arch/arc/mm/tlbex.S |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm
From: Noam Camus
For User Mode Memory Bus Error some platforms do not creat interrupt
level 2 e.g. nps400 creates machine check exception.
Turning mem_service into weak symbol allows each platform to override
mem_service with its own implementation.
Signed-off-by: Noam Camus
---
arch/arc
From: Noam Camus
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/plat-eznps/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps
From: Noam Camus
When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can
From: Noam Camus
This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
When this feature is enabled low values of this counter cause
downgrade in performance and in the worst case even a livelock.
Remove those couple of lines and resort to HW reset
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Noam Camus
Change Log
---
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.
With this patch set I continue the effort of up
From: Noam Camus
v6 change:
Adapt patch to latest version (nothing functional)
v5 change:
Two patches is now squashed into single one
v4 change
Remove patch for skipping looptest through DT option.
This is now handled in our simulator model.
Thanks to Vineet Gupta from Synopsys for his help
From: Noam Camus
Add support for UPIO_MEM32BE in addition to UPIO_MEM32.
dw8250_serial_out32() extra functionality that is not part of
the 8250 core driver was moved to new function called
dw8250_check_LCR().
For big endian we use 2 new accessors similar to little endian,
called
From: Noam Camus
v7 change:
Fix build warning due to redundant "const" qualifier at
_dw8250_serial_in32be() signature.
v6 change:
Adapt patch to latest version (nothing functional)
v5 change:
Two patches is now squashed into single one
v4 change
Remove patch for skipping looptest
From: Noam Camus
Add support for UPIO_MEM32BE in addition to UPIO_MEM32.
dw8250_serial_out32() extra functionality that is not part of
the 8250 core driver was moved to new function called
dw8250_check_LCR().
For big endian we use 2 new accessors similar to little endian,
called
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: Sunday, October 18, 2015 7:06 AM
> This patch still doesn't apply at all to my tty-next branch, what are you
> making it against?
> Please fix it up and resend.
The patch is against v4.3-rc4
I will update to rc5
From: Noam Camus
Add support for UPIO_MEM32BE in addition to UPIO_MEM32.
dw8250_serial_out32() extra functionality that is not part of
the 8250 core driver was moved to new function called
dw8250_check_LCR().
For big endian we use 2 new accessors similar to little endian,
called
-by: Noam Camus
Signed-off-by: Tal Zilcer
Acked-by: Alexey Brodkin
---
Chahges in patch v2,v3:
1) Did some renaming:
a) EZCHIP_NPS_LAN to EZCHIP_NPS_MANAGEMENT_ENET
b) nps_enet to nps_mgt_enet
2) Update GPL to version 2
3) Remove driver default configuration (y)
4) Change integer
From: Noam Camus
Simple LAN device for debug or management purposes.
Device supports interrupts for RX and TX(completion).
Device does not have DMA ability.
Signed-off-by: Noam Camus
Signed-off-by: Tal Zilcer
Acked-by: Alexey Brodkin
---
Change log for v4:
1) replace macros with generic ones
From: Noam Camus
Simple LAN device for debug or management purposes.
Device supports interrupts for RX and TX(completion).
Device does not have DMA ability.
Signed-off-by: Noam Camus
Signed-off-by: Tal Zilcer
Acked-by: Alexey Brodkin
---
Change log for v5:
Basically its all based on Florian
From: David Miller [mailto:da...@davemloft.net]
Sent: Sunday, June 21, 2015 7:22 PM
> This builds with several warnings and also doesn't compile.
>
> drivers/net/ethernet/ezchip/nps_enet.c: In function ‘nps_enet_read_rx_fifo’:
> drivers/net/ethernet/ezchip/nps_enet.c:43:24: warning: cast from poi
From: Noam Camus
Simple LAN device for debug or management purposes.
Device supports interrupts for RX and TX(completion).
Device does not have DMA ability.
Signed-off-by: Noam Camus
Signed-off-by: Tal Zilcer
Acked-by: Alexey Brodkin
---
Change log for v6:
Below changes are in response for
From: Mahesh Bandewar [mailto:mahe...@google.com]
Sent: Monday, June 22, 2015 8:45 PM
> > a/drivers/net/ethernet/ezchip/Kconfig
> > b/drivers/net/ethernet/ezchip/Kconfig
> > new file mode 100644
> > index 000..d031177
> > --- /dev/null
> > +++ b/drivers/net/ethernet/ezchip/Kconfig
> > @@ -0,
From: Noam Camus
Simple LAN device for debug or management purposes.
Device supports interrupts for RX and TX(completion).
Device does not have DMA ability.
Signed-off-by: Noam Camus
Signed-off-by: Tal Zilcer
Acked-by: Alexey Brodkin
---
Change log for v7:
1) Update nps_enet_open() comment
Andreas Dilger suggested that my previous email may be discarded due to my
Sender Policy Framework (SPF) .
So I email this from different location, just in case.
Noam
From: Noam Camus
Sent: Tuesday, June 9, 2015 3:32 PM
To: linux-fsde...@vger.kernel.org
From: Noam Camus
Today bss/heap is placed above last loaded sections.
However if STACK_TOP is not equal to TASK_SIZE we wish to ignore
such sections mapped to this gap between STACK_TOP and TASK_SIZE.
set_brk will never work for such case.
So at the moment this addition is just a sanity check
-by: Noam Camus
---
.../devicetree/bindings/net/ezchip_enet.txt| 15 +
drivers/net/ethernet/Kconfig |1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/ezchip/Kconfig| 30 +
drivers/net/ethernet/ezchip/Makefile
-by: Noam Camus
Signed-off-by: Tal Zilcer
Acked-by: Alexey Brodkin
---
.../devicetree/bindings/net/ezchip_enet.txt| 15 +
drivers/net/ethernet/Kconfig |1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/ezchip/Kconfig
From: Noam Camus
Structure name and variable name were erroneously interchanged
Signed-off-by: Noam Camus
---
arch/arc/mm/cache_arc700.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 4670afc..22df2d1
From: Peter Hurley [mailto:pe...@hurleysoftware.com]
Sent: Wednesday, July 22, 2015 3:19 PM
> This is not an adequate changelog.
> Please describe the refactoring.
I will in my v2 patch set
Noam
From: Peter Hurley [mailto:pe...@hurleysoftware.com]
Sent: Wednesday, July 22, 2015 3:41 PM
>> diff --git a/drivers/tty/serial/8250/8250_dw.c
>> b/drivers/tty/serial/8250/8250_dw.c
>> index d48b506..fe0b487 100644
>> --- a/drivers/tty/serial/8250/8250_dw.c
>> +++ b/drivers/tty/serial/8250/8250_d
From: Peter Hurley [mailto:pe...@hurleysoftware.com]
Sent: Wednesday, July 22, 2015 3:21 PM
>>On 07/22/2015 05:34 AM, Noam Camus wrote:
>> From: Noam Camus
>>
>> Add support for OF option "no-loopback-test"
> Changes to devicetree need to at least get acks
From: Peter Hurley [mailto:pe...@hurleysoftware.com]
Sent: Wednesday, July 22, 2015 3:39 PM
>> +/* Writing to LCR may cause BUSY interrupt before we
>> + * register the IRQ line.
>> + * Currently autoconf() uses several writes to LCR.
>> + * In order to avoid calling to autoconf()
From: Peter Hurley [mailto:pe...@hurleysoftware.com]
Sent: Wednesday, July 22, 2015 3:52 PM
> Subject: Re: [PATCH 4/4] serial: 8250_dw: use serial_in() and not readl()
> From: Noam Camus
>
> This is now matches device endianness.
> I'm not seeing where serial_in() is used
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Thursday, July 09, 2015 9:21 AM
>
> Commit ed71871bed719 ("tty/8250_early: Turn serial_in/serial_out into weak
> symbols") made these
> routines weak to allow platform specific Big endian override
>
> However recent updates to core,
From: Noam Camus
v5 change:
Two patches is now squashed into single one
v4 change
Remove patch for skipping looptest through DT option.
This is now handled in our simulator model.
Thanks to Vineet Gupta from Synopsys for his help.
We are left with 2 patches which adds BIG endian support.
V3
From: Noam Camus
Add support for UPIO_MEM32BE in addition to UPIO_MEM32.
dw8250_serial_out32() extra functionality that is not part of
the 8250 core driver was moved to new function called
dw8250_check_LCR().
For big endian we use 2 new accessors similar to little endian,
called
From: Noam Camus
Today bss/heap is placed above last loaded sections.
Current check is only against TASK_SIZE, maybe since most architectures do:
But this is not true for all of them and a gap between TASK_SIZE
and STACK_TOP is possible and may be used for variant purposes.
For example we use
From: Noam Camus
Today bss/heap is placed above last loaded sections.
Current check is only against TASK_SIZE, maybe since most architectures do:
#define STACK_TOP TASK_SIZE
But this is not true for all of them and a gap between TASK_SIZE
and STACK_TOP is possible and may be used for
From: David Miller [mailto:da...@davemloft.net]
Sent: Monday, August 17, 2015 8:36 PM
> You should not move TX completion out of NAPI handling, NAPI poll is exactly
> where it belongs.
>
> If you handle it in hardware interrupt context you have to use
> dev_kfree_skb_irq() which defers the oper
From: Noam Camus
Change v2
TX done is handled back with NAPI poll.
Change v1
This patch set is a bunch of fixes to make nps_enet work correctly with
all platforms, i.e. real device, emulation system, and simulation system.
The main trigger for this patch set was that in our emulation system
the
From: Noam Camus
When interrupt is received we read directly from control
register for RX/TX instead of reading cause register
since this register fails to indicate TX done when
TX interrupt is "edge mode".
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_ene
From: Noam Camus
We set controller to drop control frames and not trying
to pass them on. This is only needed for debug reasons.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net
From: Noam Camus
We need to set tx_skb pointer before send frame.
If we receive interrupt before we set pointer we will try
to free SKB with wrong pointer.
Now we are sure that SKB pointer will never be NULL during
handling TX done and check is removed.
Signed-off-by: Noam Camus
---
drivers
From: Noam Camus
We define buf_int_enable in the minimal namespace it is used.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/ezchip/nps_enet.c
b/drivers/net/ethernet
From: Noam Camus
This is needed for when TX done interrupt is in
"level mode".
For example it is true for some simulators of this device.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/d
From: Noam Camus
This patch set is a bunch of fixes to make nps_enet work correctly with
all platforms, i.e. real device, emulation system, and simulation system.
The main trigger for this patch set was that in our emulation system
the TX end interrupt is "edge-sensitive" and therefore
From: Noam Camus
TX handler is minimalistic and there is no need to schedule
a NAPI job.
Tx done will be processed during hardware interrupt context.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c | 17 ++---
1 files changed, 10 insertions(+), 7 deletions
From: Noam Camus
When interrupt is received we read directly from control
register for RX/TX instead of reading cause register
since this register fails to indicate TX done when
TX interrupt is "edge mode".
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_ene
From: Noam Camus
We need to set tx_skb pointer before send frame.
If we receive interrupt before we set pointer we will try
to free SKB with wrong pointer.
Now we are sure that SKB pointer will never be NULL during
handling TX done and check is removed.
Signed-off-by: Noam Camus
---
drivers
From: Noam Camus
We set controller to drop control frames and not trying
to pass them on. This is only needed for debug reasons.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net
From: Noam Camus
We define buf_int_enable in the minimal namespace it is used.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/ezchip/nps_enet.c
b/drivers/net/ethernet
From: Noam Camus
This is needed for when TX done interrupt is in
"level mode".
For example it is true for some simulators of this device.
Signed-off-by: Noam Camus
---
drivers/net/ethernet/ezchip/nps_enet.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/d
>From: Daniel Lezcano
>Sent: Friday, December 4, 2015 10:07 AM
>>
>> diff --git a/Documentation/devicetree/bindings/arc/eznps.txt
>> b/Documentation/devicetree/bindings/arc/eznps.txt
>> new file mode 100644
>> index 000..f8b5e9b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arc/
>From: Daniel Lezcano
>Sent: Friday, December 4, 2015 11:13 AM
>> +obj-$(CONFIG_ARC_PLAT_EZNPS) += timer-nps.o
>CONFIG_CLKSRC_NPS
I wish this driver to be build only for this specific ARC platform.
This clock source is embedded in our SoC.
It is not meant to be built for any other architecture.
T
From: Marc Zyngier [mailto:marc.zyng...@arm.com]
Sent: Thursday, December 03, 2015 8:34 PM
>>> Silly question: why cannot you just write the actual instruction
>>> instead of shoving the instruction like this? Also, .inst would be
>>> more appropriate...
&g
From: Noam Camus
v4:
1) irqchip -- use irq_domain_add_linear()
2) clocksource -- use of_clk_get()
3) New header at include/soc use by platform and drivers
4) update DTS file for above fixed drivers
v3:
1) irqchip: use MACROS instead of structures to decribe
registers.
2
From: Noam Camus
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus
---
include/soc/nps/common.h | 123 ++
1
From: Noam Camus
We add IPI irq definition to be used later by any
irqchip such NPS400 IC.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/irq.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 4fd7d62
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc
From: Noam Camus
If we hold rwlock and interrupt occures we may
end up spinning on it for ever during softirq.
Note that this lock is an internal lock
and since the lock is free to be used from any context,
the lock needs to be IRQ-safe.
Below you may see an example for interrupt we get while
From: Noam Camus
User space use lower 2G of the virtual address space.
However kernel steals upper 512M of this space.
This stolen space is used partially for vmalloc and the rest
serves as gutter between kernel and user space.
The vmalloc size is depend on NR_CPUS since "per cpu" mec
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by
From: Noam Camus
External clock source can be used if included by one of
DTS file of a chosen platform.
Clocksource may be depend on some clk from DTS as the
real source of this clock.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/kernel/time.c | 10 +-
1 files
From: Noam Camus
In SMP setup, master loops for each_present_cpu calling cpu_up().
For ARC it returns as soon as new cpu's status becomes online,
However secondary may still do HW initializing,
machine or platform hook level.
So turn secondary online only after all HW setup is done.
Signe
From: Noam Camus
Adding default configuration file and DTS file
Signed-off-by: Noam Camus
---
arch/arc/boot/dts/eznps.dts| 93
arch/arc/configs/nps_defconfig | 85
2 files changed, 178 insertions(+), 0
From: Noam Camus
This platform include boards:
Hardware Emulator (HE)
Simulator based upon nSIM.
Signed-off-by: Noam Camus
---
MAINTAINERS |6 +
arch/arc/plat-eznps/Kconfig | 34 ++
arch/arc/plat-eznps/Makefile
From: Noam Camus
NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device
From: Noam Camus
NPS use special mapping right below TASK_SIZE.
Hence we need to lower STACK_TOP so that user stack won't
overlap NPS special mapping.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/processor.h | 17 +
arch/arc/mm/
From: Noam Camus
With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support up to 4096 CPUs.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h |8
arch/arc/kerne
-off-by: Noam Camus
Cc: Peter Zijlstra
Acked-by: Vineet Gupta
---
arch/arc/include/asm/processor.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 41142ab..974b878 100644
--- a/arch/arc
From: Noam Camus
The default 256 bytes sometimes is just not enough.
We usually provide earlycon=... and console=... and ip=...
All this and more may need more room.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/setup.h |4
1 files changed, 4 insertions
From: Noam Camus
This commit should be left last since only now eznps platform
is in state which one can actually use.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig |1 +
arch/arc/Makefile |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arc/Kconfig b
From: Noam Camus
This will better reflect its description i.e. "any needed setup..."
and not just do an "IPI request".
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/smp.h |4 ++--
arch/arc/kernel/irq.c |4 ++--
arch/arc/kern
From: Noam Camus
We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h | 79 +++-
arch
From: Noam Camus
Add EZchip to vendor prefixes list.
EZchip introduce the NPS platform for the ARC architecture.
Signed-off-by: Noam Camus
Acked-by: Rob Herring
Cc: Pawel Moll
---
Documentation/devicetree/bindings/arc/eznps.txt|7 +++
.../devicetree/bindings/vendor-prefixes.txt
From: Marc Zyngier [mailto:marc.zyng...@arm.com]
Sent: Wednesday, December 16, 2015 11:31 AM
>> +static int __init nps400_of_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> +if (parent)
>> +panic("DeviceTree incore ic not a root
>From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>Sent: Friday, December 18, 2015 1:21 PM
>> I need this for my per CPU irqs such timer and IPI which do not come
>> from some external device but from CPUs. For these IRQs I am calling
>> to irq_create_mapping() from my platform at arch/arc and
>From: Thomas Gleixner [mailto:t...@linutronix.de]
>Sent: Saturday, November 07, 2015 1:26 PM
>So that clocksource goes up to 1GHz. That means u32 fits ~4.29 seconds. Unless
>you are striving for NOHZ idle sleep times above that there is no point in
>doing that 64bit dance.
>
>The timekeeping
From: Noam Camus
v3:
1) irqchip: use MACROS instead of structures to decribe
registers.
2) clocksource: use 32bit counter and avoid 2 halfs read
of 64bit dance.
v2:
1) Remove out of tree platform include path
2) Move atomic/bitop/cmpxchg for platform to end
From: Noam Camus
Add EZchip to vendor prefixes list.
EZchip introduce the NPS platform for the ARC architecture.
Signed-off-by: Noam Camus
Acked-by: Rob Herring
Cc: Pawel Moll
---
Documentation/devicetree/bindings/arc/eznps.txt|7 +++
.../devicetree/bindings/vendor-prefixes.txt
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc
From: Noam Camus
We add IPI irq definition to be used later by any
irqchip such NPS400 IC.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/irq.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 4fd7d62
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by
From: Noam Camus
This will better reflect its description i.e. "any needed setup..."
and not just do an "IPI request".
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/smp.h |4 ++--
arch/arc/kernel/irq.c |4 ++--
arch/arc/kern
From: Noam Camus
User space use lower 2G of the virtual address space.
However kernel steals upper 512M of this space.
This stolen space is used partially for vmalloc and the rest
serves as gutter between kernel and user space.
The vmalloc size is depend on NR_CPUS since "per cpu" mec
From: Noam Camus
External clock source can be used if included by one of
DTS file of a chosen platform.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/kernel/time.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arc/kernel/time.c b/arch/arc
From: Noam Camus
In SMP setup, master loops for each_present_cpu calling cpu_up().
For ARC it returns as soon as new cpu's status becomes online,
However secondary may still do HW initializing,
machine or platform hook level.
So turn secondary online only after all HW setup is done.
Signe
From: Noam Camus
We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h | 79 +++-
arch
From: Noam Camus
Adding default configuration file and DTS file
Signed-off-by: Noam Camus
---
arch/arc/boot/dts/eznps.dts| 76 +++
arch/arc/configs/nps_defconfig | 85
2 files changed, 161 insertions(+), 0
-off-by: Noam Camus
Cc: Peter Zijlstra
Acked-by: Vineet Gupta
---
arch/arc/include/asm/processor.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 41142ab..974b878 100644
--- a/arch/arc
From: Noam Camus
With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support up to 4096 CPUs.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h |8
arch/arc/kerne
From: Noam Camus
This commit should be left last since only now eznps platform
is in state which one can actually use.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig |1 +
arch/arc/Makefile |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arc/Kconfig b
From: Noam Camus
The default 256 bytes sometimes is just not enough.
We usually provide earlycon=... and console=... and ip=...
All this and more may need more room.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/setup.h |4
1 files changed, 4 insertions
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