From: Niklas Cassel
artpec6_add_pcie_port is called from artpec6_pcie_probe.
artpec6_pcie_probe does not have the __init section marker.
It is wrong to have the marker on artpec6_add_pcie_port
when the marker is not on artpec6_pcie_probe.
Signed-off-by: Niklas Cassel
---
drivers/pci/host/pcie
From: Niklas Cassel
- Increase config size. When using a PCIe switch,
the previous config size only had room for one device.
- Add bus range. Inherited optional property.
- Map downstream I/O to PCI address 0. We can map it to any
address, but let's be consistent with other dr
pointer from the first descriptor to the last
descriptor, a skb will get freed only when the IP has cleared the
own bit of all the descriptors that are using that skb.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 20
1 file changed, 16
On 10/13/2017 06:42 PM, David Laight wrote:
> From: Behalf Of Niklas Cassel
>> Sent: 13 October 2017 17:09
>> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
>> to write to this location, the proper way to get the address to this this
>> locati
On 10/13/2017 06:43 PM, Jingoo Han wrote:
> On Friday, October 13, 2017 12:09 PM, Niklas Cassel wrote:
>>
>> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
>> to write to this location, the proper way to get the address to this this
>> locati
On 10/13/2017 06:47 PM, Jingoo Han wrote:
> On Friday, October 13, 2017 12:09 PM, Niklas Cassel wrote:
>>
>> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
>> to write to this location, the proper way to get the address to this this
>> locati
On 10/13/2017 06:09 PM, Niklas Cassel wrote:
(snip)
Hello Kishon
I just wanted to say that the function
artpec6_pcie_calc_cpu_fixup_mask should work on dra7xx
as well. (I had dra7xx in mind when I wrote it.)
However, I did not want to change pci-dra7xx.c to
also use this function, since your
On 10/31/2017 07:01 AM, Kishon Vijay Abraham I wrote:
> Hi Niklas,
>
> On Monday 30 October 2017 06:12 PM, Niklas Cassel wrote:
>> Certain SoCs need to map the MSI address in raise_irq.
>> To map an address, you first need to call pci_epc_mem_alloc_addr,
>> however, p
On 10/31/2017 07:22 AM, Kishon Vijay Abraham I wrote:
(snip)
>> --- a/drivers/pci/dwc/pcie-designware.h
>> +++ b/drivers/pci/dwc/pcie-designware.h
>> @@ -106,6 +106,8 @@
>> #define MSI_CAP_MME_MASK(7 << MSI_CAP_MME_SHIFT)
>> #define MSI_MESSAGE_ADDR_L320x54
>> #defi
On 10/31/2017 09:29 AM, Kishon Vijay Abraham I wrote:
(snip)
>>
>> +#ifdef CONFIG_PCI_DRA7XX_HOST
>
> This block can also be moved around the file so that there is a single +#ifdef
> CONFIG_PCI_DRA7XX_HOST in this file.
Hello Kishon,
Sure, will fix in V3.
>> static int __init dra7xx_add_pc
>>>
>>> static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>>> {
>>> @@ -681,6 +697,7 @@ static int __init dra7xx_pcie_probe(struct
>>> platform_device *pdev)
>>> dra7xx->link_gen = 2;
>>>
>>> switch (mode) {
>>> +#ifdef CONFIG_PCI_DRA7XX_HOST
>>> case DW_P
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control
register, thus overwriting the PCI_MSI_FLAGS_64BIT bit.
By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI
on systems where the RC has set a 64 bit MSI address.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers
ent should definitely be in dra7xx_add_pcie_port().
This is also needed to be able to compile host/ep mode specific code
independently.
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
V3:
* Added Kishon's ack.
drivers/pci/dwc/pci-dra7xx.c | 6 ++
1 file changed, 2 in
Certain registers that pcie-designware-ep tries to write are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-designware-ep.c | 8
1 file changed, 8
This function can be used by all DWC based controllers to raise a MSI
irq. However, certain controllers, like DRA7xx, has a special
convenience register for raising MSI irqs that doesn't require you to
explicitly map the MSI address.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
dr
This is done to better match other drivers such as dra7xx and imx6,
but also to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-artpec6.c | 53 +++---
1 file changed, 29 insertions(+), 24 deletions
This way pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar().
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
V3:
* Added Kishon's ack.
drivers/pci/dwc/pci-dra7xx.c | 9 -
drivers/pci/dwc/pcie-designware-ep.c | 2 +-
drivers/pci/dwc
specific code inside a single ifdef block.
Signed-off-by: Niklas Cassel
---
V3:
* Fixed commit message.
* Moved functions in order to have just a single ifdef for host,
and a single ifdef for ep.
* Removed ifdefs around match table and match table data.
* Removed ifdefs in probe, use dummy
Signed-off-by: Niklas Cassel
---
V3:
* Removed ifdefs around match table and match table data.
* Removed ifdefs in probe, use dummy implementations instead.
drivers/pci/dwc/Kconfig| 23 --
drivers/pci/dwc/pcie-artpec6.c | 162 +++--
2 files
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V3:
* No change.
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 2 ++
1 file changed, 2
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
V3:
* Now when there are no ifdefs around the match table entries,
sort them by SoC.
drivers/pci/dwc/pcie-artpec6.c | 162
.
This also fixes a bug for ARTPEC-6, where the cpu to bus address
fixup mask previously was off by one (GENMASK(27, 0), rather than
GENMASK(28, 0)), which is another reason why the it is a good idea
to calculate the mask by using values from device tree.
Signed-off-by: Niklas Cassel
---
V3:
* No
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V3:
* No change.
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
b/Documentation/devicetree
The previous handling was a bit unorthodox and would have been a bit
bloated once more DWC based controllers added support for ep mode.
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
V3:
* Added Kishon's ack.
drivers/pci/dwc/Kconfig
This greatly improves readability.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index
that it will work on all systems.
This is essentially the same thing as allocating a buffer in a driver,
to which the endpoint will write to. To do this, we use the DMA API.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-designware-host.c | 15 ---
drivers/pci
e_irq, instead we pre-allocate
a page in dw_pcie_ep_init, so this page can later be used to map/unmap
the MSI address in raise_irq.
Signed-off-by: Niklas Cassel
---
V3:
* Use ep->page_size rather than PAGE_SIZE.
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware.h
-dra7xx to better prepare for endpoint mode in other
DWC based PCIe drivers.
New in V3:
Fixed all review comments, for detailed changes, see the changelog
in each patch.
Niklas Cassel (17):
PCI: dwc: Use DMA-API for allocating MSI data
PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC
On 10/31/2017 10:38 PM, Niklas Cassel wrote:
>>>>
>>>> static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>>>> {
>>>> @@ -681,6 +697,7 @@ static int __init dra7xx_pcie_probe(struct
>>>> platform_device *pdev)
>&
irqs that are always enabled are:
LPI and PMT.
Looking at dwmac4_core.c, the irqs that are always enabled are:
PMT.
To be able to read the LPI irq status, we need to enable the LPI
irq also for dwmac4.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7
s that are always enabled are:
LPI and PMT.
Looking at dwmac4_core.c, the irqs that are always enabled are:
PMT.
To be able to read the LPI irq status, we need to enable the LPI
irq also for dwmac4.
Signed-off-by: Niklas Cassel
---
Changes since v1:
Fixed two typos in the commit message.
On 11/02/2017 10:13 AM, Arnd Bergmann wrote:
> On Tue, Oct 31, 2017 at 11:39 PM, Niklas Cassel
> wrote:
>> Signed-off-by: Niklas Cassel
>
> It seems like you are missing a changelog text. Please explain what
> your work is good for
> in any patch you send.
You ar
-dra7xx to better prepare for endpoint mode in other
DWC based PCIe drivers.
New in V4:
Fixed all commit messages so that they are readable without the title.
Replaced ifdefs in pci-dra7xx and pcie-artpec6 by using the
IS_ENABLED macro. (Thanks Arnd!)
Niklas Cassel (17):
PCI: dwc: Use the DMA-API to
Remove the static keyword from dw_pcie_ep_reset_bar() so that
pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar().
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 9 -
drivers/pci/dwc/pcie-designware-ep.c | 2
Split artpec6_pcie_establish_link() into smaller functions
to better match other drivers such as dra7xx and imx6.
This is also done to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 53 +++---
1 file
Refactor the Kconfig and Makefile handling for host/ep mode, since
the previous handling was a bit unorthodox and would have been a bit
bloated once more DWC based controllers added support for ep mode.
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig
silently dropped by the compiler,
including static functions and structures that are referenced indirectly
from there.
Suggested-by: Arnd Bergmann
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pci-dra7xx.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/dwc/pci-dra7xx.c
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/Kconfig| 23 +--
drivers/pci/dwc/pcie-artpec6.c | 152
Use BIT and GENMASK macros to improve readability.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index
Add support for the ARTPEC-7 SoC in the artpec6 driver.
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/axis
.
This also fixes a bug for ARTPEC-6, where the cpu to bus address
fixup mask previously was off by one (GENMASK(27, 0), rather than
GENMASK(28, 0)). This is another reason to calculate the mask by
using values from device tree.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pci-dra7xx.c
Add support for the ARTPEC-7 SoC in the artpec6 driver.
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 162
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 3 -
to struct dw_pcie,
the pp->ops assignment should definitely be in dra7xx_add_pcie_port().
This is done so that the compiler (in a later commit) can remove more
code when enabling only one of the two supported modes (host/ep) in
the dra7xx driver.
Signed-off-by: Niklas Cassel
Acked-by: Kishon
ivers will
not use this generic function, even if they can.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 34 ++
drivers/pci/dwc/pcie-designware.h| 9 +
2 files changed, 43 insertions(+)
diff --git a/drivers/pci/dwc/pcie-desig
Certain registers that pcie-designware-ep tries to write to are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after
writing these registers.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie
e_irq.
Pre-allocate a page in dw_pcie_ep_init(), so that this page can later
be used to map/unmap the MSI address in raise_irq.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware.h| 2 ++
2 files changed, 12 insertions(+)
. To do this, we use the DMA API.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-host.c | 15 ---
drivers/pci/dwc/pcie-designware.h | 3 ++-
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-host.c
b/drivers/pci/dwc
-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 4 +++-
drivers/pci/dwc/pcie-designware.h| 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c
b/drivers/pci/dwc/pcie-designware-ep.c
index d53d5f168363..c92ab87fd660 100644
On 11/03/2017 11:23 AM, Arnd Bergmann wrote:
> On Fri, Nov 3, 2017 at 10:56 AM, Niklas Cassel wrote:
>> On 11/02/2017 10:13 AM, Arnd Bergmann wrote:
> What I meant is that you can remove the #ifdef entirely if you add
>
> if (!IS_ENABLED(CONFIG
dra7xx_pcie_shutdown should be static.
This patch introduces a new sparse warning.
On Wed, Oct 11, 2017 at 9:32 PM, Bjorn Helgaas wrote:
> On Wed, Sep 20, 2017 at 10:54:15AM +0530, Keerthy wrote:
>> Add shutdown handler to cleanly turn off clocks. This will help
>> in cases of kexec where in a n
On 10/18/2017 10:03 AM, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On Tuesday 17 October 2017 05:13 AM, Bjorn Helgaas wrote:
>> On Fri, Oct 13, 2017 at 06:09:11PM +0200, Niklas Cassel wrote:
>>> Signed-off-by: Niklas Cassel
>>> ---
>>> .../devicetree
On 10/19/2017 09:59 AM, Christoph Hellwig wrote:
> On Mon, Oct 16, 2017 at 06:43:26PM -0500, Bjorn Helgaas wrote:
>> understand it. I guess the idea is to build pcie-artpec6.o if either
>> CONFIG_PCIE_ARTPEC6_HOST or CONFIG_PCIE_ARTPEC6_EP is set (or both).
>>
>> Is this really the simplest way to
Hello Bjorn
On 10/17/2017 01:43 AM, Bjorn Helgaas wrote:
(snip)
> I see you're copying the DRA7XX style here, but I don't really
> understand it. I guess the idea is to build pcie-artpec6.o if either
> CONFIG_PCIE_ARTPEC6_HOST or CONFIG_PCIE_ARTPEC6_EP is set (or both).
>
> Is this really the si
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control
register, thus overwriting the PCI_MSI_FLAGS_64BIT bit.
By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI
on systems where the RC has set a 64 bit MSI address.
Signed-off-by: Niklas Cassel
---
V2:
* Clarified commit
that it will work on all systems.
This is essentially the same thing as allocating a buffer in a driver,
to which the endpoint will write to. To do this, we use the DMA API.
Signed-off-by: Niklas Cassel
---
V2:
* Sort headers.
* MSI with captial letters in error print.
* Don't chan
ent should definitely be in dra7xx_add_pcie_port().
This is also needed to be able to compile host/ep mode specific code
independently.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/pci-dra7xx.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --gi
This function can be used by all DWC based controllers to raise a MSI
irq. However, certain controllers, like DRA7xx, has a special
convenience register for raising MSI irqs that doesn't require you to
explicitly map the MSI address.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in
This is done to better match other drivers such as dra7xx and imx6,
but also to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
V2:
* Changed the order of the functions to be more logical.
drivers/pci/dwc/pcie-artpec6.c | 53 +++---
1
This way you will not build and include unused code
when only building for only one mode.
Moved dra7xx_pcie_enable_wrapper_interrupts() in order
to avoid adding an extra ifdef block.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/pci-dra7xx.c | 36
e_irq, instead we pre-allocate
a page in dw_pcie_ep_init, so this page can later be used to map/unmap
the MSI address in raise_irq.
Signed-off-by: Niklas Cassel
---
V2:
* No change.
drivers/pci/dwc/pcie-designware-ep.c | 8
drivers/pci/dwc/pcie-designware.h| 2 ++
2 files changed, 10 inser
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V2:
* Split out the DT binding change to a self contained patch.
* Added Rob's ack (from V1). No chan
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
V2:
* DT binding change is now in a separate commit.
* Changed the order of the functions to be more logical.
drivers/pci/dwc
Signed-off-by: Niklas Cassel
---
V2:
* DT binding change is now in a separate commit.
* Removed local copy of dw_pcie_ep_reset_bar, it is now part of
pcie-designware-ep.c.
* Removed raise_msi_irq, it is now part of pcie-designware-ep.c.
* Refactored Kconfig and Makefile handling.
* Added ifdefs
.
This also fixes a bug for ARTPEC-6, where the cpu to bus address
fixup mask previously was off by one (GENMASK(27, 0), rather than
GENMASK(28, 0)), which is another reason why the it is a good idea
to calculate the mask by using values from device tree.
Signed-off-by: Niklas Cassel
---
V2
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V2:
* Split out the DT binding change to a self contained patch.
* Added Rob's ack (from V1). No change to this file since V1.
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions(+), 1 del
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
V2:
* Changed commit message to inclu
This greatly improves readability.
Signed-off-by: Niklas Cassel
---
V2:
* No change.
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index
The previous handling was a bit unorthodox and would have been a bit
bloated once more DWC based controllers added support for ep mode.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/Kconfig | 45 ++---
drivers/pci/dwc
This way pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar().
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/pci-dra7xx.c | 9 -
drivers/pci/dwc/pcie-designware-ep.c | 2 +-
drivers/pci/dwc/pcie-designware.h| 5 +
3 files
Certain registers that pcie-designware-ep tries to write are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit.
Signed-off-by: Niklas Cassel
---
V2:
* No change.
drivers/pci/dwc/pcie-designware-ep.c | 8
1 file changed, 8
first letter in summary for all patches.
Moved DT binding changes to self contained patches.
Fixed all review comments, for detailed changes, see the note for in patch.
Niklas Cassel (17):
PCI: dwc: Use DMA-API for allocating MSI data
PCI: designware-ep: dw_pcie_ep_set_msi() should only set
SZ_4K;
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/smem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index bf4bd71ab53f..b77573eed596 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drive
be
compile tested even when building for other architectures.
Changes since v3:
-Picked up Vinod's Reviewed-by tags.
-Rebased against v4.19-rc1
Niklas Cassel (6):
soc: qcom: smem: Add missing include of sizes.h
soc: qcom: llcc-slice: Add missing include of sizes.h
soc: qcom: sm
QCOM_SMD_RPM builds perfectly fine without CONFIG_OF set.
Remove the bogus depends of OF.
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/Kconfig b
Add missing include of sizes.h.
drivers/soc/qcom/llcc-slice.c: In function ‘llcc_update_act_ctrl’:
drivers/soc/qcom/llcc-slice.c:41:44: error: ‘SZ_4K’ undeclared
#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
^
Signed-off-by: Niklas Cassel
‘irq_domain_add_linear’
entry->domain = irq_domain_add_linear(node, 32, &smp2p_irq_ops, entry);
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/
‘irq_domain_add_linear’
entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry);
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/s
o Kconfigs
that depend on QCOM_SCM, since that triggers lots of build errors in
qcom_scm.
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/qcom
‘irq_domain_add_linear’
entry->domain = irq_domain_add_linear(node, 32, &smp2p_irq_ops, entry);
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/
SZ_4K;
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/smem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index bf4bd71ab53f..b77573eed596 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drive
‘irq_domain_add_linear’
entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry);
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/s
be
compile tested even when building for other architectures.
Changes since v5:
-kbuild test robot now uses gcc 8, so it found some new warnings
with -Wstringop-truncation, created 2 new patches for this.
-Removed depends on OF from QCOM_RPMH, new patch.
Niklas Cassel (9):
soc: qcom: smem: A
rncpy' specified bound 32
equals destination size [-Wstringop-truncation]
strncpy(chinfo.name, name, sizeof(chinfo.name));
^~~
This changes it to use the safer strscpy() instead.
Signed-off-by: Niklas Cassel
---
drivers/soc/qcom/wcnss_ct
This changes it to use the safer strscpy() instead.
Signed-off-by: Niklas Cassel
---
drivers/soc/qcom/apr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c
index 57af8a537332..ee9197f5aae9 100644
--- a/drivers/soc/qcom/apr.c
Add missing include of sizes.h.
drivers/soc/qcom/llcc-slice.c: In function ‘llcc_update_act_ctrl’:
drivers/soc/qcom/llcc-slice.c:41:44: error: ‘SZ_4K’ undeclared
#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
^
Signed-off-by: Niklas Cassel
QCOM_SMD_RPM builds perfectly fine without CONFIG_OF set.
Remove the bogus depends on OF.
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/Kconfig b
QCOM_RPHM already selects ARM64, which always selects OF.
Additionally, the rpmh driver only uses linux/of.h, which has dummy
definitions for all functions, in order for code to to be able to
build without CONFIG_OF set.
Remove the superfluous depends on OF.
Signed-off-by: Niklas Cassel
o Kconfigs
that depend on QCOM_SCM, since that triggers lots of build errors in
qcom_scm.
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/qcom
On Mon, Aug 27, 2018 at 10:12:03PM -0700, Bjorn Andersson wrote:
> The Hexagon v5 ADSP driver is used for more than only the ADSP and
> there's an upcoming non-PAS ADSP PIL for SDM845, so rename the driver to
> qcom_q6v5_pas in order to better suite this.
Hello Bjorn,
so I'm a bit new to this, bu
Add qcom,apq8096 to compatible string.
This compatible is defined in Documentation/devicetree/bindings/arm/qcom.txt
and is needed for e.g. drivers/cpufreq/qcom-cpufreq-kryo.c to be probed
correctly (and for drivers/cpufreq/cpufreq-dt-platdev.c to work properly).
Signed-off-by: Niklas Cassel
compatible string will be used.
Signed-off-by: Niklas Cassel
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index cd3865e7a270..354d3f900f72 100644
--- a/arch/arm64/boo
On Thu, Aug 30, 2018 at 12:05:14PM +0530, Rajendra Nayak wrote:
>
>
> On 6/27/2018 10:22 AM, Rajendra Nayak wrote:
> > Changes in v4:
> > * Included the patch to add qcom-opp bindings (dropped accidentally in v3)
> > * merged the patches to add bindings for rpm and rpmh, added consumer
> > bindi
On Tue, Aug 14, 2018 at 05:42:33PM +0530, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
>
> The required OPP related data is determined based on
> the
On Tue, Aug 14, 2018 at 05:42:33PM +0530, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
>
> The required OPP related data is determined based on
> the
_dsi 1a98000.dsi: Using legacy clk name binding. Use "iface" instead of
"iface_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "bus" instead of
"bus_clk"
msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "byte" instead of
"b
On Sat, Jul 21, 2018 at 01:51:47PM -0500, Andy Gross wrote:
> On Thu, Jul 19, 2018 at 12:53:04PM +0200, Nicolas Dechesne wrote:
> > hi Niklas,
> >
> > On Wed, Jul 18, 2018 at 4:53 PM Niklas Cassel
> > wrote:
> > >
> > > Drop legacy suffix for cloc
Hello Song
On 05/12/2017 03:51 AM, Song Xiaowei wrote:
> From: songxiaowei
>
> Hisilicon PCIe Driver shares the common functions fo PCIe dw-host
>
> The poweron functions is developed on hi3660 SoC, while Others Functions
> are common for Kirin series SoCs.
>
> Lowpower(L1ss and SR), hotplug a
1 - 100 of 751 matches
Mail list logo
