ces CPU cycles by 0.54%.
This can result in more internal fragmentation and memory overhead for a
given allocation, an option nohugevmalloc is added to disable at boot.
Signed-off-by: Nicholas Piggin
---
arch/Kconfig| 4 +
include/linux/vmalloc.h | 1 +
mm/page_alloc.c |
This allows unsupported levels to be constant folded away, and so
p4d_free_pud_page can be removed because it's no longer linked to.
Cc: linuxppc-...@lists.ozlabs.org
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/vmalloc.h | 19 ---
arch/powerpc/mm/boo
Excerpts from Eric Dumazet's message of August 22, 2020 1:38 am:
>
> On 8/21/20 8:12 AM, Nicholas Piggin wrote:
>> Support huge page vmalloc mappings. Config option HAVE_ARCH_HUGE_VMALLOC
>> enables support on architectures that define HAVE_ARCH_HUGE_VMAP and
>> sup
Excerpts from Andrew Morton's message of August 22, 2020 6:07 am:
> On Sat, 22 Aug 2020 01:12:05 +1000 Nicholas Piggin wrote:
>
>> vmalloc_to_page returns NULL for addresses mapped by larger pages[*].
>> Whether or not a vmap is huge depends on the architecture detai
Excerpts from Andrew Morton's message of August 22, 2020 6:14 am:
> On Sat, 22 Aug 2020 01:12:09 +1000 Nicholas Piggin wrote:
>
>> This changes the awkward approach where architectures provide init
>> functions to determine which levels they can provide large mappings f
e pte is encountered")
> url:
> https://github.com/0day-ci/linux/commits/Nicholas-Piggin/huge-vmalloc-mappings/20200821-124543
> base: https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git next
>
> in testcase: boot
>
> on test machine: qemu-system-x86_64 -enab
4. Add a non-refcounting lazy mmu mode, to help scalability when the
same mm is used for a lot of lazy mmu switching.
Comments, questions on anything would be much appreciated.
Thanks,
Nick
Nicholas Piggin (7):
asm-generic: add generic MMU versions of mmu context functions
arch: use asm-gene
right place.
There is also a exit_lazy_tlb case that is not covered by this call, which
could be a bugs (kthread use mm the membarrier process's mm then context
switch back to the process without switching mm or lazy mm switch).
This makes lazy tlb code a bit more modular.
Signed-off-by
This patch bunches all architectures together. If the general idea is
accepted I will split them individually. Some architectures can go
further e.g., with consolidating switch_mm and activate_mm but I
only did the more obvious ones.
---
arch/alpha/include/asm/mmu_context.h | 12 ++---
arc
Many of these are no-ops on many architectures, so extend mmu_context.h
to cover MMU and NOMMU, and split the NOMMU bits out to nommu_context.h
Cc: Arnd Bergmann
Cc: Remis Lima Baima
Signed-off-by: Nicholas Piggin
---
arch/microblaze/include/asm/mmu_context.h | 2 +-
arch/sh/include/asm
NOMMU systems could easily go without this and save a bit of code
and the mm refcounting, because their mm switch is a no-op. I haven't
flipped them over because haven't audited all arch code to convert
over to using the _lazy_tlb refcounting.
Signed-off-by: Nicholas Piggin
---
ar
Add explicit _lazy_tlb annotated functions for lazy mm refcounting.
This makes things a bit more explicit, and allows explicit refcounting
to be removed if it is not used.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/smp.c| 2 +-
arch/powerpc/mm/book3s64/radix_tlb.c | 4
f idle), upstream can achieve a rate of about 1 million context
switches per second. After this patch it goes up to 118 million.
Signed-off-by: Nicholas Piggin
---
arch/Kconfig | 16
arch/powerpc/Kconfig | 1 +
include/linux/sched/mm.h | 6 +++---
kernel/
Signed-off-by: Nicholas Piggin
---
fs/exec.c | 5 +++--
include/asm-generic/mmu_context.h | 20
kernel/kthread.c | 1 +
kernel/sched/core.c | 2 ++
4 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/fs
Excerpts from Arnd Bergmann's message of October 10, 2020 6:25 pm:
> On Sat, Oct 10, 2020 at 4:02 AM Stephen Rothwell
> wrote:
>> On Fri, 9 Oct 2020 16:01:22 +0200 Arnd Bergmann wrote:
>>
>> > Are there other changes that depend on this? If not, I would
>> > just wait until -rc1 and then either
Excerpts from Andrew Morton's message of September 29, 2020 2:46 pm:
> On Tue, 29 Sep 2020 02:17:19 +0100 Matthew Wilcox wrote:
>
>> On Mon, Sep 28, 2020 at 06:03:07PM -0700, Andrew Morton wrote:
>> > On Sat, 26 Sep 2020 22:39:19 +0100 "Matthew Wilcox (Oracle)"
>> > wrote:
>> >
>> > > Here is
All the cool kids are doing it.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/atomic.h | 681 ++---
arch/powerpc/include/asm/cmpxchg.h | 62 +--
2 files changed, 248 insertions(+), 495 deletions(-)
diff --git a/arch/powerpc/include/asm/atomic.h
b/arch
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/book3s64/iommu_api.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/book3s64/iommu_api.c
b/arch/powerpc/mm/book3s64/iommu_api.c
index 563faa10bb66..685d7bb3d26f 100644
--- a/arch/powerpc/mm/book3s64
This passes atomic64 selftest on ppc32 on qemu (uniprocessor only)
both before and after powerpc is converted to use ARCH_ATOMIC.
Signed-off-by: Nicholas Piggin
---
include/asm-generic/atomic64.h | 70 +++---
lib/atomic64.c | 36 -
2
This conversion seems to require generic atomic64 changes, looks
like nothing else uses ARCH_ATOMIC and GENERIC_ATOMIC64 yet.
Thanks,
Nick
Nicholas Piggin (3):
asm-generic/atomic64: Add support for ARCH_ATOMIC
powerpc/64s/iommu: don't use atomic_ function on atomic64_t type
po
Excerpts from Peter Zijlstra's message of November 11, 2020 11:44 pm:
> On Wed, Nov 11, 2020 at 02:39:01PM +0100, Christophe Leroy wrote:
>> Hello,
>>
>> Le 11/11/2020 à 12:07, Nicholas Piggin a écrit :
>> > This passes atomic64 selftest on ppc32 on qemu (unip
Excerpts from Christophe Leroy's message of November 9, 2020 2:57 am:
> In head_64.S, we have two places using RFI to return to
> kernel. Use RFI_TO_KERNEL instead.
>
> They are the two only places using RFI on book3s/64, so
> the RFI macro can go away.
Looks good to me.
Excerpts from Peter Zijlstra's message of July 26, 2020 6:26 am:
> On Thu, Jul 23, 2020 at 08:56:14PM +1000, Nicholas Piggin wrote:
>> diff --git a/arch/powerpc/include/asm/hw_irq.h
>> b/arch/powerpc/include/asm/hw_irq.h
>> index 3a0db7b0b46e..35060be09073 100644
>>
Excerpts from Mathieu Desnoyers's message of July 21, 2020 2:46 am:
> - On Jul 19, 2020, at 11:03 PM, Nicholas Piggin npig...@gmail.com wrote:
>
>> Excerpts from Mathieu Desnoyers's message of July 17, 2020 11:42 pm:
>>> - On Jul 16, 2020, at 7:26 PM, Ni
Excerpts from Peter Zijlstra's message of July 8, 2020 6:41 pm:
> On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote:
>> Yes, powerpc could certainly get more performance out of the slow
>> paths, and then there are a few parameters to tune.
>
Sorry for the
Excerpts from Peter Zijlstra's message of July 9, 2020 6:31 pm:
> On Wed, Jul 08, 2020 at 07:54:34PM -0400, Waiman Long wrote:
>> On 7/8/20 4:41 AM, Peter Zijlstra wrote:
>> > On Tue, Jul 07, 2020 at 03:57:06PM +1000, Nicholas Piggin wrote:
>> > > Yes, powerpc c
Excerpts from Mathieu Desnoyers's message of July 21, 2020 11:11 pm:
> - On Jul 21, 2020, at 6:04 AM, Nicholas Piggin npig...@gmail.com wrote:
>
>> Excerpts from Mathieu Desnoyers's message of July 21, 2020 2:46 am:
> [...]
>>
>> Yeah you're probabl
Excerpts from Pratik Sampat's message of July 21, 2020 8:29 pm:
>
>
> On 20/07/20 5:27 am, Nicholas Piggin wrote:
>> Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
>>> Replace the variable name from using "pnv_first_spr_loss_level&
Excerpts from Andy Lutomirski's message of July 14, 2020 10:46 pm:
>
>
>> On Jul 13, 2020, at 11:31 PM, Nicholas Piggin wrote:
>>
>> Excerpts from Nicholas Piggin's message of July 14, 2020 3:04 pm:
>>> Excerpts from Andy Lutomirski's message
Excerpts from Andy Lutomirski's message of July 14, 2020 10:46 pm:
>
>
>> On Jul 13, 2020, at 11:31 PM, Nicholas Piggin wrote:
>>
>> Excerpts from Nicholas Piggin's message of July 14, 2020 3:04 pm:
>>> Excerpts from Andy Lutomirski's message
Excerpts from Mathieu Desnoyers's message of July 14, 2020 12:13 am:
> - On Jul 13, 2020, at 9:47 AM, Nicholas Piggin npig...@gmail.com wrote:
>
>> Excerpts from Nicholas Piggin's message of July 13, 2020 2:45 pm:
>>> Excerpts from Andy Lutomirski's message
Excerpts from Nicholas Piggin's message of July 16, 2020 2:15 pm:
> Excerpts from Mathieu Desnoyers's message of July 14, 2020 12:13 am:
>> - On Jul 13, 2020, at 9:47 AM, Nicholas Piggin npig...@gmail.com wrote:
>>
>>> Excerpts from Nicholas Piggin&
Excerpts from Andy Lutomirski's message of July 16, 2020 3:18 pm:
>
>
>> On Jul 15, 2020, at 9:15 PM, Nicholas Piggin wrote:
>>
>> Excerpts from Mathieu Desnoyers's message of July 14, 2020 12:13 am:
>>> - On Jul 13, 2020, at 9:47
Excerpts from Eric Biggers's message of July 16, 2020 1:03 pm:
> On Thu, Jul 16, 2020 at 09:42:03AM +1000, Dave Chinner wrote:
>> On Wed, Jul 15, 2020 at 09:32:56AM -0700, Eric Biggers wrote:
>> > [+Cc linux-fsdevel]
>> >
>> > On Wed, Jul 15, 2020 at 05:29:12PM +0200, 'Marco Elver' via syzkaller-b
Excerpts from Eric Biggers's message of July 16, 2020 4:54 pm:
> On Thu, Jul 16, 2020 at 04:24:01PM +1000, Nicholas Piggin wrote:
>> Excerpts from Eric Biggers's message of July 16, 2020 1:03 pm:
>> > On Thu, Jul 16, 2020 at 09:42:03AM +1000, Dave Chinner wrote:
>>
Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
> Replace the variable name from using "pnv_first_spr_loss_level" to
> "pnv_first_fullstate_loss_level".
>
> As pnv_first_spr_loss_level is supposed to be the earliest state that
> has OPAL_PM_LOSE_FULL_CONTEXT set, however as
Excerpts from Pratik Rajesh Sampat's message of July 18, 2020 4:53 am:
> As the idle framework's architecture is incomplete, hence instead of
> checking for just the processor type advertised in the device tree CPU
> features; check for the Processor Version Register (PVR) so that finer
> granulari
r the
> check for machines lower than Power9
>
> Signed-off-by: Pratik Rajesh Sampat
> Reviewed-by: Gautham R. Shenoy
Reviewed-by: Nicholas Piggin
> ---
> arch/powerpc/platforms/powernv/idle.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff -
When I last looked at this (predating io_uring), as far as I remember it was
not permitted to actually switch to (use_mm) an mm user context that was
pinned with mmget_not_zero. Those pins were only allowed to look at page
tables, vmas, etc., but not actually run the CPU in that mm context.
spa
Excerpts from Zefan Li's message of July 20, 2020 12:02 pm:
>> +static int vmap_pages_range_noflush(unsigned long start, unsigned long end,
>> +pgprot_t prot, struct page **pages,
>> +unsigned int page_shift)
>> +{
>> +if (page_shi
Excerpts from Mathieu Desnoyers's message of July 17, 2020 11:42 pm:
> - On Jul 16, 2020, at 7:26 PM, Nicholas Piggin npig...@gmail.com wrote:
> [...]
>>
>> membarrier does replace barrier instructions on remote CPUs, which do
>> order accesses performed by t
Cc: Thomas Bogendoerfer
Cc: linux-m...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/mips/include/asm/mmu_context.h | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/mips/include/asm/mmu_context.h
b/arch/mips/include/asm/mmu_context.h
index
Cc: Tony Luck
Cc: Fenghua Yu
Cc: linux-i...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/ia64/include/asm/mmu_context.h | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/ia64/include/asm/mmu_context.h
b/arch/ia64/include/asm/mmu_context.h
Cc: Geert Uytterhoeven
Cc: linux-m...@lists.linux-m68k.org
Signed-off-by: Nicholas Piggin
---
arch/m68k/include/asm/mmu_context.h | 47 +
1 file changed, 8 insertions(+), 39 deletions(-)
diff --git a/arch/m68k/include/asm/mmu_context.h
b/arch/m68k/include/asm
Cc: Vineet Gupta
Cc: linux-snps-...@lists.infradead.org
Signed-off-by: Nicholas Piggin
---
arch/arc/include/asm/mmu_context.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arc/include/asm/mmu_context.h
b/arch/arc/include/asm/mmu_context.h
index
Cc: Guo Ren
Cc: linux-c...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/csky/include/asm/mmu_context.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/csky/include/asm/mmu_context.h
b/arch/csky/include/asm/mmu_context.h
index abdf1f1cb6ec
Cc: Jonas Bonn
Cc: Stefan Kristiansson
Cc: Stafford Horne
Cc: openr...@lists.librecores.org
Signed-off-by: Nicholas Piggin
---
arch/openrisc/include/asm/mmu_context.h | 8 +++-
arch/openrisc/mm/tlb.c | 2 ++
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a
Cc: Richard Henderson
Cc: Ivan Kokshaysky
Cc: Matt Turner
Cc: linux-al...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/alpha/include/asm/mmu_context.h | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/alpha/include/asm/mmu_context.h
b/arch/alpha
Cc: Catalin Marinas
Cc: Will Deacon
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Nicholas Piggin
---
arch/arm64/include/asm/mmu_context.h | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/mmu_context.h
b/arch/arm64/include/asm
Cc: Brian Cain
Cc: linux-hexa...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/hexagon/include/asm/mmu_context.h | 33 --
1 file changed, 5 insertions(+), 28 deletions(-)
diff --git a/arch/hexagon/include/asm/mmu_context.h
b/arch/hexagon/include/asm
of them in the next window?
Thanks,
Nick
Nicholas Piggin (24):
asm-generic: add generic versions of mmu context functions
alpha: use asm-generic/mmu_context.h for no-op implementations
arc: use asm-generic/mmu_context.h for no-op implementations
arm: use asm-generic/mmu_context.h
Many of these are no-ops on many architectures, so extend mmu_context.h
to cover MMU and NOMMU, and split the NOMMU bits out to nommu_context.h
Cc: Arnd Bergmann
Cc: linux-a...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/microblaze/include/asm/mmu_context.h | 2 +-
arch/sh/include
Cc: Russell King
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Nicholas Piggin
---
arch/arm/include/asm/mmu_context.h | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/mmu_context.h
b/arch/arm/include/asm
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc: x...@kernel.org
Cc: "H. Peter Anvin"
Signed-off-by: Nicholas Piggin
---
arch/x86/include/asm/mmu_context.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/mmu_context.h
b/arch/x86/i
Cc: Michal Simek
Signed-off-by: Nicholas Piggin
---
arch/microblaze/include/asm/mmu_context_mm.h | 8
arch/microblaze/include/asm/processor.h | 3 ---
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/microblaze/include/asm/mmu_context_mm.h
b/arch/microblaze
Cc: Nick Hu
Cc: Greentime Hu
Cc: Vincent Chen
Signed-off-by: Nicholas Piggin
---
arch/nds32/include/asm/mmu_context.h | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/nds32/include/asm/mmu_context.h
b/arch/nds32/include/asm/mmu_context.h
index b8fd3d189fdc
Cc: Ley Foon Tan
Signed-off-by: Nicholas Piggin
---
arch/nios2/include/asm/mmu_context.h | 21 -
arch/nios2/mm/mmu_context.c | 1 +
2 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/nios2/include/asm/mmu_context.h
b/arch/nios2/include/asm
Cc: Jeff Dike
Cc: Richard Weinberger
Cc: Anton Ivanov
Cc: linux...@lists.infradead.org
Signed-off-by: Nicholas Piggin
---
arch/um/include/asm/mmu_context.h | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/um/include/asm/mmu_context.h
b/arch/um/include/asm
Cc: Guan Xuetao
Signed-off-by: Nicholas Piggin
---
arch/unicore32/include/asm/mmu_context.h | 24 +++-
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/arch/unicore32/include/asm/mmu_context.h
b/arch/unicore32/include/asm/mmu_context.h
index 388c0c811c68
Cc: Paul Walmsley
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc: linux-ri...@lists.infradead.org
Signed-off-by: Nicholas Piggin
---
arch/riscv/include/asm/mmu_context.h | 22 ++
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/include/asm/mmu_context.h
b
Cc: Michael Ellerman
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-...@lists.ozlabs.org
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/mmu_context.h | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm
Cc: "David S. Miller"
Cc: sparcli...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/sparc/include/asm/mmu_context_32.h | 10 --
arch/sparc/include/asm/mmu_context_64.h | 10 +-
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/arch/sparc/i
Cc: "James E.J. Bottomley"
Cc: Helge Deller
Cc: linux-par...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/parisc/include/asm/mmu_context.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/parisc/include/asm/mmu_context.h
b/arch/pari
Cc: Yoshinori Sato
Cc: Rich Felker
Cc: linux...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/sh/include/asm/mmu_context.h| 5 ++---
arch/sh/include/asm/mmu_context_32.h | 9 -
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/sh/include/asm
Cc: Chris Zankel
Cc: Max Filippov
Cc: linux-xte...@linux-xtensa.org
Signed-off-by: Nicholas Piggin
---
arch/xtensa/include/asm/mmu_context.h | 11 +++
arch/xtensa/include/asm/nommu_context.h | 26 +
2 files changed, 4 insertions(+), 33 deletions(-)
diff --git
Cc: Heiko Carstens
Cc: Vasily Gorbik
Cc: Christian Borntraeger
Cc: linux-s...@vger.kernel.org
Signed-off-by: Nicholas Piggin
---
arch/s390/include/asm/mmu_context.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/s390/include/asm/mmu_context.h
b/arch/s390
Excerpts from Vineet Gupta's message of July 28, 2020 2:01 pm:
> On 7/27/20 8:33 PM, Nicholas Piggin wrote:
>> Many of these are no-ops on many architectures, so extend mmu_context.h
>> to cover MMU and NOMMU, and split the NOMMU bits out to nommu_context.h
>>
>
>
Excerpts from pet...@infradead.org's message of July 26, 2020 10:11 pm:
> On Sun, Jul 26, 2020 at 02:14:34PM +1000, Nicholas Piggin wrote:
>> Excerpts from Peter Zijlstra's message of July 26, 2020 6:26 am:
>
>> > Which is 'funny' when it interlea
Excerpts from Waiman Long's message of July 6, 2020 5:00 am:
> On 7/3/20 3:35 AM, Nicholas Piggin wrote:
>> Signed-off-by: Nicholas Piggin
>> ---
>> arch/powerpc/include/asm/paravirt.h | 28 ++
>> arch/powerpc/inclu
Excerpts from Christophe Leroy's message of July 6, 2020 3:49 am:
>
>
> Le 03/07/2020 à 16:13, Michael Ellerman a écrit :
>> We have powerpc specific logic in our page fault handling to decide if
>> an access to an unmapped address below the stack pointer should expand
>> the stack VMA.
>>
>> Th
An include goes away in future patches which breaks compilation
without this.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/powernv/pci-ioda-tce.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda-tce.c
b/arch/powerpc/platforms/powernv/pci
v3 is updated to use __pv_queued_spin_unlock, noticed by Waiman (thank you).
Thanks,
Nick
Nicholas Piggin (6):
powerpc/powernv: must include hvcall.h to get PAPR defines
powerpc/pseries: move some PAPR paravirt functions to their own file
powerpc: move spinlock implementation to
This brings the behaviour of the uncontended fast path back to
roughly equivalent to simple spinlocks -- a single atomic op with
lock hint.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/atomic.h| 28
arch/powerpc/include/asm/qspinlock.h | 2 +-
2
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paravirt.h | 28
arch/powerpc/include/asm/qspinlock.h | 66 +++
arch/powerpc/include/asm/qspinlock_paravirt.h | 7 ++
arch/powerpc/platforms/pseries/Kconfig| 5 ++
arch/powerpc
To prepare for queued spinlocks. This is a simple rename except to update
preprocessor guard name and a file reference.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/simple_spinlock.h| 292 ++
.../include/asm/simple_spinlock_types.h | 21 ++
arch/powerpc
.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/Kconfig | 13
arch/powerpc/include/asm/Kbuild | 2 ++
arch/powerpc/include/asm/qspinlock.h | 25 +++
arch/powerpc/include/asm/spinlock.h | 5 +
arch/powerpc/include
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paravirt.h | 61 +
arch/powerpc/include/asm/spinlock.h | 24 +---
arch/powerpc/lib/locks.c| 12 +++---
3 files changed, 68 insertions(+), 29 deletions(-)
create mode 100644 arch/powerpc
Excerpts from Waiman Long's message of July 7, 2020 4:39 am:
> On 7/6/20 12:35 AM, Nicholas Piggin wrote:
>> v3 is updated to use __pv_queued_spin_unlock, noticed by Waiman (thank you).
>>
>> Thanks,
>> Nick
>>
>> Nicholas Piggin (6):
>>
Excerpts from Peter Zijlstra's message of July 23, 2020 9:40 pm:
> On Thu, Jul 23, 2020 at 08:56:14PM +1000, Nicholas Piggin wrote:
>
>> diff --git a/arch/powerpc/include/asm/hw_irq.h
>> b/arch/powerpc/include/asm/hw_irq.h
>> index 3a0db7b0b46e..35060be09073 100644
Excerpts from Waiman Long's message of July 22, 2020 12:36 am:
> On 7/21/20 7:08 AM, Nicholas Piggin wrote:
>> diff --git a/arch/powerpc/include/asm/qspinlock.h
>> b/arch/powerpc/include/asm/qspinlock.h
>> index b752d34517b3..26d8766a1106 100644
>> --- a/arch
Excerpts from Michael Ellerman's message of July 9, 2020 8:53 pm:
> Nicholas Piggin writes:
>
>> Signed-off-by: Nicholas Piggin
>> ---
>> arch/powerpc/include/asm/paravirt.h | 28
>> arch/powerpc/include/asm/qspinlock.h | 66 +
Excerpts from Waiman Long's message of July 24, 2020 12:29 am:
> On 7/23/20 9:30 AM, Nicholas Piggin wrote:
>>> I would prefer to extract out the pending bit handling code out into a
>>> separate helper function which can be overridden by the arch code
>>> inst
Excerpts from Peter Zijlstra's message of July 24, 2020 12:59 am:
> On Thu, Jul 23, 2020 at 11:11:03PM +1000, Nicholas Piggin wrote:
>> Excerpts from Peter Zijlstra's message of July 23, 2020 9:40 pm:
>> > On Thu, Jul 23, 2020 at 08:56:14PM +1000, Nicholas Piggin wro
Excerpts from Alexey Kardashevskiy's message of July 24, 2020 2:16 pm:
>
>
> On 23/07/2020 23:11, Nicholas Piggin wrote:
>> Excerpts from Peter Zijlstra's message of July 23, 2020 9:40 pm:
>>> On Thu, Jul 23, 2020 at 08:56:14PM +1000, Nicholas Piggin wrote:
investigated and
improved in future.
Performance results can be found in the commit which added queued spinlocks.
Acked-by: Peter Zijlstra (Intel)
Acked-by: Waiman Long
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paravirt.h | 28
arch/powerpc/include/asm
cool technology and great results especially
on the big systems but even on smaller ones there are nice gains. Thanks
Waiman and everyone who developed it.
Thanks,
Nick
Nicholas Piggin (6):
powerpc/pseries: move some PAPR paravirt functions to their own file
powerpc: move spinlock implemen
These functions will be used by queued spinlock implementation,
and may be useful elsewhere too, so move them out of spinlock.h.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paravirt.h | 59 +
arch/powerpc/include/asm/spinlock.h | 24 +---
arch
regressions haven't been analysed very well yet, there are a lot of
things that can be tuned, particularly the paravirtualised locking, but the
numbers already look like a good net win even on relatively small systems.
Acked-by: Peter Zijlstra (Intel)
Signed-off-by: Nicholas Piggin
---
arch/po
To prepare for queued spinlocks. This is a simple rename except to update
preprocessor guard name and a file reference.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/simple_spinlock.h| 288 ++
.../include/asm/simple_spinlock_types.h | 21 ++
arch/powerpc
This implements smp_cond_load_relaed with the slowpath busy loop using the
preferred SMT priority pattern.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/barrier.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc
This brings the behaviour of the uncontended fast path back to roughly
equivalent to simple spinlocks -- a single atomic op with lock hint.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/atomic.h| 28
arch/powerpc/include/asm/qspinlock.h | 2 +-
2
Excerpts from Peter Zijlstra's message of July 22, 2020 6:35 pm:
> On Tue, Jul 21, 2020 at 02:06:23PM -0700, Andrew Morton wrote:
>> On Tue, 21 Jul 2020 17:41:06 +0200 Peter Zijlstra
>> wrote:
>>
>> >
>> > For SMP systems using IPI based TLB invalidation, looking at
>> > current->active_mm is e
Kardashevskiy
Signed-off-by: Nicholas Piggin
---
I haven't tested on other architectures but I imagine NMIs in general
might cause a similar problem.
Other architectures might have to be updated for patch 2, but there's
a lot of asm around interrupt/return, so I didn't have a very
to NMIs etc.
Signed-off-by: Nicholas Piggin
---
kernel/locking/lockdep.c | 80 +-
kernel/locking/lockdep_internals.h | 4 --
kernel/locking/lockdep_proc.c | 10 +---
3 files changed, 35 insertions(+), 59 deletions(-)
diff --git a/kernel/locking
Excerpts from Waiman Long's message of July 13, 2020 9:05 am:
> On 7/12/20 1:34 PM, Peter Zijlstra wrote:
>> On Sat, Jul 11, 2020 at 02:21:28PM -0400, Waiman Long wrote:
>>> The previous patch enables native qspinlock to store lock holder cpu
>>> number into the lock word when the lock is acquired
Excerpts from Andy Lutomirski's message of July 11, 2020 3:04 am:
> On Thu, Jul 9, 2020 at 6:57 PM Nicholas Piggin wrote:
>>
>> And get rid of the generic sync_core_before_usermode facility.
>>
>> This helper is the wrong way around I think. The idea that membarri
Excerpts from Peter Zijlstra's message of July 10, 2020 7:35 pm:
> On Fri, Jul 10, 2020 at 11:56:46AM +1000, Nicholas Piggin wrote:
>> On big systems, the mm refcount can become highly contented when doing
>> a lot of context switching with threaded applications (particularly
Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm:
> Changelog v1 --> v2:
> 1. Save-restore DAWR and DAWRX unconditionally as they are lost in
> shallow idle states too
> 2. Rename pnv_first_spr_loss_level to pnv_first_fullstate_loss_level to
> correct naming terminology
>
> Pr
Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm:
> Additional registers DAWR0, DAWRX0 may be lost on Power 10 for
> stop levels < 4.
> Therefore save the values of these SPRs before entering a "stop"
> state and restore their values on wakeup.
Hmm, where do you get this from
Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm:
> POWER9 onwards the support for the registers HID1, HID4, HID5 has been
> receded.
> Although mfspr on the above registers worked in Power9, In Power10
> simulator is unrecognized. Moving their assignment under the
> check for
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