On 8/16/2017 2:53 PM, Radim Krcmar wrote:
2017-08-16 10:54-0500, Janakarajan Natarajan:
Enable the Virtual GIF feature. This is done by setting bit 25 at position
60h in the vmcb.
With this feature enabled, the processor uses bit 9 at position 60h as the
virtual GIF when executing STGI/CLGI ins
On 8/16/2017 12:36 PM, Borislav Petkov wrote:
On Wed, Aug 16, 2017 at 10:54:49AM -0500, Janakarajan Natarajan wrote:
Define a new cpufeature definition for Virtual GIF.
"Define ... definition" ?
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file chan
In Family 17h, some L3 Cache Performance events require the ThreadMask
and SliceMask to be set. For other events, these fields do not affect
the count either way.
Set ThreadMask and SliceMask to 0xFF and 0xF respectively.
Signed-off-by: Janakarajan Natarajan
---
v2: Changed L3 Slice and L3 Threa
Add a new cpufeature definition for the WBNOINVD instruction.
The WBNOINVD instruction writes all modified line in all levels of
cache associated with a processor to main memory while retaining the
cached values.
Both AMD and Intel support this instruction.
Signed-off-by: Janakarajan Natarajan
On 5/10/2018 12:28 PM, Borislav Petkov wrote:
Use a prefix for the subject pls:
Subject: [PATCH RESEND 1/2] crypto: ccp: Add DOWNLOAD_FIRMWARE SEV command
or
Subject: [PATCH RESEND 1/2] crypto/ccp: Add DOWNLOAD_FIRMWARE SEV command
or so.
Okay.
On Wed, May 09, 2018 at 11:18:27AM -0500,
On 9/27/19 4:48 PM, Thomas Renninger wrote:
> On Friday, September 27, 2019 6:07:56 PM CEST Natarajan, Janakarajan wrote:
>> On 9/18/2019 11:34 AM, Natarajan, Janakarajan wrote:
>>> This is advantageous because an IPI is not generated when a read_msr() is
>>> execut
On 9/27/2019 1:59 PM, shuah wrote:
> On 9/18/19 10:34 AM, Natarajan, Janakarajan wrote:
>> Modify cpupower to schedule itself on each of the cpus in the system and
>> then get the APERF/MPERF register values.
>>
>> This is advantageous because an IPI is not generat
As per "AMD64 Architecture Programmer's Manual Volume 3: General-Purpose
and System Instructions", MWAITX EAX[7:4]+1 specifies the optional hint
of the optimized C-state. For C0 state, EAX[7:4] should be set to 0xf.
Currently, a value of 0xf is set for EAX[3:0] instead of EAX[7:4]. Fix
this by cha
On 10/5/2019 7:40 AM, Thomas Renninger wrote:
> Hi,
>
> On Wednesday, October 2, 2019 4:45:03 PM CEST Natarajan, Janakarajan wrote:
>> On 9/27/19 4:48 PM, Thomas Renninger wrote:
>>
>>> On Friday, September 27, 2019 6:07:56 PM CEST Natarajan, Janakarajan
>>
Modify cpupower to schedule itself on each of the cpus in the system and
then get the APERF/MPERF register values.
This is advantageous because an IPI is not generated when a read_msr() is
executed on the local logical CPU thereby reducing the chance of having
APERF and MPERF being out of sync.
S
AMD Zen 2 introduces the RDPRU instruction which can be used to access some
processor registers which are typically only accessible in privilege level
0. ECX specifies the register to read and EDX:EAX will contain the value read.
ECX: 0 - Register MPERF
1 - Register APERF
This has the added
On 9/18/2019 11:34 AM, Natarajan, Janakarajan wrote:
> Modify cpupower to schedule itself on each of the cpus in the system and
> then get the APERF/MPERF register values.
>
> This is advantageous because an IPI is not generated when a read_msr() is
> executed on the local logi
On 10/11/2019 2:37 PM, Natarajan, Janakarajan wrote:
> This patchset updates cpupower to make it more accurate by removing
> the userspace to kernel transitions and read_msr initiated IPI delays.
>
> The first patch does a little re-arrangement of variables in the
> cpuidle_mo
On 10/10/2019 6:22 AM, Thomas Renninger wrote:
> On Monday, October 7, 2019 11:11:30 PM CEST Natarajan, Janakarajan wrote:
>> On 10/5/2019 7:40 AM, Thomas Renninger wrote:
>>
> ...
>>>> APERF/MPERF from CPL > 0) and avoid using the msr module (patch 2).
>>&
The per_cpu_schedule flag is used to move the cpupower process to the cpu
on which we are looking to read the APERF/MPERF registers.
This prevents IPIs from being generated by read_msr()s as we are already
on the cpu of interest.
Ex: If cpupower is running on CPU 0 and we execute
read_msr(20
Move the needs_root variable into a sub-struct. This is in preparation
for adding a new flag for cpuidle_monitor.
Update all uses of the needs_root variable to reflect this change.
Signed-off-by: Janakarajan Natarajan
---
tools/power/cpupower/utils/idle_monitor/amd_fam14h_idle.c | 2 +-
tools/
This patchset updates cpupower to make it more accurate by removing
the userspace to kernel transitions and read_msr initiated IPI delays.
The first patch does a little re-arrangement of variables in the
cpuidle_monitor struct to prepare for a new flag.
The second patch introduces a per_cpu_sched
AMD Zen 2 introduces the RDPRU instruction which can be used to access some
processor registers which are typically only accessible in privilege level
0. ECX specifies the register to read and EDX:EAX will contain the value read.
ECX: 0 - Register MPERF
1 - Register APERF
This has the added
From: Yazen Ghannam
The show_cppc_data macro implicity uses define_one_cppc_ro. This will
prevent the creation of an attribute with read and write permissions.
Create a separate macro that defines a show attribute and creates
a read-only sysfs entry. This is in preparation for adding a macro
to
CPC_SUP_BUFFER_ONLY ensures that an expected BUFFER only register has a
register type of ACPI_TYPE_BUFFER and is not NULL.
Signed-off-by: Janakarajan Natarajan
---
drivers/acpi/cppc_acpi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_ac
CPPC (Collaborative Processor Performance Control) offers optional
registers which can be used to tune the system based on energy and/or
performance requirements.
Newer AMD processors add support for a subset of these optional CPPC
registers, based on ACPI v6.1.
The following are the supported CP
Add attributes for registers that are supported by the platform. This prevents
unsupported optional registers from having sysfs entries created.
Also, add a macro REG_SUPPORTED which will decide on the check to perform
based on the type of register.
Signed-off-by: Janakarajan Natarajan
---
driv
From: Yazen Ghannam
Newer AMD processors support a subset of the optional CPPC registers.
Create show, store and helper routines for supported CPPC registers.
Signed-off-by: Yazen Ghannam
[ carved out into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan Natarajan
---
drivers/acp
From: Yazen Ghannam
Some CPPC registers can be used to configure the platform. To enable this,
create macros to define the show, store routines and create sysfs entries
with R/W permission.
Signed-off-by: Yazen Ghannam
[ carved into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan
From: Yazen Ghannam
The cppc_set_perf() currently only works for DESIRED_PERF. To make it
generic, pass in the index of the register being accessed.
Also, rename cppc_set_perf() to cppc_set_reg(). This is in preparation
for it to be used for more than just the DESIRED_PERF register.
Signed-off-
From: Yazen Ghannam
To enable CPPC on a processor, the OS should write a value "1" to the
CPPC Enable register. Add support for this register.
Signed-off-by: Yazen Ghannam
[ carved out into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan Natarajan
---
drivers/acpi/cppc_acpi.c |
CPPC (Collaborative Processor Performance Control) offers optional
registers which can be used to tune the system based on energy and/or
performance requirements.
Newer AMD processors (>= Family 17h) add support for a subset of these
optional CPPC registers, based on ACPI v6.1.
The following are
From: Yazen Ghannam
The cppc_set_perf() currently only works for DESIRED_PERF. To make it
generic, pass in the index of the register being accessed.
Also, rename cppc_set_perf() to cppc_set_reg(). This is in preparation
for it to be used for more than just the DESIRED_PERF register.
Signed-off-
From: Yazen Ghannam
To enable CPPC on a processor, the OS should write a value "1" to the
CPPC Enable register. Add support for this register.
Since we have a new variable "enable" in cppc_perf_ctrls, rename it
and the associated functions i.e. cppc_perf_ctrls->cppc_ctrls and
cppc_get_perf()->cp
From: Yazen Ghannam
Newer AMD processors support a subset of the optional CPPC registers.
Add support for these optional registers.
Signed-off-by: Yazen Ghannam
[ carved out into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan Natarajan
---
drivers/acpi/cppc_acpi.c | 88
Add a new CPUFreq driver which exposes sysfs entries to control the
platform. To make use of this driver use a kernel commandline option.
Ex: amd_cpufreq=enable - Enable AMD CPUFreq driver for Fam17h and later
Also, place amd-cpufreq before acpi-cpufreq in the Makefile to give it
higher priority
Add attributes only for registers that are supported by the platform.
This prevents unsupported, optional registers from having sysfs entries
created.
Signed-off-by: Janakarajan Natarajan
---
drivers/acpi/cppc_acpi.c | 82 +---
1 file changed, 68 insertions(+)
Introduce two macros to help with checking the support for optional CPPC
registers.
CPC_SUP_BUFFER_ONLY ensures that an expected BUFFER only register has a
register type of ACPI_TYPE_BUFFER and is not NULL.
REG_SUPPORTED decides which check to perform based the expected type of
the CPPC register.
Add attributes for registers that are supported by the platform. This prevents
unsupported optional registers from having sysfs entries created.
Signed-off-by: Janakarajan Natarajan
---
drivers/acpi/cppc_acpi.c | 70
1 file changed, 56 insertions(+), 14 d
From: Yazen Ghannam
To enable CPPC on a processor, the OS should write a value "1" to the
CPPC Enable register. Add support for this register.
Signed-off-by: Yazen Ghannam
[ carved out into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan Natarajan
---
drivers/acpi/cppc_acpi.c |
From: Yazen Ghannam
Some CPPC registers can be used to configure the platform. To enable this,
create macros to define the show, store routines and create sysfs entries
with R/W permission.
Signed-off-by: Yazen Ghannam
[ carved into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan
CPPC (Collaborative Processor Performance Control) offers optional
registers which can be used to tune the system based on energy and/or
performance requirements.
Newer AMD processors add support for a subset of these optional CPPC
registers, based on ACPI v6.1.
The following are the supported CP
From: Yazen Ghannam
Newer AMD processors support a subset of the optional CPPC registers.
Create show, store and helper routines for supported CPPC registers.
Signed-off-by: Yazen Ghannam
[ carved out into a patch, cleaned up, productized ]
Signed-off-by: Janakarajan Natarajan
---
drivers/acp
From: Yazen Ghannam
The cppc_set_perf() currently only works for DESIRED_PERF. To make it
generic, pass in the index of the register being accessed.
Also, rename cppc_set_perf() to cppc_set_reg(). This is in preparation
for it to be used for more than just the DESIRED_PERF register.
Signed-off-
From: Yazen Ghannam
The show_cppc_data macro implicity uses define_one_cppc_ro. This will
prevent the creation of an attribute with read and write permissions.
Create a separate macro that defines a show attribute and creates
a read-only sysfs entry. This is in preparation for adding a macro
to
On 1/12/2017 3:20 AM, Peter Zijlstra wrote:
On Wed, Jan 11, 2017 at 10:02:17AM -0600, Janakarajan Natarajan wrote:
This patch updates the AMD uncore driver to support AMD Family17h
processors. In Family17h, there are two extra last level cache counters.
The counters are, therefore, allocated dy
On 11/16/2016 12:47 PM, Borislav Petkov wrote:
On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
This patch enables perf core PMU support for AMD family17h processors.
In family17h, there is no PMC-event constraint. All events, irrespective
of the type, can be measured usin
On 11/16/2016 11:30 AM, Peter Zijlstra wrote:
On Wed, Nov 16, 2016 at 11:01:53AM -0600, Janakarajan Natarajan wrote:
This patch enables perf core PMU support for AMD family17h processors.
In family17h, there is no PMC-event constraint. All events, irrespective
of the type, can be measured using
On 11/17/2016 12:46 AM, Ingo Molnar wrote:
* Janakarajan Natarajan wrote:
This patch enables perf core PMU support for AMD family17h processors. In
family17h, there is no PMC-event constraint. All events, irrespective of the
type, can be measured using any of the performance counters.
BTW.,
On 4/25/2017 4:44 PM, Janakarajan Natarajan wrote:
This patch prevents the value 0 from being used for the MWAITX timer.
Newer hardware has uncovered a bug in the software implementation of
using MWAITX for the delay function. A value of 0 for the timer is meant
to indicate that a timeout will n
On 6/6/2017 11:31 AM, Borislav Petkov wrote:
On Mon, Jun 05, 2017 at 11:13:18AM -0500, Janakarajan Natarajan wrote:
In Family 17h, L3 is the last level cache as opposed to L2 in previous
families. Avoid this name confusion and rename X86_FEATURE_PERFCT_L2 to
X86_FEATURE_PERFCTR_LLC to indicate
On 2/2/2018 2:03 PM, kbuild test robot wrote:
Hi Janakarajan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on tip/x86/core]
[also build test WARNING on v4.15]
[cannot apply to kvm/linux-next next-20180202]
[if your patch is applied to the wrong git tree, pleas
On 2/5/2018 7:43 AM, Radim Krcmar wrote:
2018-01-30 11:32-0600, Janakarajan Natarajan:
Expose the AMD Core Perf Extension flag to the guests.
Signed-off-by: Janakarajan Natarajan
---
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
@@ -365,7 +371,7 @@ static inline int __do_cpuid_ent(s
On 2/5/2018 1:24 PM, Janakarajan Natarajan wrote:
This patchset adds support for Perf Extension on AMD KVM guests.
When perf runs on a guest with family = 15h || 17h, the MSRs that are
accessed, when the Perf Extension flag is made available, differ from
the existing K7 MSRs. The accesses are to
On 11/9/2017 12:34 PM, Borislav Petkov wrote:
Subject: Re: [PATCH v2 3/4] Add support for AMD Core Perf Extension in guest
Btw, your subjects need a prefix:
"x86/kvm: Add guest support for the AMD core performance counters"
for example.
Okay.
On Mon, Nov 06, 2017 at 11:44:25AM -0600, Janak
On 11/15/2017 1:07 PM, Borislav Petkov wrote:
On Wed, Nov 15, 2017 at 01:04:03PM -0600, Natarajan, Janakarajan wrote:
So, when the amd_pmu_init is called, a query to guest_cpuid_family() gives a
value of -1.
And that is because...? And it can be fixed to give the proper guest family I
presume
On 11/16/2017 11:25 AM, Borislav Petkov wrote:
On Thu, Nov 16, 2017 at 11:13:47AM -0600, Natarajan, Janakarajan wrote:
On 11/15/2017 1:07 PM, Borislav Petkov wrote:
On Wed, Nov 15, 2017 at 01:04:03PM -0600, Natarajan, Janakarajan wrote:
So, when the amd_pmu_init is called, a query to
On 12/8/2017 4:39 PM, Janakarajan Natarajan wrote:
This patchset adds support for Perf Extension on AMD KVM guests.
When perf runs on a guest with family = 15h || 17h, the MSRs that are
accessed, when the Perf Extension flag is made available, differ from
the existing K7 MSRs. The accesses are t
On 11/17/2017 5:44 AM, Borislav Petkov wrote:
On Thu, Nov 16, 2017 at 12:00:11PM -0600, Natarajan, Janakarajan wrote:
Ah my apologies. So when the pmu is initialized the cpuid entries
aren't available then.
So let's see:
... kvm_arch_vcpu_create() ->
svm_create_vcpu() -&g
On 11/17/2017 5:44 AM, Borislav Petkov wrote:
On Thu, Nov 16, 2017 at 12:00:11PM -0600, Natarajan, Janakarajan wrote:
Ah my apologies. So when the pmu is initialized the cpuid entries
aren't available then.
So let's see:
... kvm_arch_vcpu_create() ->
svm_create_vcpu() -&g
On 12/5/2017 11:56 AM, Radim Krcmar wrote:
2017-12-01 13:30-0600, Natarajan, Janakarajan:
On 11/17/2017 5:44 AM, Borislav Petkov wrote:
On Thu, Nov 16, 2017 at 12:00:11PM -0600, Natarajan, Janakarajan wrote:
Ah my apologies. So when the pmu is initialized the cpuid entries
aren't avai
Commit-ID: d7cbbe49a9304520181fb8c9272d1327deec8453
Gitweb: https://git.kernel.org/tip/d7cbbe49a9304520181fb8c9272d1327deec8453
Author: Natarajan, Janakarajan
AuthorDate: Thu, 27 Sep 2018 15:51:55 +
Committer: Ingo Molnar
CommitDate: Tue, 2 Oct 2018 09:38:04 +0200
perf/x86/amd
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