From: Mohamed Mediouni
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
quirk.
On Apple processors, writes using the nGnRE device memory type get dropped in
flight,
getting to nowhere.
Signed-off-by: Mohamed Mediouni
Signed-off-by: Stan Skowronek
---
arch/arm64
across WFI.
As such, put a mechanism in cpu_ops to put a custom
sleep function instead.
- use nGnRnE instead of nGnRE on Apple processors
Device-nGnRE writes go to nowhere on Apple processors, as
such use MAIR to change those to Device-nGnRE writes.
Mohamed Mediouni (1):
arm64: mm: use nGnRnE
From: Stan Skowronek
WFI drops register state on Apple Silicon for SMP systems.
This hook will be used for a hardware workaround in the
Apple CPU start driver.
Signed-off-by: Stan Skowronek
---
arch/arm64/include/asm/cpu_ops.h | 2 ++
arch/arm64/kernel/cpu_ops.c | 6 ++
arch/arm64/
From: Stan Skowronek
On Apple processors, the timer is wired through FIQ.
As such, add FIQ support to the kernel.
Signed-off-by: Stan Skowronek
---
arch/arm64/include/asm/arch_gicv3.h | 2 +-
arch/arm64/include/asm/assembler.h | 8 ++--
arch/arm64/include/asm/daifflags.h | 4 +-
arch/arm6
From: Stan Skowronek
On Apple processors, the timer is wired through FIQ.
As such, add FIQ support to the kernel.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
arch/arm64/include/asm/arch_gicv3.h | 2 +-
arch/arm64/include/asm/assembler.h | 8 ++--
arch/arm64/include
for WFI on the hardware.
What is not present:
- Device tree, will be present in a future version of this
patchset
- More devices.
Thank you,
Mohamed Mediouni (1):
arm64: mm: use nGnRnE instead of nGnRE on Apple processors
Stan Skowronek (6):
arm64: kernel: FIQ support
arm64: kernel:
From: Stan Skowronek
Apple SoCs use the Apple AIC interrupt controller.
The Arm architectural timers is wired over FIQ on that hardware.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
.../interrupt-controller/apple,aic.yaml | 49
MAINTAINERS
From: Stan Skowronek
This driver is needed to spawn CPUs for SMP
on Apple Silicon platforms.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
.../devicetree/bindings/arm/cpus.yaml | 1 +
arch/arm64/kernel/Makefile| 1 +
arch/arm64/kernel
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
quirk.
On Apple processors, writes using the nGnRE device memory type get dropped in
flight,
getting to nowhere.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
arch/arm64/mm/proc.S | 26
> On 20 Jan 2021, at 14:16, Marc Zyngier wrote:
>
> Hi Mohamed,
>
> On 2021-01-20 11:36, Mohamed Mediouni wrote:
>> From: Stan Skowronek
>> On Apple processors, the timer is wired through FIQ.
>
> Which timer? There are at least 3, potentially 4 timers
> On 20 Jan 2021, at 18:11, Alexander Graf wrote:
>
> On 20.01.21 14:27, Mohamed Mediouni wrote:
>> From: Stan Skowronek
>> Apple SoCs use the Apple AIC interrupt controller.
>> The Arm architectural timers is wired over FIQ on that hardware.
>> Signed-off-
> On 20 Jan 2021, at 17:47, Alexander Graf wrote:
>
> On 20.01.21 14:27, Mohamed Mediouni wrote:
>> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
>> quirk.
>> On Apple processors, writes using the nGnRE device memory type get dropped
From: Stan Skowronek
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
arch/arm64/Kconfig.platforms | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6eecdef538bd..cc52519d4f67 100644
--- a/arch/arm64
From: Stan Skowronek
WFI drops register state on Apple Silicon for SMP systems.
This hook will be used for a hardware workaround in the
Apple CPU start driver.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
arch/arm64/include/asm/cpu_ops.h | 2 ++
arch/arm64/kernel
From: Stan Skowronek
This includes IPI support and a workaround for non-working WFI on
Apple processors.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
drivers/irqchip/irq-apple-aic.c | 177 +---
1 file changed, 165 insertions(+), 12 deletions
> On 21 Jan 2021, at 11:52, Arnd Bergmann wrote:
>
> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
> wrote:
>> --- a/arch/arm64/kernel/cpu_ops.c
>> +++ b/arch/arm64/kernel/cpu_ops.c
>
>> #if defined(CONFIG_STACKPROTECTOR) &&
>> !defi
> On 21 Jan 2021, at 13:44, Arnd Bergmann wrote:
>
> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
> wrote:
>
>> +#ifdef CONFIG_SMP
>> +static void apple_aic_ipi_send_mask(struct irq_data *d,
>> + const struct cpumask *
> On 21 Jan 2021, at 14:22, Marc Zyngier wrote:
>
> On 2021-01-21 12:50, Mohamed Mediouni wrote:
>>> On 21 Jan 2021, at 13:44, Arnd Bergmann wrote:
>>> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
>
> [...]
>
>>>> + aic.
> On 21 Jan 2021, at 13:47, Will Deacon wrote:
>
> On Thu, Jan 21, 2021 at 11:44:23AM +, Marc Zyngier wrote:
>> On 2021-01-21 11:27, Will Deacon wrote:
>>> On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
>>>> Use nGnRnE instead of
> On 21 Jan 2021, at 16:09, Arnd Bergmann wrote:
>
> On Thu, Jan 21, 2021 at 3:10 PM Marc Zyngier wrote:
>> On 2021-01-21 13:34, Mohamed Mediouni wrote:
>>>> On 21 Jan 2021, at 14:22, Marc Zyngier wrote:
>>> Because UART access adapters for the new M1
> On 21 Jan 2021, at 17:40, Rob Herring wrote:
>
> On Thu, Jan 21, 2021 at 6:52 AM Mohamed Mediouni
> wrote:
>>
>>
>>
>>> On 21 Jan 2021, at 13:44, Arnd Bergmann wrote:
>>>
>>> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
&
> On 21 Jan 2021, at 18:37, Rob Herring wrote:
>
> On Thu, Jan 21, 2021 at 10:43 AM Mohamed Mediouni
> wrote:
>>> On 21 Jan 2021, at 17:40, Rob Herring wrote:
>>> On Thu, Jan 21, 2021 at 6:52 AM Mohamed Mediouni
>>> wrote:
>>>>> On 21
> On 21 Jan 2021, at 19:15, Marc Zyngier wrote:
>
> On 2021-01-21 17:55, Will Deacon wrote:
>> On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
>>> On 2021-01-21 15:12, Mohamed Mediouni wrote:
>>>> Please ignore that patch.
>>>>
>
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