RE: [PATCH v4 00/22] perf: Add infrastructure and support for Intel PT

will have the Trace Memory Controller (TMC) in the Embedded Trace Router (ETR) configuration that can write directly to system memory. Many systems have a dedicated Embedded Trace Buffer (ETB). This is a dedicated SRAM for collecting trace that is not memory-mapped. It can only be accessed by t

RE: [PATCH V3 6/6] coresight-stm: adding driver for CoreSight STM component

Hi Chunyan, Chunyan Zhang wrote on 2016-02-17: > Hi Michael, > > One question below need to be clarified. > > On Fri, Feb 12, 2016 at 10:55 PM, Michael Williams > wrote: >> Mathieu Poirier [mailto:mathieu.poir...@linaro.org] wrote: >>> On 6 February 2016 at 04:04

RE: [RESEND PATCH V4 4/4] coresight-stm: adding driver for CoreSight STM component

Reviewed-by: Michael Williams This resend addresses my earlier concerns. > -Original Message- > From: Chunyan Zhang [mailto:zhang.chun...@linaro.org] > Sent: 08 March 2016 06:34 > To: mathieu.poir...@linaro.org; alexander.shish...@linux.intel.com > Cc: Mike Leach; Micha

RE: [PATCH V3 6/6] coresight-stm: adding driver for CoreSight STM component

Mathieu Poirier [mailto:mathieu.poir...@linaro.org] wrote: > On 6 February 2016 at 04:04, Chunyan Zhang wrote: >> From: Pratik Patel >> >> This driver adds support for the STM CoreSight IP block, allowing any >> system compoment (HW or SW) to log and aggregate messages via a >> single entity. >>

My Good Friend,

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