pdated Neil sent today: [0]
This is still working fine for me (driving the LPO clock of an AP6330
SDIO wifi chip).
Please note that I don't have a scope to measure the actual signal,
but I guess it's fine since my AP6330 is happy.
So feel free to keep my:
Tested-by: Martin Bl
ideally you should always try to include
> the driver author - particularly in the case of patches to a recent
> driver such as this one.
>
> To that end I've cc'd Martin.
thanks for spotting this (and providing a patch to fix it)
this looks good to me, so:
Acked-by: Martin Bl
On Thu, Nov 2, 2017 at 10:27 AM, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in pr_err error message
>
> Signed-off-by: Colin Ian King
Acked-by: Martin Blumenstingl
thank you for catching and fixing this!
> ---
> arch/arm/mach-meson/
On Tue, Nov 7, 2017 at 3:10 PM, Yixun Lan wrote:
> From: Xingyu Chen
>
> The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC,
> it is irrelevant for the SAR ADC.
>
> Signed-off-by: Xingyu Chen
> Signed-off-by: Yixun Lan
Reviewed-by: Martin Blumens
On Tue, Nov 7, 2017 at 6:37 AM, Yixun Lan wrote:
> From: Xingyu Chen
>
> Update the doc as the SAR ADC modules doesn't require "sana" clock.
>
> Singed-off-by: Xingyu Chen
> Signed-off-by: Yixun Lan
Acked-by: Martin Blumenstingl
> ---
> Documentation/de
you can add my ACK on both (32-bit and 64-bit) .dts patches:
Acked-by: Martin Blumenstingl
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 3 +--
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 3 +--
> 4 files changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/d
Hi Yixun,
On Tue, Nov 7, 2017 at 10:36 PM, Martin Blumenstingl
wrote:
> Hi Yixun,
>
> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan wrote:
>> patch [1/4]:
>> Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL,
>> the published datasheets[4] also has wrong descri
Hi Thomas,
thank you for this patch!
On Sun, Nov 5, 2017 at 3:12 PM, Greg Kroah-Hartman
wrote:
> On Sun, Nov 05, 2017 at 05:29:30AM +0100, Thomas Rohloff wrote:
>> Devices like DCF77 receivers need the baud-rate to be as low as 50.
>>
>> I have tested this on a Meson GXL device with uart_A.
>>
>
Hi Yixun,
On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote:
> Hi Neil:
>
>
> On 11/06/17 16:57, Neil Armstrong wrote:
>> On 06/11/2017 08:52, Yixun Lan wrote:
>>> According to the datasheet, in Meson-GXBB/GXL series,
>>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>>> while clock gat
On Thu, Aug 2, 2018 at 1:21 PM Jerome Brunet wrote:
>
> On Thu, 2018-08-02 at 09:52 +0200, Neil Armstrong wrote:
> > On 01/08/2018 22:23, Martin Blumenstingl wrote:
> > > Hi Neil,
> > >
> > > On Wed, Aug 1, 2018 at 12:05 PM Neil Armstrong
> > >
Hello Yixun, Hello Liang,
I have a few small comments inline below
additionally I tried to explain the reason behind
"amlogic,mmc-syscon", clkin0 and clkin1 so Rob (or the devicetree
maintainers in general) can give feedback. feel free to correct me
wherever I'm wrong or provide additional notes i
meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
> clk: meson: clk-pll: remove od parameters
> clk: meson: clk-pll: drop hard-coded rates from pll tables
for the whole series:
Reviewed-by: Martin Blumenstingl
as well as:
Tested-by: Martin Blumenstingl
(tested on Meson8b / Odroid-C1, even CPU frequency scaling still works
with my out-of-tree patches)
Regards
Martin
roducing
of_get_compatible_child is also backported
do we have to inform Greg somehow?
> Cc: Carlo Caione
> Cc: Martin Blumenstingl
> Cc: Ulf Hansson
> Signed-off-by: Johan Hovold
Acked-by: Martin Blumenstingl
Regards
Martin
Hi Neil,
On Fri, Jul 20, 2018 at 11:40 AM Neil Armstrong wrote:
>
> Add the clocks entries used in the video clock path, the clock path
> is doubled to permit having different synchronized clocks for different
> parts of the video pipeline.
maybe you can add the comment about CLK_GET_RATE_NOCACHE
Hi Neil,
On Fri, Jul 20, 2018 at 11:40 AM Neil Armstrong wrote:
>
> Add support the VID_PLL fully programmable divider used right after the
> HDMI PLL clock source. It is used to achieve complex fractional division
> with a programmble bitfield.
I assume you have no other information that the S91
e some questions inline, but with those answered:
Acked-by: Martin Blumenstingl
> ---
> drivers/clk/meson/axg.c | 28 ---
> drivers/clk/meson/clk-pll.c | 47
> -
> drivers/clk/meson/clkc.h| 1
Hi Jerome,
On Tue, Jul 17, 2018 at 11:56 AM Jerome Brunet wrote:
>
> Remove od parameters from pll clocks and add post dividers clocks
> instead. Some clock, especially the one which feature several ods,
> may provide output between those ods. Also, some drivers, such
> as the hdmi driver, may re
On Thu, Jul 19, 2018 at 10:44 AM Neil Armstrong wrote:
>
> On 17/07/2018 11:56, Jerome Brunet wrote:
> > Putting hard-coded rates inside the parameter tables assumes that
> > the parent is known and will never change. That's a big assumption
> > we should not make.
> >
> > We have everything we ne
Hi Jerome,
On Tue, Jul 17, 2018 at 11:56 AM Jerome Brunet wrote:
>
> This patchset is yet another round of update to the amlogic pll driver.
>
> 1) Enable bit is added so we don't rely on the bootloader or the init
> value to enable to pll device.
> 2) OD post dividers are removed from the
Hi Jerome,
On Sat, Jul 21, 2018 at 10:46 PM Jerome Brunet wrote:
>
> On Sat, 2018-07-21 at 22:16 +0200, Martin Blumenstingl wrote:
> > > We could even add ranges instead of table when we know the PLL supports a
> > > well-known continuous dividers range.
> >
&
Hi Jerome,
On Sat, Jul 21, 2018 at 10:42 PM Jerome Brunet wrote:
>
> On Sat, 2018-07-21 at 22:01 +0200, Martin Blumenstingl wrote:
> > > +static struct clk_regmap gxbb_hdmi_pll_od = {
> > > + .data = &(struct clk_regmap_div_data){
> > > +
Hi Neil,
On Wed, Aug 1, 2018 at 12:05 PM Neil Armstrong wrote:
>
> The Amlogic Meson GX and AXG SoCs needs to do a Secure Monitor call to
> set the TEST_N pin direction.
> This patch adds a "smc" boolean to the bank structure to differentiate
> the TEST_N bank and call the Secure Monitor in the _
Hi Jerome,
On Tue, Jul 24, 2018 at 2:53 PM Jerome Brunet wrote:
>
> The main purpose of this patchset is to add the audio devices on amlogic's
> AXG SoCs.
>
> Some codecs require some power supplies. This is why the 3 first patches
> deal with the S400 power supplies, even if some are not related
Hi Jerome,
On Tue, Jul 24, 2018 at 3:09 PM Jerome Brunet wrote:
>
> Add the es7241 analog to digital converter which is fed by the
> lienin jack of the s400
>
> Signed-off-by: Jerome Brunet
> ---
> arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 10 ++
> 1 file changed, 10 insertions(+
Hi Jerome,
On Wed, Jul 25, 2018 at 11:19 PM wrote:
>
> On Wed, 2018-07-25 at 21:11 +0200, Martin Blumenstingl wrote:
> > nit-pick: one patch uses "arm64: dts: meson-axg: s400" in the subject
> > while other patches that are touching the s400 board aren't
>
On Wed, Jul 11, 2018 at 3:06 PM Jian Hu wrote:
>
>
>
> On 2018/7/10 17:29, Jerome Brunet wrote:
> > On Mon, 2018-07-09 at 19:12 +0800, Jian Hu wrote:
> >> Add new binding for Meson-G12A SoC Everything-Else part
> >
> > nitpick: I would prefer if the words 'clock' and 'controller' was somewhere
>
On Tue, Jul 10, 2018 at 12:07 AM Martin Blumenstingl
wrote:
>
> Hi Linus,
>
> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij wrote:
> >
> > On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan wrote:
> > >
> > > This patch series try to add pinctrl d
Hi Neil,
On Wed, Jul 11, 2018 at 10:37 AM Neil Armstrong wrote:
>
> On 09/07/2018 23:41, Kevin Hilman wrote:
> > Martin Blumenstingl writes:
> >
> >> Hi Neil,
> >>
> >> On Wed, Jul 4, 2018 at 10:41 AM Neil Armstrong
> >> wrote:
> >
the commit message) stating that GPIOE is
actually located (checked with the ASIC / hardware team) in the AO
bank
> Signed-off-by: Yixun Lan
with that:
Acked-by: Martin Blumenstingl
> ---
> include/dt-bindings/gpio/meson-g12a-gpio.h | 114 +
> 1 file changed, 114
ot; (this is for the "HIZ" line of the the pwm_ao_a
controller) -> to have a consistent naming it would either have to be
"uart_ao_a_rx" or "pwm_hiz_ao_a"
> Signed-off-by: Yixun Lan
with the few notes fixed (see below):
Acked-by: Martin Blumenstingl
> ---
Hi Yixun,
On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan wrote:
> Describe the pinctrl info for the UART controller which is found
> in the Meson-AXG SoCs.
>
> Signed-off-by: Yixun Lan
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97
> ++
> 1 file changed, 97 ins
rts were a workaround for a wrong syscon-reboot mask. With a
> mask set which includes the GPHY resets, these resets aren't required
> any more.
>
> Fixes: 126534141b45 ("MIPS: lantiq: Add a GPHY driver which uses the RCU
> syscon-mfd")
> Cc: sta...@vger.kernel.org
Hello Liang,
On Thu, Sep 27, 2018 at 10:19 AM Liang Yang wrote:
>
> Hello Martin,
>
> On 9/22/2018 11:32 PM, Martin Blumenstingl wrote:
> > Hello,
> >
> > On Thu, Sep 20, 2018 at 10:51 AM Jianxin Pan
> > wrote:
> > [snip]
> >> +
Hi Jerome,
On Thu, Nov 22, 2018 at 10:05 AM Jerome Brunet wrote:
>
> On Fri, 2018-11-16 at 21:53 +0100, Martin Blumenstingl wrote:
> > This is the successor to my previous series "meson8b: add the CPU_DIV16
> > clock for the ARM TWD" from [0]. I decided to not send th
sheet%20V0.8%2020150126.pdf
[2] https://patchwork.kernel.org/cover/10687023/
Martin Blumenstingl (4):
dt-bindings: clock: meson8b: export the CPU post dividers
clk: meson: clk-regmap: add read-only gate ops
clk: meson: meson8b: rename cpu_div2/cpu_div3 to
cpu_in_div2/cpu_in_div3
clk: me
way that the clock can
stay enabled when changing the mux). It's still good practise to
describe this clock even if we're not supposed to modify it. Thus
this uses the read-only gate ops.
Signed-off-by: Martin Blumenstingl
Acked-by: Jerome Brunet
ck naming could be
misleading as we have "cpu_div2" as well as "cpu_clk_div2".
Rename the existing "cpu_in" dividers so the name of the divider's
parent is part of the divider clock's name.
Signed-off-by: Martin Blumenstingl
Acked-by: Jerome Brunet
---
dr
There are four CPU clock post dividers:
- ABP
- PERIPH (used as input for the ARM global timer and ARM TWD timer)
- AXI
- L2 DRAM
Export these so we can use them in .dts files.
Signed-off-by: Martin Blumenstingl
Acked-by: Jerome Brunet
---
include/dt-bindings/clock/meson8b-clkc.h | 4
1
hanging the mux
selection. Typically this bit is set to 0 since the clock muxes can
switch without glitches.".
This adds new read-only ops for gate clocks so we can describe these
clocks in our clock controller drivers while ensuring that we can't
accidentally modify the registers.
Signed-of
likely) failure case of devm_kasprintf() should be fine here.
>
> Signed-off-by: Nicholas Mc Guire
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic
> Meson SoCs")
Acked-by: Martin Blumenstingl
thank you for the patch!
I tested the non-error ca
> (unlikely) failure case of devm_kasprintf() should be fine here.
>
> Signed-off-by: Nicholas Mc Guire
> Fixes: ed80a13bb4c4 ("mmc: meson-mx-sdio: Add a driver for the Amlogic Meson8
> and Meson8b SoCs")
Acked-by: Martin Blumenstingl
thank you for the patch!
I tested the
in the PWM, Ethernet and MMC
drivers. It also fixes the problem with debugfs.
The idea is shamelessly taken from commit b96e9eb62841c5 ("pwm: meson:
Fix mux clock names").
Fixes: 3921db46a8c5bc ("iio: Convert to using %pOF instead of full_name")
Signed-off-by: Martin Blumenstin
eant to be applied on top of "iio: adc: meson-saradc:
check for devm_kasprintf failure" from [0]
[0] https://patchwork.kernel.org/patch/10693631/
Martin Blumenstingl (1):
iio: adc: meson-saradc: fix internal clock names
drivers/iio/adc/meson_saradc.c | 8
1 file changed
Hi Neil,
On Thu, Nov 22, 2018 at 9:26 AM Neil Armstrong wrote:
>
> Hi Martin,
>
> On 21/11/2018 22:53, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Wed, Nov 21, 2018 at 12:19 PM Neil Armstrong
> > wrote:
> >>
> >> The GXL Docume
Hi Daniel,
On Sun, Nov 18, 2018 at 2:27 AM Daniel Lezcano
wrote:
>
> On 15/11/2018 23:46, Martin Blumenstingl wrote:
> > While trying to add support for the ARM TWD Timer and the ARM Global
> > Timer on Meson8, Meson8b and Meson8m2 (ARM Cortex-A5 and Cortex-A9 SoCs)
> &g
On Fri, Nov 23, 2018 at 7:15 AM Daniel Lezcano
wrote:
>
> On 22/11/2018 23:12, Martin Blumenstingl wrote:
> > Hi Daniel,
> >
> > On Sun, Nov 18, 2018 at 2:27 AM Daniel Lezcano
> > wrote:
> >>
> >> On 15/11/2018 23:46, Martin Blumenstingl wrote:
&
On Fri, Nov 23, 2018 at 3:40 PM Neil Armstrong wrote:
>
> On 22/11/2018 22:40, Martin Blumenstingl wrote:
> > This is the successor to my previous series "meson8b: add the CPU_DIV16
> > clock for the ARM TWD" from [0]. I decided to not send this as v2 of
> > the
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 24
arch/arm/boot/dts/meson8.dtsi | 12 +++-
arch/arm/boot/dts/meson8b.dtsi | 12 +++-
3 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/meson.dtsi
VEL_LOW to prevent "GIC: PPI13 is secure or misconfigured"
message during boot, use pre-processor macros to specify the IRQ,
added the correct clock, dropped TWD watchdog node since there's no
driver for it anymore ]
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8
k (which is derived from the CPU clock).
[0] https://patchwork.kernel.org/patch/7797581/
[1] https://patchwork.kernel.org/cover/10687005/
[2] http://lists.infradead.org/pipermail/linux-amlogic/2018-November/009136.html
Martin Blumenstingl (6):
ARM: meson: select HAVE_ARM_TWD and ARM_GLOBAL
CPU clock). Unfortunately
the arm_global_timer driver does not handle changes to the clock rate
yet.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.
allows us to add the timers
to the SoC.dtsi files.
Signed-off-by: Martin Blumenstingl
---
arch/arm/mach-meson/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index d51cfda953d4..b16831697183 100644
--- a/arch/arm/mach-meson/Kc
t;GIC: PPI13 is secure or misconfigured"
message during boot, use pre-processor macros to specify the IRQ,
added the correct clock, dropped TWD watchdog node since there's no
driver for it anymore ]
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8b.dtsi | 7 +
nately
the arm_global_timer driver does not handle changes to the clock rate
yet.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8b.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index a3
Hello Hanjie, Hello Yue,
sorry for being late with my comment
On Tue, Oct 9, 2018 at 3:53 AM Hanjie Lin wrote:
>
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
> controll
Hi Neil,
On Wed, Nov 21, 2018 at 12:19 PM Neil Armstrong wrote:
>
> The GXL Documentation specifies 12 bits for the Fractional bit field,
> bit the last bits have a different purpose that we cannot handle right
> now, so update the bitwidth to have correct fractional calculations.
I assume you ha
Hi Kevin,
On Thu, Nov 29, 2018 at 1:30 AM Kevin Hilman wrote:
>
> Martin Blumenstingl writes:
>
> > Some Meson8b boards (Odroid-C1, EC-100) use a PWM regulator which is the
> > voltage supply of the CPU cores (this regulator is typically called
> > "VCCK").
ge
regulator on this board is has a minimum output of 0.86V and a maximum
output of 1.14V. The recommended settings are added with this patch
instead of using the values that are only valid for one board.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/m
ork.kernel.org/cover/10696327/
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-November/009137.html
[2] https://patchwork.kernel.org/cover/10685241/
Martin Blumenstingl (2):
ARM: dts: meson: meson8: add the CPU OPP table
ARM: dts: meson: meson8b: add the CPU OPP tables
arch
The values are taken from Amlogic's 3.10 kernel sources.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8b.dtsi | 66 ++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
Hi Kevin,
On Fri, Nov 30, 2018 at 12:28 AM Kevin Hilman wrote:
>
> Martin Blumenstingl writes:
>
> > Hi Kevin,
> >
> > On Thu, Nov 29, 2018 at 1:30 AM Kevin Hilman wrote:
> >>
> >> Martin Blumenstingl writes:
> >>
> >> > Some M
Hi Daniel, Hi Thomas,
On Sun, Oct 28, 2018 at 1:55 PM Martin Blumenstingl
wrote:
>
> While trying to add support for the ARM TWD Timer and the ARM Global
> Timer on Meson8, Meson8b and Meson8m2 (ARM Cortex-A5 and Cortex-A9 SoCs)
> I did a review of the existing driver.
> Unfortuna
clock tree since the bug which
locked up the system is now fixed (by switching the CPU clock temporary
to run off XTAL while changing the CPU clock tree).
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/meson8b.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
PLL changing the
latter results in a full system lockup.
Fix this system lockup by switching the CPU clock to run off the XTAL
while we are changing the any of the clocks in the CPU clock tree.
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/meson8b.c | 63
und). This
worked fine on my Meson8b Odroid-C1 and EC-100 boards as well as my
Meson8m2 board.
Martin Blumenstingl (7):
clk: meson: meson8b: run from the XTAL when changing the CPU frequency
clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
clk: meson: clk-pll: check if the cloc
this one)
while running "stress --cpu 4" in the background. This caused sporadic
hangs where the whole system would fully lock up.
Amlogic's 3.10 kernel code also does not use the cpu_div3 clock either
when changing the CPU clock.
Signed-off-by: Martin Blumenstingl
---
dr
sys_pll) are read-only. However, once we allow
modifications to the clocks in that tree we will need this.
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/meson8b.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/me
's voltage regulator design is bad, some missing bits
for these values in our clk-pll driver, etc.). Thus the following M
values from the Amlogic 3.10 GPL kernel sources are skipped as of now:
69, 70, 71, 72, 73, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98
Signed-off-by: Martin Blume
sed clocks" mechanism checks for this. Everything
else still uses the ref-counting (internal to the common clock
framework) when clk_enable is called.
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/clk-pll.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/meson/clk-pll.
amework up until the sys_pll clock. If we reset the PLL
unconditionally in meson_clk_pll_enable the CPU will be stopped (on
Meson8, Meson8b and Meson8m2).
To prevent this we simply check if the PLL is already enabled and do
reset the PLL if it's already enabled and locked.
Signed-off-by: Martin B
kernel so we can configure the CPU voltage early in the boot process.
Signed-off-by: Martin Blumenstingl
---
arch/arm/configs/multi_v7_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 63
Hi Daniel,
thanks for your feedback!
On Thu, Nov 15, 2018 at 2:35 AM Daniel Lezcano
wrote:
>
> On 28/10/2018 13:55, Martin Blumenstingl wrote:
> > This makes the driver use the names from S805 datasheet for the
> > preprocessor #defines. This makes it easier to sp
's voltage regulator design is bad, some missing bits
for these values in our clk-pll driver, etc.). Thus the following M
values from the Amlogic 3.10 GPL kernel sources are skipped as of now:
69, 70, 71, 72, 73, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98
Signed-off-by: Martin Blumen
cks for this. Everything
else still uses the ref-counting (internal to the common clock
framework) when clk_enable is called.
Signed-off-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
---
drivers/clk/meson/clk-pll.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/d
meson_clk_pll_enable()
instead of calling meson_clk_pll_is_enabled() directly (this matches
the implementation of sclk-div.c)
- documented the dependencies of this series in the cover-letter
- dropped "RFC" prefix
- collected Jerome's Acked-/Reviewed-by's (thanks for the quick
this one)
while running "stress --cpu 4" in the background. This caused sporadic
hangs where the whole system would fully lock up.
Amlogic's 3.10 kernel code also does not use the cpu_div3 clock either
when changing the CPU clock.
Signed-off-by: Martin Blumenstingl
Reviewed-by
clock tree since the bug which
locked up the system is now fixed (by switching the CPU clock temporary
to run off XTAL while changing the CPU clock tree).
Signed-off-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
---
drivers/clk/meson/meson8b.c | 12 ++--
1 file changed, 6 insertions
sys_pll) are read-only. However, once we allow
modifications to the clocks in that tree we will need this.
Signed-off-by: Martin Blumenstingl
Acked-by: Jerome Brunet
---
drivers/clk/meson/meson8b.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson
PLL changing the
latter results in a full system lockup.
Fix this system lockup by switching the CPU clock to run off the XTAL
while we are changing the any of the clocks in the CPU clock tree.
Signed-off-by: Martin Blumenstingl
Reviewed-by: Jerome Brunet
---
drivers/clk/meson/meson8b.c | 63
ll.
[0] https://patchwork.kernel.org/cover/10658591/
Martin Blumenstingl (2):
clocksource: meson6_timer: use register names from the datasheet
clocksource: meson6_timer: implement ARM delay timer
drivers/clocksource/meson6_timer.c | 128 +++--
1 file changed, 85 insertions(+
datasheet.
Signed-off-by: Martin Blumenstingl
---
drivers/clocksource/meson6_timer.c | 108 +
1 file changed, 64 insertions(+), 44 deletions(-)
diff --git a/drivers/clocksource/meson6_timer.c
b/drivers/clocksource/meson6_timer.c
index 92f20991a937..23c7638e2bb3 100644
clock off the XTAL while
changing the PLL or it's dividers. After changing the CPU clocks we need
to wait a few usecs for the clock to become stable. So having an
udelay() implementation that doesn't depend on the CPU frequency is
beneficial.
Suggested-by: Jianxin Pan
Signed-off-
y assume that the necessary bias (if any)
> is already provided by the pin function itself.
>
> Signed-off-by: Jerome Brunet
Acked-by: Martin Blumenstingl
my Odroid-C1 still boots fine from SD card and Ethernet (ping) also still works
Kevin, can you please move this patch from your v4.21
k has two clock inputs. This also adds
them.
NOTE: the alias "timer_abcde" was chosen because there's a second
timer instance (F..I which are similar to A..D and J which is
similar to E).
[0] https://patchwork.kernel.org/cover/10658573/
Martin Blumenstingl (2):
ARM: dts: meson:
works
internally.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 2 +-
arch/arm/boot/dts/meson6.dtsi | 5 +
arch/arm/boot/dts/meson8.dtsi | 5 +
arch/arm/boot/dts/meson8b.dtsi | 5 +
4 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boo
The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events.
For each of these a separate interrupt exists.
Pass these interrupts to allow using the timers other than TIMER A.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson.dtsi | 5 -
1 file changed, 4 insertions
atasheet states that this should
be set to 1 to disable the clock. the default value is 0. there is
also a hint that these are "just in case" bits which is why I set
these clocks to CLK_IS_CRITICAL).
Signed-off-by: Martin Blumenstingl
---
dri
There are four CPU clock post dividers:
- ABP
- PERIPH (used as input for the ARM global timer and ARM TWD timer)
- AXI
- L2 DRAM
Export these so we can use them in .dts files.
Signed-off-by: Martin Blumenstingl
---
include/dt-bindings/clock/meson8b-clkc.h | 4
1 file changed, 4
ck naming could be
misleading as we have "cpu_div2" as well as "cpu_clk_div2".
Rename the existing "cpu_in" dividers so the name of the divider's
parent is part of the divider clock's name.
Signed-off-by: Martin Blumenstingl
---
drivers/clk/meson/mes
iver.
The result of this is that we can use the PERIPH clock which clocks
the ARM TWD timer. I will send a separate series to add the TWD timer.
[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html
[1] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
On Fri, Nov 16, 2018 at 9:53 PM Martin Blumenstingl
wrote:
>
> This is the successor to my previous series "meson8b: add the CPU_DIV16
> clock for the ARM TWD" from [0]. I decided to not send this as v2 of
> the original series because the PERIPH clock is not the CPU_DIV16 c
n8, Meson8b and Meson8m2 as well
>
> Signed-off-by: Neil Armstrong
with the comment above and below:
Acked-by: Martin Blumenstingl
> ---
> .../bindings/soc/amlogic/clk-measure.txt | 15 +++
> 1 file changed, 15 insertions(+)
> create mode 100644
>
Hi Neil,
On Wed, Nov 14, 2018 at 2:18 PM Neil Armstrong wrote:
>
> The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
> clock paths frequencies.
I would remove "GX" from that sentence
> The precision is determined by stepping into the divider until the counter
> overflo
Hi Neil,
On Tue, Nov 6, 2018 at 3:59 PM Neil Armstrong wrote:
>
> Add the clocks entries used in the video clock path, the clock path
> is doubled to permit having different synchronized clocks for different
> parts of the video pipeline.
>
> All dividers are flagged with CLK_GET_RATE_NOCACHE, a
Hi Neil,
On Tue, Nov 6, 2018 at 3:59 PM Neil Armstrong wrote:
>
> In an attempt to better describe the HDMI PLL, a single DCO clock was
> left for GXBB and GXL, but the GXL DCO does not have a pre-multiplier.
>
> This patch adds back a GXL specific HDMI PLL DCO with xtal as parent.
according to t
On Sun, Nov 18, 2018 at 2:51 PM Neil Armstrong wrote:
>
> The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
> clock paths frequencies.
> This patch adds the node in the top-level meson-gx dtsi.
>
> Signed-off-by: Neil Armstrong
Acked-by: Martin Blumenstingl
y summary and each clock can be measured
> individually aswell.
>
> Cc: Martin Blumenstingl
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
I have successfully tested it on Odroid-C1:
Tested-by: Martin Blumenstingl
On Sun, Nov 18, 2018 at 2:51 PM Neil Armstrong wrote:
>
> The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
> clocks frequencies.
> The precision is determined by stepping into the duration until the counter
> overflows.
> The debugfs shows a pretty summary and each cloc
Hi Ben,
On Wed, Dec 5, 2018 at 2:36 PM Ben Dooks wrote:
>
> On 02/12/2018 22:08, Martin Blumenstingl wrote:
> > Add support for the RTC block on the 32-bit Amlogic Meson6, Meson8,
> > Meson8b and Meson8m2 SoCs.
> >
> > The RTC is split in to two parts, which a
/io.h#L61
[1]
https://github.com/endlessm/linux-meson/blob/cd4096c3ff4eb5b8a8a5581bb46508601c5470dc/arch/arm/mach-meson8/include/mach/io.h#L53
[2]
https://github.com/endlessm/linux-meson/blob/cd4096c3ff4eb5b8a8a5581bb46508601c5470dc/arch/arm/mach-meson8b/include/mach/io.h#L53
Martin Blumenstin
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