[PATCH 0/9] Intel Processor Trace virtulization enabling

From: Chao Peng Hi All, Here is a patch-series which adding Processor Trace enabling in KVM guest. You can get It's software developer manuals from: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf In Chapter 5 INTEL

[PATCH 3/9] KVM: x86: add Intel processor trace virtualization mode

simultaneous and output to their respective buffer. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 7 arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 6 +++ arch/x86/kvm/vmx.c | 88

[PATCH 5/9] KVM: x86: implement intel processor trace virtualization callbacks

From: Chao Peng Implement Intel processor trace virtualization callbacks to suppress host event in guest only mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch

[PATCH 4/9] perf/x86/intel/pt: add Intel processor trace virtualization call backs

From: Chao Peng Add Intel processor trace virtualization call backs to suppress host event in guest only mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 21 + arch/x86/include/asm/intel_pt.h | 9 + 2 files changed

[PATCH 6/9] KVM: x86: add Intel processor trace cpuid emulataion

From: Chao Peng Expose Intel processor trace cpuid to guest. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 23 +-- arch/x86/kvm/svm.c | 6 ++ arch/x86/kvm/vmx.c

[PATCH 1/9] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header

From: Chao Peng Intel processor trace virtualization enabling in guest need to use these MSR bits, so move then to public header msr-index.h. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.h | 37 - arch/x86/include

[PATCH 8/9] KVM: x86: Implement Intel processor trace context switch

From: Chao Peng Load/Store Intel processor trace register in context switch. MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS, other MSRs are loaded/stored manaully. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 100

[PATCH 7/9] KVM: x86: add Intel processor trace context for each vcpu

From: Chao Peng Add a date structure to save Intel processor trace context. It mainly include all the MSR of Intel processor trace. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx.c

[PATCH 9/9] KVM: x86: Disable intercept for Intel processor trace MSRs

From: Chao Peng Trap for Intel processor trace is none sense. Pass through to guest directly. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 3c9ce3e

[PATCH 2/9] perf/x86/intel/pt: change pt_cap_get() to a public function

From: Chao Peng Change pt_cap_get() to a public function so that KVM can access it. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 3 ++- arch/x86/events/intel/pt.h | 18 -- arch/x86/include/asm/intel_pt.h | 20

[patch v2 8/8] KVM: x86: Disable intercept for Intel processor trace MSRs

From: Chao Peng Pass through Intel processor trace to guest directly. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 8f61a8d..01447e2 100644 --- a/arch

[patch v2 7/8] KVM: x86: add Intel PT msr RTIT_CTL read/write

out write this msr in L1 VMX operation. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 091120e..8f61a8d 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/

[patch v2 6/8] KVM: x86: Implement Intel processor trace context switch

From: Chao Peng Load/Store Intel processor trace register in context switch. MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS, other MSRs are loaded/stored manaully. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 75

[patch v2 5/8] KVM: x86: add Intel processor trace context for each vcpu

From: Chao Peng Add a date structure to save Intel processor trace context. It mainly include all the MSR of Intel processor trace. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx.c

[patch v2 4/8] KVM: x86: add Intel processor trace cpuid emulataion

From: Chao Peng Expose Intel processor trace cpuid to guest. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 23 +-- arch/x86/kvm/svm.c | 6 ++ arch/x86/kvm/vmx.c

[patch v2 2/8] perf/x86/intel/pt: change pt_cap_get() to a public function

From: Chao Peng Change pt_cap_get() to a public function so that KVM can access it. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 3 ++- arch/x86/events/intel/pt.h | 18 -- arch/x86/include/asm/intel_pt.h | 20

[patch v2 0/8] Intel Processor Trace virtulization enabling

From: Chao Peng Hi All, Here is a patch-series which adding Processor Trace enabling in KVM guest. You can get It's software developer manuals from: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf In Chapter 5 INTEL

[patch v2 1/8] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header

From: Chao Peng Intel processor trace virtualization enabling in guest need to use these MSR bits, so move then to public header msr-index.h. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.h | 37 - arch/x86/include

[patch v2 3/8] KVM: x86: add Intel processor trace virtualization mode

-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 6 arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 6 arch/x86/kvm/vmx.c | 73 +--- 4 files changed, 82 insertions(+), 4

[PATCH v6 00/11] Intel Processor Trace virtualization enabling

n KVM: x86: Add Intel Processor Trace virtualization mode KVM: x86: Add Intel Processor Trace cpuid emulation KVM: x86: Add Intel processor trace context for each vcpu KVM: x86: Implement Intel Processor Trace context switch KVM: x86: Implement Intel Processor Trace MSRs read/write KVM:

[PATCH v6 11/11] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest

exception (#GP). Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 27185da..77a28f3 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3763,7 +3763,8 @@ static int

[PATCH v6 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function

From: Chao Peng Change pt_cap_get() to a public function so that KVM can access it. Introduce new capablility PT_CAP_output_subsys to support of output to Trace Transport subsystem. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 4 +++- arch/x86

[PATCH v6 10/11] KVM: x86: Set intercept for Intel PT MSRs

From: Chao Peng Disable interrcept Intel PT MSRs only when Intel PT is enabled in guest. But MSR_IA32_RTIT_CTL will alway be intercept. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 20 1 file changed, 20 insertions(+) diff --git a/arch/x86

[PATCH v6 09/11] KVM: x86: Implement Intel Processor Trace MSRs read/write

From: Chao Peng Implement Intel Processor Trace MSRs read/write. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 8 ++ arch/x86/kvm/vmx.c | 163 arch/x86/kvm/x86.c | 33 +++- 3

[PATCH v6 05/11] KVM: x86: Add Intel Processor Trace cpuid emulation

From: Chao Peng Expose Intel Processor Trace to guest only when PT work in HOST_GUEST mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 22 -- arch/x86/kvm/svm.c | 6

[PATCH v6 06/11] KVM: x86: Add Intel processor trace context for each vcpu

From: Chao Peng Add a data structure to save Intel Processor Trace context. It mainly include the value of Intel PT host/guest MSRs and guest CPUID information. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 19 +++ 1 file changed, 19 insertions

[PATCH v6 03/11] perf/x86/intel/pt: Introduce a new function to get the capability of Intel PT

Because of the guest CPUID information may different with host(some bits may mask off in guest) so introduce a new function to get the capability of Intel PT. Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 10 -- arch/x86/include/asm/intel_pt.h | 2 ++ 2 files changed

[PATCH v6 04/11] KVM: x86: Add Intel Processor Trace virtualization mode

-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 6 arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 8 + arch/x86/kvm/vmx.c | 68 +--- 4 files changed, 79 insertions(+), 4

[PATCH v6 08/11] KVM: x86: Introduce a function to initialize the PT configuration

Initialize the Intel PT configuration when cpuid update. Include cpuid inforamtion, rtit_ctl bit mask and the number of address ranges. Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 69 ++ 1 file changed, 69 insertions(+) diff --git a

[PATCH v6 07/11] KVM: x86: Implement Intel Processor Trace context switch

-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 60 ++ 1 file changed, 60 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 940df0e..34bcb30 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c

[PATCH v6 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header

From: Chao Peng Intel Processor Trace virtualization enabling in guest need to use these MSR bits, so move them to public header msr-index.h. Introduce RTIT_CTL_FABRIC_EN and sync the definitions to latest spec. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel

[PATCH v8 00/12] Intel Processor Trace virtualization enabling

r Trace virtualization mode KVM: x86: Add Intel Processor Trace cpuid emulation KVM: x86: Add Intel Processor Trace context switch for each vcpu KVM: x86: Implement Intel Processor Trace MSRs read/write emulation KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang (5): perf/x

[PATCH v8 02/12] perf/x86/intel/pt: Change pt_cap_get() to a public function

From: Chao Peng Change pt_cap_get() to a public function that KVM can access this function to check if specific feature is supported on hardware. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 3 ++- arch/x86/events/intel/pt.h | 21

[PATCH v8 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs

-by: Luwei Kang --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 5e8d156..f163f04 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -112,6 +112,7

[PATCH v8 06/12] KVM: x86: Add Intel Processor Trace virtualization mode

From: Chao Peng Intel PT virtualization can be work in one of 2 possible modes: a. system-wide: trace both host and guest and output to host buffer; b. host-guest: trace host/guest simultaneous and output to their respective buffer. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang

[PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header

From: Chao Peng Intel Processor Trace virtualization enabling in KVM guest need to access these MSRs bit definitions, so move them to public header file msr-index.h. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.h | 37

[PATCH v8 05/12] perf/x86/intel/pt: Introduce a new function to get capability of Intel PT

New function pt_cap_decode() will be invoked in KVM to check if a specific capability is available in KVM guest. Another function pt_cap_get() can only check the hardware capabilities but this may different with KVM guest because some features may not be exposed to guest. Signed-off-by: Luwei

[PATCH v8 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation

From: Chao Peng Expose Intel Processor Trace to guest only when PT work in HOST_GUEST mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 22 -- arch/x86/kvm/svm.c | 6

[PATCH v8 08/12] KVM: x86: Add Intel Processor Trace context switch for each vcpu

From: Chao Peng Load/Store Intel processor trace register in context switch. MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS. In HOST_GUEST mode, we need load/resore PT MSRs only when PT is enabled in guest. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c

[PATCH v8 09/12] KVM: x86: Introduce a function to initialize the PT configuration

Initialize the Intel PT configuration when cpuid update. Include cpuid inforamtion, rtit_ctl bit mask and the number of address ranges. Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 69 ++ 1 file changed, 69 insertions(+) diff --git a

[PATCH v8 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write

From: Chao Peng Disable intercept Intel PT MSRs only when Intel PT is enabled in guest. But MSR_IA32_RTIT_CTL will alway be intercept. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/arch

[PATCH v8 10/12] KVM: x86: Implement Intel Processor Trace MSRs read/write emulation

From: Chao Peng This patch implement Intel Processor Trace MSRs read/write emulation. Intel PT MSRs read/write need to be emulated when Intel PT MSRs is intercepted in guest and during live migration. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h

[PATCH v8 12/12] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest

exception (#GP). Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 170cd48..7ace11a 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3996,7 +3996,8 @@ static int

[PATCH v8 04/12] perf/x86/intel/pt: add new capability for Intel PT

and a #GP would be injected to guest if set IA32_RTIT_CTL.FabricEn with CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0. Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 1 + arch/x86/include/asm/intel_pt.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/events/intel/pt.c b/arch

[PATCH v13 00/12] Intel Processor Trace virtualization enabling

Add Intel PT virtualization work mode KVM: x86: Add Intel Processor Trace cpuid emulation KVM: x86: Add Intel PT context switch for each vcpu KVM: x86: Implement Intel PT MSRs read/write emulation KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang (5): perf/x86/intel/pt: Introd

[PATCH v13 02/12] perf/x86/intel/pt: Export pt_cap_get()

Acked-by: Song Liu Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 49 ++--- arch/x86/events/intel/pt.h | 21 -- arch/x86/include/asm/intel_pt.h | 23 +++ 3 files changed, 49 inserti

[PATCH v13 05/12] perf/x86/intel/pt: add new capability for Intel PT

This adds support for "output to Trace Transport subsystem" capability of Intel PT. It means that PT can output its trace to an MMIO address range rather than system memory buffer. Acked-by: Song Liu Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 1 + arch/x86/i

[PATCH v13 04/12] perf/x86/intel/pt: Add new bit definitions for PT MSRs

Add bit definitions for Intel PT MSRs to support trace output directed to the memeory subsystem and holds a count if packet bytes that have been sent out. These are required by the upcoming PT support in KVM guests for MSRs read/write emulation. Signed-off-by: Luwei Kang --- arch/x86/include

[PATCH v13 03/12] perf/x86/intel/pt: Introduce intel_pt_validate_cap()

guest can be different from the host array. Provide a new function to check against a given capability array. Acked-by: Song Liu Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 12 +--- arch/x86/include/asm/intel_pt.h | 2 ++ 2 files changed, 11 insertions(+), 3 deletions

[PATCH v13 01/12] perf/x86/intel/pt: Move Intel PT MSRs bit defines to global header

-by: Luwei Kang --- arch/x86/events/intel/pt.h | 37 - arch/x86/include/asm/msr-index.h | 33 + 2 files changed, 33 insertions(+), 37 deletions(-) diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h index

[PATCH v13 12/12] KVM: x86: Disable Intel PT when VMXON in L1 guest

exception (#GP). Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index ed247dd..5001049 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -4556,7 +4556,8 @@ static int

[PATCH v13 08/12] KVM: x86: Add Intel PT context switch for each vcpu

From: Chao Peng Load/Store Intel Processor Trace register in context switch. MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS. In Host-Guest mode, we need load/resore PT MSRs only when PT is enabled in guest. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include

[PATCH v13 06/12] KVM: x86: Add Intel PT virtualization work mode

: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 3 ++ arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 8 + arch/x86/kvm/vmx.c | 68 +--- 4 files changed, 76 insertions(+), 4 deletions

[PATCH v13 09/12] KVM: x86: Introduce a function to initialize the PT configuration

Initialize the Intel PT configuration when cpuid update. Include cpuid inforamtion, rtit_ctl bit mask and the number of address ranges. Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 73 ++ 1 file changed, 73 insertions(+) diff --git a

[PATCH v13 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write

From: Chao Peng To save performance overhead, disable intercept Intel PT MSRs read/write when Intel PT is enabled in guest. MSR_IA32_RTIT_CTL is an exception that will always be intercepted. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 23

[PATCH v13 10/12] KVM: x86: Implement Intel PT MSRs read/write emulation

From: Chao Peng This patch implement Intel Processor Trace MSRs read/write emulation. Intel PT MSRs read/write need to be emulated when Intel PT MSRs is intercepted in guest and during live migration. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h

[PATCH v13 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation

From: Chao Peng Expose Intel Processor Trace to guest only when the PT works in Host-Guest mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 22 -- arch/x86/kvm/svm.c | 6

[RFC v1 0/9] PEBS enabling in KVM guest

output to Intel PT. The native driver as [1] (still under review). [1] https://www.spinics.net/lists/kernel/msg3215354.html Luwei Kang (9): KVM: x86: Add base address parameter for get_fixed_pmc function KVM: x86: PEBS via Intel PT HW feature detection KVM: x86: Implement

[RFC v1 1/9] KVM: x86: Add base address parameter for get_fixed_pmc function

MSR_RELOAD_FIXED_CTRx registers. Signed-off-by: Luwei Kang --- arch/x86/kvm/pmu.h | 5 ++--- arch/x86/kvm/vmx/pmu_intel.c | 14 +- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 58265f7..c62a1ff 100644 --- a/arch/x86/kvm/pmu.h

[RFC v1 7/9] KVM: X86: Expose PDCM cpuid to guest

PDCM (Perfmon and Debug Capability) indicates the processor supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES. PEBS enabling in KVM guest depend on PEBS via PT, and PEBS via PT is detected by IA32_PERF_CAPABILITIES[Bit16]. Signed-off-by: Luwei Kang --- arch/x86

[RFC v1 6/9] KVM: x86: Add shadow value of PEBS status

real hardware. Update the shadow value of PEBS before VM-entry when PT is enabled in guest. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/pmu.c | 34 ++ arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/vmx/vmx.c

[RFC v1 2/9] KVM: x86: PEBS via Intel PT HW feature detection

: 1. PEBS feature is supported by HW (IA32_MISC_ENABLE[Bit12]=0); 2. Intel PT must be working in HOST_GUEST mode. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kvm/vmx/capabilities.h | 11 +++ arch/x86/kvm/vmx

[RFC v1 3/9] KVM: x86: Implement MSR_IA32_PEBS_ENABLE read/write emulation

destroyed. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kvm/vmx/pmu_intel.c | 42 +--- 3 files changed, 44 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b

[RFC v1 4/9] KVM: x86: Implement counter reload MSRs read/write emulation

changed. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kvm/vmx/pmu_intel.c | 22 +- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include

[RFC v1 9/9] KVM: x86: Expose PEBS feature to guest

Expose PEBS feature to guest by IA32_MISC_ENABLE[bit12]. IA32_MISC_ENABLE[bit12] is Processor Event Based Sampling (PEBS) Unavailable (RO) flag: 1 = PEBS is not supported; 0 = PEBS is supported. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/svm.c

[RFC v1 5/9] KVM: x86: Allocate performance counter for PEBS event

This patch add a new parameter "pebs" that to make the host PMU framework allocate performance counter for guest PEBS event. Signed-off-by: Luwei Kang --- arch/x86/kvm/pmu.c | 23 +++ arch/x86/kvm/pmu.h | 5 +++-- arch/x86/kvm/pmu_amd.c

[RFC v1 8/9] KVM: X86: MSR_IA32_PERF_CAPABILITIES MSR emulation

Expose some bits of definition which relate with enable PEBS to KVM guest especially PEBS via PT feature. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ arch/x86/kvm/vmx/vmx.c | 14 ++ 3 files changed, 18

[PATCH V4] KVM: x86: Sync the pending Posted-Interrupts

posted interrupt coming at this time, the irq remmaping facility will set the bit of PIR (Posted Interrupt Requests) without ON (Outstanding Notification). So this interrupt can't be sync to APIC virtualization register and will not be handled by Guest because ON is zero. Signed-off-by: Luwei

[PATCH 0/3] Inject a PMI for KVM Guest when ToPA buffer is filled

buffer is filled. Luwei Kang (3): perf/x86/intel/pt: Move pt structure to global header perf/x86/intel/pt: Inject PMI for KVM guest KVM: x86: Add support of clear Trace_ToPA_PMI status arch/x86/events/intel/pt.c | 12 +++- arch/x86/events/intel/pt.h | 38

[PATCH 1/3] perf/x86/intel/pt: Move pt structure to global header

Intel PT structure (struct pt) is in a private header. Move it (and sub structure) to a global header so that it can be accessible from KVM code. The definition of perf_output_handle structure included in "linux/perf_event.h". Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.h

[PATCH 3/3] KVM: x86: Add support of clear Trace_ToPA_PMI status

Add support of clear Intel PT ToPA PMI status for KVM guest. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 4 arch/x86/kvm/vmx/pmu_intel.c | 8 +++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86

[PATCH 2/3] perf/x86/intel/pt: Inject PMI for KVM guest

Inject a PMI for KVM guest when Intel PT working in Host-Guest mode and Guest ToPA entry memory buffer was completely filled. The definition of ‘kvm_make_request’ and ‘KVM_REQ_PMI’ depend on "linux/kvm_host.h" header. Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c

[PATCH v2] KVM: x86: Sync the pending Posted-Interrupts

posted interrupt coming at this time, the irq remmaping facility will set the bit of PIR (Posted Interrupt Requests) without ON (Outstanding Notification). So this interrupt can't be sync to APIC virtualization register and will not be handled by Guest because ON is zero. Signed-off-by: Luwei

[PATCH] KVM: x86: Sync the pending Posted-Interrupts

posted interrupt coming at this time, the irq remmaping facility will set the bit of PIR (Posted Interrupt Requests) but ON (Outstanding Notification). So this interrupt can't be sync to APIC virtualization register and will not be handled by Guest because ON is zero. Signed-off-by: Luwei

[PATCH] KVM: LAPIC: Do not mask the local interrupts when LAPIC is sw disabled

d when LAPIC is "software disabled" and this local interrupt still disabled after LAPIC "software enabled". This patch will not mask the local interrupts when LAPIC is "software disabled" and add LAPIC "software enabled" checking before deliver local interrupt

[PATCH v2 1/2] KVM: x86: Inject PMI for KVM guest

Inject a PMI for KVM guest when Intel PT working in Host-Guest mode and Guest ToPA entry memory buffer was completely filled. Signed-off-by: Luwei Kang --- arch/x86/events/intel/core.c | 6 +- arch/x86/include/asm/msr-index.h | 4 arch/x86/kvm/x86.c | 10

[PATCH v2 0/2] Inject a PMI for KVM Guest when ToPA buffer is filled

buffer is filled. >From v1: - Exported a global function pointers may not a good chioce. Add a new member in kvm_guest_cbs to send Intel PT PMI for KVM guest. Luwei Kang (2): KVM: x86: Inject PMI for KVM guest KVM: x86: Add support of clear Trace_ToPA_PMI status arch/x86/events/intel/cor

[PATCH v2 2/2] KVM: x86: Add support of clear Trace_ToPA_PMI status

Add support of clear Intel PT ToPA PMI status for KVM guest. Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 4 arch/x86/kvm/vmx/pmu_intel.c | 8 +++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86

[PATCH v9 00/12] Intel Processor Trace virtualization enabling

x86: Implement Intel Processor Trace MSRs read/write emulation KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang (5): perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs perf/x86/intel/pt: add new capability for Intel PT perf/x86/intel/pt: Introduce a new func

[PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header

From: Chao Peng Intel Processor Trace virtualization enabling in KVM guest need to access these MSRs bit definitions, so move them to public header file msr-index.h. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.h | 37

[PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs

-by: Luwei Kang --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index afe4e13..6ae2462 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -112,6 +112,7

[PATCH v9 05/12] perf/x86/intel/pt: Introduce a new function to get capability of Intel PT

New function pt_cap_decode() will be invoked in KVM to check if a specific capability is available in KVM guest. Another function pt_cap_get() can only check the hardware capabilities but this may different with KVM guest because some features may not be exposed to guest. Signed-off-by: Luwei

[PATCH v9 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation

From: Chao Peng Expose Intel Processor Trace to guest only when PT work in HOST_GUEST mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 22 -- arch/x86/kvm/svm.c | 6

[PATCH v9 08/12] KVM: x86: Add Intel Processor Trace context switch for each vcpu

From: Chao Peng Load/Store Intel processor trace register in context switch. MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS. In HOST_GUEST mode, we need load/resore PT MSRs only when PT is enabled in guest. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include

[PATCH v9 09/12] KVM: x86: Introduce a function to initialize the PT configuration

Initialize the Intel PT configuration when cpuid update. Include cpuid inforamtion, rtit_ctl bit mask and the number of address ranges. Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 70 ++ 1 file changed, 70 insertions(+) diff --git a

[PATCH v9 12/12] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest

exception (#GP). Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index a09157c..093c1f7 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3997,7 +3997,8 @@ static int

[PATCH v9 06/12] KVM: x86: Add Intel Processor Trace virtualization mode

From: Chao Peng Intel PT virtualization can be work in one of 2 possible modes: a. system-wide: trace both host and guest and output to host buffer; b. host-guest: trace host/guest simultaneous and output to their respective buffer. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang

[PATCH v9 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write

From: Chao Peng Disable intercept Intel PT MSRs only when Intel PT is enabled in guest. But MSR_IA32_RTIT_CTL will alway be intercept. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/arch

[PATCH v9 10/12] KVM: x86: Implement Intel Processor Trace MSRs read/write emulation

From: Chao Peng This patch implement Intel Processor Trace MSRs read/write emulation. Intel PT MSRs read/write need to be emulated when Intel PT MSRs is intercepted in guest and during live migration. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h

[PATCH v9 04/12] perf/x86/intel/pt: add new capability for Intel PT

and a #GP would be injected to guest if set IA32_RTIT_CTL.FabricEn with CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0. Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 1 + arch/x86/include/asm/intel_pt.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/events/intel/pt.c b/arch

[PATCH v9 02/12] perf/x86/intel/pt: Change pt_cap_get() to a public function

From: Chao Peng Change pt_cap_get() to a public function that KVM can access this function to check if specific feature is supported on hardware. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 3 ++- arch/x86/events/intel/pt.h | 21

[PATCH v5 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header

From: Chao Peng Intel Processor Trace virtualization enabling in guest need to use these MSR bits, so move them to public header msr-index.h. Introduce RTIT_CTL_FABRIC_EN and sync the definitions to latest spec. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel

[PATCH v5 00/11] Intel Processor Trace virtulization enabling

Implement Intel Processor Trace context switch KVM: x86: Implement Intel Processor Trace MSRs read/write KVM: x86: Set intercept for Intel PT MSRs Luwei Kang (3): perf/x86/intel/pt: Introduce a new function to get the capability of Intel PT KVM: x86: Introduce a function to initi

[PATCH v5 03/11] perf/x86/intel/pt: Introduce a new function to get the capability of Intel PT

Because of the guest CPUID information may diffrent with with host(some bits may mask off in guest) so introduce a new function pt_cap_get_ex() to get the capability of Intel PT. Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 10 ++ arch/x86/include/asm/intel_pt.h | 2

[PATCH v5 06/11] KVM: x86: Add Intel processor trace context for each vcpu

From: Chao Peng Add a data structure to save Intel Processor Trace context. It mainly include the value of Intel PT host/guest MSRs and guest CPUID information. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 19 +++ 1 file changed, 19 insertions

[PATCH v5 11/11] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest

exception (#GP). Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 0a55772..a1ec71d 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -3710,7 +3710,8 @@ static int

[PATCH v5 05/11] KVM: x86: Add Intel Processor Trace cpuid emulation

From: Chao Peng Expose Intel Processor Trace to guest only when PT work in HOST_GUEST mode. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c| 22 -- arch/x86/kvm/svm.c | 6

[PATCH v5 09/11] KVM: x86: Implement Intel Processor Trace MSRs read/write

From: Chao Peng Implement Intel Processor Trace MSRs read/write. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 8 ++ arch/x86/kvm/vmx.c | 167 arch/x86/kvm/x86.c | 33 +++- 3

[PATCH v5 10/11] KVM: x86: Set intercept for Intel PT MSRs

From: Chao Peng Disable interrcept Intel PT MSRs only when Intel PT is enabled in guest. But MSR_IA32_RTIT_CTL will alway be intercept. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/kvm/vmx.c | 20 1 file changed, 20 insertions(+) diff --git a/arch/x86

[PATCH v5 04/11] KVM: x86: Add Intel Processor Trace virtualization mode

-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/include/asm/intel_pt.h | 6 arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 8 + arch/x86/kvm/vmx.c | 68 +--- 4 files changed, 79 insertions(+), 4

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