On Fri, Nov 20, 2020 at 07:16:11PM +0800, Jisheng Zhang wrote:
> Some designware based device driver especially host only driver may
> work well with the default read_dbi/write_dbi/link_up implementation
> in pcie-designware.c, thus remove the assumption to simplify those
> drivers.
>
> Since v1:
On Wed, 20 Jan 2021 06:37:45 -0800, Pan Bian wrote:
> Also drop the reference count of the node on error path.
Applied to pci/xilinx, thanks!
[1/1] PCI: xilinx-cpm: Fix reference count leak on error path
https://git.kernel.org/lpieralisi/pci/c/ae191d2e51
Thanks,
Lorenzo
| 14 ++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
Acked-by: Lorenzo Pieralisi
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index d4eac6d7e9fb..2494138a6905 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@
On Thu, 28 Jan 2021 14:42:13 +0800, Jisheng Zhang wrote:
> Some designware based device driver especially host only driver may
> work well with the default read_dbi/write_dbi/link_up implementation
> in pcie-designware.c, thus remove the assumption to simplify those
> drivers.
>
> Since v2:
> -
On Fri, Jan 22, 2021 at 07:48:52PM +0530, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On 20/01/21 12:04 am, Bjorn Helgaas wrote:
> > On Mon, Jan 04, 2021 at 08:58:53PM +0530, Kishon Vijay Abraham I wrote:
> >> Add specification for the *PCI NTB* function device. The endpoint function
> >> driver
On Thu, Nov 26, 2020 at 03:54:00PM +, David Brazdil wrote:
> Function IDs used by PSCI are configurable for v0.1 via DT/APCI. If the
Side note: in ACPI we don't support versions < 0.2, for commit log
accuracy.
Other than that I agree with Mark's change request.
Thanks,
Lorenzo
> host is usi
On Thu, Nov 26, 2020 at 03:54:14PM +, David Brazdil wrote:
> Forward the following PSCI SMCs issued by host to EL3 as they do not
> require the hypervisor's intervention. This assumes that EL3 correctly
> implements the PSCI specification.
>
> Only function IDs implemented in Linux are include
On Fri, 23 Oct 2020 17:20:08 +0100, Lad Prabhakar wrote:
> Drop unused members dev and base from struct rcar_pcie_host.
Applied to pci/rcar, thanks!
[1/1] PCI: rcar: Drop unused members from struct rcar_pcie_host
https://git.kernel.org/lpieralisi/pci/c/6e8e137abe
Thanks,
Lorenzo
On Mon, 2 Nov 2020 15:57:12 -0500, Jim Quinlan wrote:
> The variable 'tmp' is used multiple times in the brcm_pcie_setup()
> function. One such usage did not initialize 'tmp' to the current value of
> the target register. By luck the mistake does not currently affect
> behavior; regardless 'tmp'
On Fri, 6 Nov 2020 20:41:05 +0530, Kishon Vijay Abraham I wrote:
> Make "cdns,max-outbound-regions" optional DT property in all the
> platforms using Cadence PCIe core.
>
> Kishon Vijay Abraham I (2):
> dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
> PCI: cadence: Do not
On Fri, 13 Nov 2020 18:01:34 +0100, Marek Szyprowski wrote:
> This patchset is a resurrection of the DW PCIe support for the Exynos5433
> SoCs posted long time ago here: https://lkml.org/lkml/2016/12/26/6 and
> later here: https://lkml.org/lkml/2017/12/21/296 .
>
> In meantime the support for the
On Sat, Feb 22, 2014 at 10:38:40AM +, Russell King - ARM Linux wrote:
> On Wed, Feb 19, 2014 at 04:12:54PM +0000, Lorenzo Pieralisi wrote:
> > On Wed, Feb 19, 2014 at 01:52:09AM +, Sebastian Capella wrote:
> > > +/*
> > > + * Snapshot kernel memory and reset
On Sat, Feb 22, 2014 at 10:16:55AM +, Russell King - ARM Linux wrote:
> On Thu, Feb 20, 2014 at 04:27:55PM +0000, Lorenzo Pieralisi wrote:
> > I still do not understand why switching to idmap, which is a clone of
> > init_mm + 1:1 kernel mappings is required here. Why idmap
Hi Stephen,
On Wed, Feb 19, 2014 at 12:20:43AM +, Stephen Boyd wrote:
> (Sorry, this discussion stalled due to merge window + life events)
Sorry for the delay in replying on my side too.
> On 01/17, Lorenzo Pieralisi wrote:
> > On Thu, Jan 16, 2014 at 07:26:17PM +, Stephe
On Sun, Feb 23, 2014 at 08:02:08PM +, Sebastian Capella wrote:
> Quoting Lorenzo Pieralisi (2014-02-22 04:09:10)
> > On Sat, Feb 22, 2014 at 10:38:40AM +, Russell King - ARM Linux wrote:
> > > On Wed, Feb 19, 2014 at 04:12:54PM +, Lorenzo Pieralisi wrote:
> >
On Tue, Feb 25, 2014 at 05:55:31PM +, Sebastian Capella wrote:
> Quoting Lorenzo Pieralisi (2014-02-25 03:32:51)
> > On Sun, Feb 23, 2014 at 08:02:08PM +, Sebastian Capella wrote:
> > > I'll go with leaving the soft_restart as is unless someone feels
On Tue, Feb 25, 2014 at 08:48:38PM +, Kumar Gala wrote:
>
> On Feb 25, 2014, at 5:16 AM, Lorenzo Pieralisi
> wrote:
>
> > Hi Stephen,
> >
> > On Wed, Feb 19, 2014 at 12:20:43AM +, Stephen Boyd wrote:
> >> (Sorry, this discussion st
On Wed, Feb 26, 2014 at 05:50:55PM +, Sebastian Capella wrote:
> Quoting Lorenzo Pieralisi (2014-02-26 02:24:27)
> > On Tue, Feb 25, 2014 at 05:55:31PM +, Sebastian Capella wrote:
> >
> > Please add:
> >
> > "swsusp_save() is executed in the su
On Tue, Mar 04, 2014 at 09:55:31AM +, Sebastian Capella wrote:
> Quoting Sebastian Capella (2014-02-28 15:38:54)
> > Quoting Lorenzo Pieralisi (2014-02-28 14:49:33)
> > > On Fri, Feb 28, 2014 at 08:15:57PM +, Sebastian Capella wrote:
> > > > >
> > &
[CC'in BenH and Grant to check how this is handled in powerPC]
On Thu, Mar 06, 2014 at 10:00:10AM +, Ben Dooks wrote:
> On 05/03/14 20:33, Stephen Boyd wrote:
> > +Lorenzo
> >
> > On 02/24/14 03:22, Jürg Billeter wrote:
> >> Skip 'disabled' cpu nodes when building the cpu logical map. This avo
On Thu, Feb 27, 2014 at 11:57:58PM +, Sebastian Capella wrote:
[...]
> diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
> new file mode 100644
> index 000..a41e0e3
> --- /dev/null
> +++ b/arch/arm/kernel/hibernate.c
> @@ -0,0 +1,113 @@
> +/*
> + * Hibernation support
On Fri, Feb 28, 2014 at 08:15:57PM +, Sebastian Capella wrote:
[...]
> > > +
> > > +/*
> > > + * The framework loads the hibernation image into a linked list anchored
> > > + * at restore_pblist, for swsusp_arch_resume() to copy back to the proper
> > > + * destinations.
> > > + *
> > > + * T
On Mon, Feb 03, 2014 at 04:17:47PM +, Arjan van de Ven wrote:
[...]
> >> 1) A latency driven one
> >> 2) A performance impact on
> >>
> >> first one is pretty much the exit latency related time, sort of a
> >> "expected time to first instruction" (currently menuidle has the
> >> 99.999% worst
On Wed, Feb 12, 2014 at 04:14:38PM +, Arjan van de Ven wrote:
>
> >> sched_cpu_cache_wiped(int llc)
> >>
> >> that would be very nice for this; the menuidle side knows this
> >> for some cases and thus can just call it. This would be a very
> >> small and minimal change
> >
> > What do you mea
On Wed, Feb 19, 2014 at 01:52:09AM +, Sebastian Capella wrote:
[...]
> diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
> new file mode 100644
> index 000..16f406f
> --- /dev/null
> +++ b/arch/arm/kernel/hibernate.c
> @@ -0,0 +1,106 @@
> +/*
> + * Hibernation support
On Wed, Feb 19, 2014 at 07:10:31PM +, Russ Dill wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 02/19/2014 08:12 AM, Lorenzo Pieralisi wrote:
>
> + * https://patchwork.kernel.org/patch/96442/
>
I am guessing the snippets of code your comments refer to
Hi Sebastian,
On Wed, Feb 19, 2014 at 07:33:15PM +, Sebastian Capella wrote:
> Quoting Lorenzo Pieralisi (2014-02-19 08:12:54)
> > On Wed, Feb 19, 2014 at 01:52:09AM +, Sebastian Capella wrote:
> > [...]
> > > diff --git a/arch/arm/kernel/hibernate.c b/arc
On Mon, Jan 20, 2014 at 05:32:53PM +, Tomasz Figa wrote:
> Hi Lorenzo,
>
> On 16.01.2014 17:34, Lorenzo Pieralisi wrote:
> > Hi Tomasz,
> >
> > thank you for posting this series. I would like to use the DT bindings
> > for power domains in the bindings
On Fri, Jan 17, 2014 at 12:24:58PM +, Hanjun Guo wrote:
[...]
> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> index bd9bbd0..2210353 100644
> --- a/arch/arm64/kernel/setup.c
> +++ b/arch/arm64/kernel/setup.c
> @@ -41,6 +41,7 @@
> #include
> #include
> #include
> +
On Fri, Jan 17, 2014 at 12:25:04PM +, Hanjun Guo wrote:
[...]
> +/* map logic cpu id to physical GIC id */
> +extern int arm_cpu_to_apicid[NR_CPUS];
> +#define cpu_physical_id(cpu) arm_cpu_to_apicid[cpu]
Sudeep already commented on this, please update it accordingly.
> +
> #else/*
Hi Hanjun,
On Fri, Jan 24, 2014 at 09:09:40AM +, Hanjun Guo wrote:
> On 2014?01?23? 23:56, Tomasz Nowicki wrote:
> > Hi Lorenzo,
> >
> > W dniu 22.01.2014 12:54, Lorenzo Pieralisi pisze:
> >> On Fri, Jan 17, 2014 at 12:24:58PM +, Hanjun Guo wrote:
> >
On Fri, Jan 24, 2014 at 02:37:28PM +, Hanjun Guo wrote:
> Hi Lorenzo,
>
> On 2014?01?22? 23:53, Lorenzo Pieralisi wrote:
> > On Fri, Jan 17, 2014 at 12:25:04PM +, Hanjun Guo wrote:
> >
> > [...]
> >
> >> +/* map logic cpu id to physical GIC id */
On Mon, Dec 30, 2013 at 08:14:15PM +, Stephen Boyd wrote:
> The Krait L1/L2 error reporting device is made up of two
> interrupts, one per-CPU interrupt for the L1 caches and one
> interrupt for the L2 cache.
>
> Cc: Lorenzo Pieralisi
> Cc: Mark Rutland
> Cc: Kumar Gala
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
> On 01/07, Lorenzo Pieralisi wrote:
> >
> > Not sure this binding (cache node) belongs in cpus.txt
> >
> > I am working on defining cache bindings for ARM within the C-state
> > stan
On Thu, Jan 09, 2014 at 08:52:21PM +, Stephen Boyd wrote:
> On 01/08/14 02:05, Lorenzo Pieralisi wrote:
> > On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
> >> On 01/07, Lorenzo Pieralisi wrote:
> >>
> >>> I have a problem with the cache le
On Tue, Jan 14, 2014 at 09:30:32PM +, Stephen Boyd wrote:
> The Krait CPU/L1 error reporting device is made up a per-CPU
> interrupt. While we're here, document the next-level-cache
> property that's used by the Krait EDAC driver.
>
> Cc: Lorenzo Pieralisi
> C
[added Nico in CC]
On Wed, Apr 23, 2014 at 10:25:54AM +0100, Chander Kashyap wrote:
> In order to support cpuidle through mcpm, suspend and powered-up
> callbacks are required in mcpm platform code.
> Hence populate the same callbacks.
>
> Signed-off-by: Chander Kashyap
> Signed-off-by: Chander
On Wed, Apr 23, 2014 at 10:25:52AM +0100, Chander Kashyap wrote:
> Add "samsung,exynos5420" compatible string to initialize generic
> big-little cpuidle driver for Exynos5420.
>
> Signed-off-by: Chander Kashyap
> Signed-off-by: Chander Kashyap
> Acked-by: Daniel Lezcano
> ---
> drivers/cpuidle
we're here, document the next-level-cache
> property that's used by the Krait EDAC driver.
>
> Cc: Lorenzo Pieralisi
> Cc: Mark Rutland
> Cc: Kumar Gala
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 58
&g
Hi Tomasz,
thank you for posting this series. I would like to use the DT bindings
for power domains in the bindings for C-states on ARM:
http://comments.gmane.org/gmane.linux.power-management.general/41012
and in particular link a given C-state to a given power domain so that the
kernel will hav
On Thu, Jan 16, 2014 at 06:05:05PM +, Stephen Boyd wrote:
> On 01/16, Lorenzo Pieralisi wrote:
> > On Thu, Jan 16, 2014 at 01:38:40AM +, Stephen Boyd wrote:
> > > On 01/15, Stephen Boyd wrote:
> > > >
> > > > Ah sorry, I forgot to put the compat
On Thu, Jan 16, 2014 at 07:26:17PM +, Stephen Boyd wrote:
> On 01/16, Lorenzo Pieralisi wrote:
> > On Thu, Jan 16, 2014 at 06:05:05PM +, Stephen Boyd wrote:
> > > On 01/16, Lorenzo Pieralisi wrote:
> > > > Do we really want to do that ? I am not sure. A cpus
[CC'ed Daniel to make him aware this patch goes through your tree]
On Thu, Sep 25, 2014 at 06:56:33AM +0100, Kukjin Kim wrote:
> Bartlomiej Zolnierkiewicz wrote:
> >
> > Recent patch by Tomasz Figa ("irqchip: gic: Fix core ID calculation
> > when topology is read from DT") fixed GIC driver to fil
On Thu, Sep 25, 2014 at 10:02:05AM +0100, Daniel Lezcano wrote:
> On 09/25/2014 10:17 AM, Lorenzo Pieralisi wrote:
> > [CC'ed Daniel to make him aware this patch goes through your tree]
>
> Thanks for the head up. I was about to send the PR to Rafael.
>
> [ ... ]
&
On Mon, Sep 01, 2014 at 03:57:54PM +0100, Hanjun Guo wrote:
> From: Graeme Gregory
>
> Add Kconfigs to build ACPI on ARM64, and make ACPI available on ARM64.
>
> acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR
> depend on X86 || IA64, and implement it on ARM64 in the fu
On Mon, Sep 29, 2014 at 03:36:30PM +0100, Arnd Bergmann wrote:
> On Sunday 28 September 2014 15:53:28 suravee.suthikulpa...@amd.com wrote:
> > +
> > +#ifdef CONFIG_ARM64
> > +struct pci_bus *gen_scan_root_bus(struct device *parent, int bus,
> > + struct pci_ops
On Tue, Sep 30, 2014 at 01:31:44PM +0100, Arnd Bergmann wrote:
> On Tuesday 30 September 2014 13:03:44 Lorenzo Pieralisi wrote:
> > > > static int gen_pci_probe(struct platform_device *pdev)
> > > > {
> > > > @@ -326,6 +385,7 @@ static int gen_pci_prob
On Tue, Sep 30, 2014 at 05:42:56PM +0100, Liviu Dudau wrote:
> On Tue, Sep 30, 2014 at 05:12:41PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Sep 30, 2014 at 01:31:44PM +0100, Arnd Bergmann wrote:
> > > On Tuesday 30 September 2014 13:03:44 Lorenzo Pieralisi wrote:
>
On Fri, Mar 07, 2014 at 11:08:56PM +, Stephen Boyd wrote:
> On 02/26, Lorenzo Pieralisi wrote:
> > On Tue, Feb 25, 2014 at 08:48:38PM +, Kumar Gala wrote:
> > >
> > > On Feb 25, 2014, at 5:16 AM, Lorenzo Pieralisi
> > > wrote:
> > > >
&
On Fri, Apr 25, 2014 at 04:18:42AM +0100, Zi Shen Lim wrote:
> Create cpu topology based on MPIDR. When hardware sets MPIDR to sane
> values, this method will always work. Therefore it should also work well
> as the fallback method. [1]
It has to be implemented as fallback, so you have to rebase t
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> > The Krait L1/L2 error reporting hardware is made up a per-CPU
> > interrupt for the L1 cache and a SPI interrupt for the L2.
> >
> > Cc
On Tue, May 13, 2014 at 12:43:31PM +0100, Chander Kashyap wrote:
[...]
> >> +static void exynos_suspend(u64 residency)
> >> +{
> >> + unsigned int mpidr, cpunr;
> >> +
> >> + mpidr = read_cpuid_mpidr();
> >> + cpunr = exynos_pmu_cpunr(mpidr);
> >
> > If I were to be picky, I would com
On Wed, May 14, 2014 at 02:04:51PM +0100, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 13:33:55 Chander Kashyap wrote:
> >
> > diff --git a/drivers/cpuidle/cpuidle-big_little.c
> > b/drivers/cpuidle/cpuidle-big_little.c
> > index 4cd02bd..344d79fa 100644
> > --- a/drivers/cpuidle/cpuidle-big_l
ions and fails to build when targetting
> other ARM instruction set versions.
>
> This works around both issues by limiting the scope of the
> Kconfig symbol to platforms that can actually build this driver
> cleanly.
>
> Signed-off-by: Arnd Bergmann
> Cc: Shawn Guo
>
On Mon, May 05, 2014 at 10:27:20AM +0100, Chander Kashyap wrote:
> In order to support cpuidle through mcpm, suspend and powered-up
> callbacks are required in mcpm platform code.
> Hence populate the same callbacks.
>
> Signed-off-by: Chander Kashyap
> Signed-off-by: Chander Kashyap
> ---
> Cha
On Fri, Jun 06, 2014 at 10:43:05PM +0100, Doug Anderson wrote:
> On exynos mcpm systems the firmware is hardcoded to jump to an address
> in SRAM (0x02073000) when secondary CPUs come up. By default the
> firmware puts a bunch of code at that location. That code expects the
> kernel to fill in a
On Mon, Jun 09, 2014 at 06:03:31PM +0100, Doug Anderson wrote:
[...]
> Cold boot and resume from suspend are detected via various special
> flags in various special locations. Resume from suspend looks at
> INFORM1 (0x10048004) for flags. This register is 0 during a cold boot
> and has special
On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
> Hi Doug,
>
> On Tue, Jun 10, 2014 at 9:19 PM, Nicolas Pitre
> wrote:
> > On Tue, 10 Jun 2014, Doug Anderson wrote:
> >
> >> My S-state knowledge is not strong, but I believe that Lorenzo's
> >> questions matter if we're using S2
On Wed, Jun 11, 2014 at 01:14:21PM +0100, Chander Kashyap wrote:
> On Wed, Jun 11, 2014 at 3:43 PM, Lorenzo Pieralisi
> wrote:
> > On Wed, Jun 11, 2014 at 05:52:10AM +0100, Chander Kashyap wrote:
> >> Hi Doug,
> >>
> >> On Tue, Jun 10, 2014 at 9:19 PM, Ni
On Tue, May 20, 2014 at 06:43:46PM +0100, Alex Elder wrote:
> Broadcom mobile SoCs use a ROM-implemented holding pen for
> controlled boot of secondary cores. A special register is
> used to communicate to the ROM that a secondary core should
> start executing kernel code. This enable method is c
On Wed, May 28, 2014 at 04:30:47AM +0100, Alex Elder wrote:
> On 05/27/2014 06:49 AM, Lorenzo Pieralisi wrote:
> > On Tue, May 20, 2014 at 06:43:46PM +0100, Alex Elder wrote:
> >> Broadcom mobile SoCs use a ROM-implemented holding pen for
> >> controlled boot of
On Wed, May 28, 2014 at 01:22:06PM +0100, Alex Elder wrote:
> On 05/28/2014 05:36 AM, Lorenzo Pieralisi wrote:
> > On Wed, May 28, 2014 at 04:30:47AM +0100, Alex Elder wrote:
> >> On 05/27/2014 06:49 AM, Lorenzo Pieralisi wrote:
> >>> On Tue, May 20, 2014 at 06:4
instead
of the software based one, now present by default.
Cc: Preeti U Murthy
Cc: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Lorenzo Pieralisi
---
arch/arm64/kernel/time.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index
Hi Preeti,
On Thu, May 29, 2014 at 12:04:36PM +0100, Preeti U Murthy wrote:
> Hi Lorenzo,
>
> On 05/29/2014 02:53 PM, Lorenzo Pieralisi wrote:
> > On platforms implementing CPU power management, the CPUidle subsystem
> > can allow CPUs to enter idle states where local ti
leaves the kernel with a functional system with some working power
management capabilities.
The hrtimer based clock event device has lowest possible rating so that,
if a platform contains a functional HW clock event device with broadcast
capabilities, that device is always chosen as a tick broadcast
any broadcast-capable HW clock
event device present will be chosen in preference as the tick broadcast
device.
Cc: Preeti U Murthy
Acked-by: Will Deacon
Acked-by: Mark Rutland
Signed-off-by: Lorenzo Pieralisi
---
changes in v2:
- Reworded the commit log according to reviews
It should be
On Thu, Jan 30, 2014 at 05:25:27PM +, Daniel Lezcano wrote:
> On 01/30/2014 05:35 PM, Peter Zijlstra wrote:
> > On Thu, Jan 30, 2014 at 05:27:54PM +0100, Daniel Lezcano wrote:
> >> struct cpuidle_state *state = &drv->states[rq->index];
> >>
> >> And from the state, we have the following informa
On Thu, Jan 30, 2014 at 09:02:15PM +, Nicolas Pitre wrote:
> On Thu, 30 Jan 2014, Lorenzo Pieralisi wrote:
>
> > On Thu, Jan 30, 2014 at 05:25:27PM +, Daniel Lezcano wrote:
> > > On 01/30/2014 05:35 PM, Peter Zijlstra wrote:
> > > > On Thu, Jan 30, 2014 at
On Sat, Feb 01, 2014 at 06:00:40AM +, Brown, Len wrote:
> > Right now (on ARM at least but I imagine this is pretty universal), the
> > biggest impact on information accuracy for a CPU depends on what the
> > other CPUs are doing. The most obvious example is cluster power down.
> > For a clust
On Mon, Sep 08, 2014 at 02:54:30PM +0100, Liviu Dudau wrote:
> Provide a function to parse the PCI DT ranges that can be used to
> create a pci_host_bridge structure together with its associated
> bus.
>
> Cc: Bjorn Helgaas
> Cc: Arnd Bergmann
> Cc: Grant Likely
> Cc: Rob Herring
> Cc: Catalin
On Thu, Sep 04, 2014 at 04:29:15PM +0100, Hanjun Guo wrote:
> Hi Lorenzo,
>
> On 2014?09?04? 01:21, Lorenzo Pieralisi wrote:
> > On Mon, Sep 01, 2014 at 03:57:47PM +0100, Hanjun Guo wrote:
> >> MADT contains the information for MPIDR which is essential for
> >>
On Tue, Sep 09, 2014 at 06:15:41PM +0100, Mark Rutland wrote:
> On Tue, Sep 09, 2014 at 05:41:51PM +0100, Jon Masters wrote:
> > On 09/09/2014 12:26 PM, Catalin Marinas wrote:
> > > On Mon, Sep 01, 2014 at 03:57:40PM +0100, Hanjun Guo wrote:
> > >> diff --git a/arch/arm64/include/asm/acenv.h
> > >
On Wed, Sep 10, 2014 at 03:22:41PM +0100, Liviu Dudau wrote:
> On Tue, Sep 09, 2014 at 02:35:46PM +0100, Lorenzo Pieralisi wrote:
> > On Mon, Sep 08, 2014 at 02:54:30PM +0100, Liviu Dudau wrote:
> > > Provide a function to parse the PCI DT ranges that can be used to
> > &g
On Wed, Sep 10, 2014 at 04:32:33PM +0100, Liviu Dudau wrote:
[...]
> > > > > + /*
> > > > > + * If we failed translation or got a zero-sized region
> > > > > + * then skip this range
> > > > > + */
> > > > > + if (range.cpu_addr == OF
On Wed, Sep 10, 2014 at 05:53:47PM +0100, Liviu Dudau wrote:
[...]
> > > > > > > + if (resource_type(res) == IORESOURCE_IO) {
> > > > > > > + if (*io_base)
> > > > > >
> > > > > > You do not zero io_base in the first place so you should ask the API
> > > > > > user to do
Hi Hanjun,
On Mon, Sep 01, 2014 at 03:57:48PM +0100, Hanjun Guo wrote:
> Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained
> from the GICC Structure introduced by ACPI 5.1.
>
> MPIDR is the CPU hardware ID as local APIC ID on x86 platform, so we use
> MPIDR not the GIC CPU
On Mon, Sep 01, 2014 at 03:57:47PM +0100, Hanjun Guo wrote:
> MADT contains the information for MPIDR which is essential for
> SMP initialization, parse the GIC cpu interface structures to
> get the MPIDR value and map it to cpu_logical_map(), and add
> enabled cpu with valid MPIDR into cpu_possibl
Hi Will,
sorry for the delay in replying (I was not copied in).
On Tue, Aug 19, 2014 at 01:05:54PM +0100, Will Deacon wrote:
> Hi guys,
>
> On Tue, Aug 12, 2014 at 05:41:35PM +0100, Liviu Dudau wrote:
> > From: Lorenzo Pieralisi
> >
> > In order to consolidate DT
Hi Arnd,
thanks for having a look.
On Thu, Sep 04, 2014 at 03:05:53PM +0100, Arnd Bergmann wrote:
> On Thursday 04 September 2014 14:39:56 Lorenzo Pieralisi wrote:
> > > > + if (!res_valid) {
> > > > + dev_err(dev, "non-prefetc
On Thu, Sep 04, 2014 at 06:01:27PM +0100, Sonny Rao wrote:
[...]
> > If an OS is booted at PL2 it can access the physical counters, and
> > should do so in case something like KVM will be used later. The OS can
> > write to CNTVOFF at PL2, and if it sets CNTVOFF to zero the physical and
> > virtu
On Fri, Aug 08, 2014 at 02:21:05PM +0100, Russell King - ARM Linux wrote:
> On Fri, Aug 08, 2014 at 01:42:37PM +0100, Juri Lelli wrote:
> > Commit af040ffc9ba1 ("ARM: make it easier to check the CPU part number
> > correctly") changed ARM_CPU_PART_X masks, and the way they are returned and
> > chec
> ARM_CPU_PART_X masks, and the way they are returned and checked against.
> Usage of read_cpuid_part_number() is now deprecated, and calling places
> updated accordingly. This actually broke cpuidle-big_little initialization,
> as bl_idle_driver_init() performs a check using and hardcoded ma
proper mask (ARM_CPU_PART_MASK) that makes this kind of checks
> cleaner and helps preventing bugs in the future. Update usage accordingly.
If Russell does not have any additional comments you can send it to his
patch system.
Thanks,
Lorenzo
> Signed-off-by: Juri Lelli
> Signed-off-b
On Fri, Oct 17, 2014 at 10:43:59AM +0100, Chander Kashyap wrote:
> Hi Lorenzo,
>
> On Wed, Oct 15, 2014 at 2:30 PM, Lorenzo Pieralisi
> wrote:
> > On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
> >> Exynos7 has core power down state whe
On Wed, Oct 01, 2014 at 10:38:45AM +0100, Arnd Bergmann wrote:
[...]
> The arm32 implementations of pci_domain_nr/pci_proc_domain can probably be
> removed if we change the arm32 pcibios_init_hw function to call the new
> interfaces that set the domain number.
I wished, but it is a bit more comp
On Thu, Oct 23, 2014 at 10:13:09AM +0100, Liviu Dudau wrote:
> On Wed, Oct 22, 2014 at 09:52:19PM +0100, Arnd Bergmann wrote:
> > On Wednesday 22 October 2014 16:59:14 Lorenzo Pieralisi wrote:
> > > On Wed, Oct 01, 2014 at 10:38:45AM +0100, A
: Will Deacon
Signed-off-by: Lorenzo Pieralisi
---
drivers/pci/host/pci-host-generic.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pci-host-generic.c
b/drivers/pci/host/pci-host-generic.c
index 3d2076f..1e1a80f 100644
--- a/drivers/pci/host/pci
space by using the newly introduced
pci_ioremap_iospace() API.
New code supports only one IO resource per generic host controller, which
should cater for all existing host controller configurations.
Cc: Arnd Bergmann
Cc: Will Deacon
Cc: Bjorn Helgaas
Signed-off-by: Lorenzo Pieralisi
---
drivers
On Wed, Nov 05, 2014 at 10:15:36AM +, Chander Kashyap wrote:
> Exynos7 has core power down state where cores can be powered off
> independently.
> This patch adds support for this state.
>
> Entry latency for the core power down is calculated as follows:
> 1. Time difference is measured betwe
On Thu, Nov 06, 2014 at 12:05:48AM +, Arnd Bergmann wrote:
> On Wednesday 05 November 2014 16:39:21 Bjorn Helgaas wrote:
> > On Wed, Oct 22, 2014 at 10:52:19PM +0200, Arnd Bergmann wrote:
> > > On Wednesday 22 October 2014 16:59:14 Lorenzo Pieralisi wrote:
> > > >
On Thu, Nov 06, 2014 at 12:05:36AM +, Bjorn Helgaas wrote:
> On Thu, Oct 23, 2014 at 04:23:06PM +0100, Lorenzo Pieralisi wrote:
> > The number of windows allocated for the host bridge depends on the
> > bus resource. Instead of first allocating the windows and then
> > l
On Thu, Nov 06, 2014 at 05:57:19PM +, Anatol Pomozov wrote:
> Quoting ARMv8 Reference Manual section D6.1:
> "The system counter must be implemented in an always-on power domain."
Do not mix up the system counter with arch timers. System counter is
always-on, but the arch timer(s) logic (that
On Mon, Oct 27, 2014 at 09:58:10AM +, Hanjun Guo wrote:
[...]
> >> +static int map_gicc_mpidr(struct acpi_subtable_header *entry,
> >> + int device_declaration, u32 acpi_id, int *mpidr)
> >> +{
> >> + struct acpi_madt_generic_interrupt *gicc =
> >> + container_of(entry, struct
On Fri, Oct 10, 2014 at 07:31:26PM +0100, Arnd Bergmann wrote:
> On Friday 10 October 2014 14:58:04 Lorenzo Pieralisi wrote:
> > On Thu, Oct 09, 2014 at 11:51:43AM +0100, Arnd Bergmann wrote:
> >
> > > > Last changes where introduced by commit 8c05cd08a, whose co
On Wed, Oct 15, 2014 at 07:35:20AM +0100, Chander Kashyap wrote:
> Exynos7 has core power down state where cores can be powered off
> independently.
> This patch adds support for this state.
Please tell us more about the idle-state values you are adding, in particular
entry, exit latencies and mi
additional offset should be applied.
Cc: Arnd Bergmann
Cc: Russell King
Signed-off-by: Lorenzo Pieralisi
---
arch/arm/kernel/bios32.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 17a26c1..b56fa2d 100644
--- a
Cc: Derrick J. Wong
Signed-off-by: Lorenzo Pieralisi
---
drivers/pci/pci-sysfs.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 92b6d9a..777d8bc 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.
On Wed, Oct 15, 2014 at 02:02:18PM +0100, Mark Rutland wrote:
> > > + CPU_SLEEP: cpu-sleep {
> > > + compatible = "arm,idle-state";
> > > + local-timer-stop;
> > > + arm,psci-suspend-param = <0x001>;
> > > +
On Wed, Oct 01, 2014 at 10:38:45AM +0100, Arnd Bergmann wrote:
[...]
> pci_mmap_page_range could either get generalized some more in an attempt
> to have a __weak default implementation that works on ARM, or it could
> be changed to lose the dependency on pci_sys_data instead. In either
> case, t
On Tue, Oct 07, 2014 at 02:52:27PM +0100, Arnd Bergmann wrote:
> On Tuesday 07 October 2014 13:06:59 Lorenzo Pieralisi wrote:
> > On Wed, Oct 01, 2014 at 10:38:45AM +0100, Arnd Bergmann wrote:
> >
> > [...]
> >
> > > pci_mmap_page_range could either get
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