On Wed, Jun 03, 2015 at 10:36:19AM +0100, Jiang Liu wrote:
> On 2015/6/3 16:44, Hanjun Guo wrote:
> > On 2015???06???02??? 17:35, Lorenzo Pieralisi wrote:
> >> On Tue, Jun 02, 2015 at 07:12:53AM +0100, Jiang Liu wrote:
> >>> From: Hanjun Guo
> >>>
> &g
On Tue, Jun 02, 2015 at 06:02:49PM +0100, Guenter Roeck wrote:
> On 06/02/2015 07:55 AM, Lorenzo Pieralisi wrote:
> > Bjorn, Guenter,
> >
> > On Wed, May 27, 2015 at 10:04:47PM +0100, Bjorn Helgaas wrote:
> >> [+cc Lorenzo, Suravee, Will]
> >>
> >> I
On Wed, Jun 03, 2015 at 11:21:16AM +0100, Jiang Liu wrote:
> On 2015/6/3 18:03, Lorenzo Pieralisi wrote:
> > On Wed, Jun 03, 2015 at 10:36:19AM +0100, Jiang Liu wrote:
> >> On 2015/6/3 16:44, Hanjun Guo wrote:
> >>> On 2015???06???02??? 17:35, Lorenzo Pieralisi wrot
On Wed, Jun 03, 2015 at 04:12:24PM +0100, Guenter Roeck wrote:
[...]
> >> After looking into this some more, I think the wrinkle may be that
> >> pci_read_bridge_bases() and thus pci_read_bridge_io() isn't called
> >> on probe-only systems (if PCI_PROBE_ONLY is set). A secondary
> >
> > That's wh
Hi Hanjun,
On Thu, Jun 04, 2015 at 10:28:17AM +0100, Hanjun Guo wrote:
> Hi Lorenzo,
>
> On 2015???06???02??? 21:32, Lorenzo Pieralisi wrote:
> > On Wed, May 27, 2015 at 09:06:26AM +0100, Tomasz Nowicki wrote:
> >> On 26.05.2015 19:08, Will Deacon wrote:
> >>>
entry-latency-us = <639>;
> + exit-latency-us = <680>;
> + min-residency-us = <1088>;
> + local-timer-stop;
> + };
> };
> };
I guess there
resource hierarchy as soon as
the bridge bases are probed.
Signed-off-by: Lorenzo Pieralisi
Cc: Ralf Baechle
Cc: James E.J. Bottomley
Cc: Michael Ellerman
Cc: Bjorn Helgaas
Cc: Richard Henderson
Cc: Benjamin Herrenschmidt
Cc: David Howells
Cc: Russell King
Cc: Tony Luck
Cc: David S. Miller
On Mon, Jun 08, 2015 at 05:20:46PM +0100, Jiang Liu wrote:
[...]
> +static int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
> +{
> + int ret;
> + struct list_head *list = &info->resources;
> + struct acpi_device *device = info->bridge;
> + struct resource_entry *
On Tue, Jun 09, 2015 at 05:58:15PM +0100, Jiang Liu wrote:
> On 2015/6/10 0:12, Lorenzo Pieralisi wrote:
[...]
> >> +struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> >> + struct acpi_pci_root_ops *ops,
> >> +
Hi Guenter,
On Thu, Jun 18, 2015 at 07:01:03PM +0100, Guenter Roeck wrote:
> On Thu, May 28, 2015 at 07:41:12AM -0500, Bjorn Helgaas wrote:
> >
> > > > I'd like res->flags to reflect the capabilities of the hardware, not
> > > > whether the window is currently enabled.
> > > >
> > > Flag bits se
On Wed, May 23, 2018 at 11:44:25AM +0100, Srinivas Kandagatla wrote:
> This patch is required when the pcie controller sits on a bus with
> its own power domain and clocks which are controlled via a bus driver
> like simple pm bus. As these bus driver have runtime pm enabled, it makes
> sense to up
On Wed, Feb 28, 2018 at 02:07:19PM +0100, Rolf Evers-Fischer wrote:
> From: Rolf Evers-Fischer
>
> Removes the goto labels completely, handles the errors at the
> respective call site and just returns instead of jumping around.
>
> Signed-off-by: Rolf Evers-Fischer
> ---
> drivers/pci/endpoint
On Tue, Feb 27, 2018 at 12:59:05PM +0100, Niklas Cassel wrote:
> A 64-bit BAR uses the succeeding BAR for the upper bits, therefore
> we cannot call pci_epc_set_bar() on a BAR that follows a 64-bit BAR.
>
> If pci_epc_set_bar() is called with flag PCI_BASE_ADDRESS_MEM_TYPE_64,
PCI_BASE_ADDRESS_ME
On Fri, Jan 19, 2018 at 09:26:51PM -0600, Gustavo A. R. Silva wrote:
> Bool initializations should use true and false.
>
> This issue was detected with the help of Coccinelle.
>
> Fixes: eaa6111b70a7 ("PCI: altera: Add Altera PCIe host controller driver")
> Signed-off-by: Gustavo A. R. Silva
> -
On Wed, Feb 28, 2018 at 06:32:17PM +0100, Rolf Evers-Fischer wrote:
> This is version 5 of a patchset to avoid double free in function
> 'pci_epf_create()'.
>
> When I accidentally created a new endpoint device with an empty name,
> the kernel warned about "attempted to be registered with empty na
On Wed, Feb 14, 2018 at 11:27:58AM +0800, Ryder Lee wrote:
> dtc recently added PCI bus checks. Fix these warnings:
>
> Warning (pci_bridge): Node /pcie@1a14/pcie@0,0 missing bus-range for PCI
> bridge
> Warning (pci_bridge): Node /pcie@1a14/pcie@1,0 missing bus-range for PCI
> bridge
>
On Thu, Mar 01, 2018 at 09:01:53PM +0530, Vignesh R wrote:
> Hi Lorenzo,
>
> On 15-Feb-18 9:59 AM, Vignesh R wrote:
> > Hi,
> >
> > On Monday 12 February 2018 11:28 PM, Lorenzo Pieralisi wrote:
> >> On Fri, Feb 09, 2018 at 05:34:14PM +0530, Vignesh R wrote:
&g
On Mon, Apr 02, 2018 at 09:37:03PM +0200, Niklas Cassel wrote:
> On Thu, Mar 29, 2018 at 03:17:11PM +0530, Kishon Vijay Abraham I wrote:
> > Hi,
> >
> > On Wednesday 28 March 2018 05:20 PM, Niklas Cassel wrote:
> > > Since a 64-bit BAR consists of a BAR pair, we need to write to both
> > > BARs in
On Tue, Apr 03, 2018 at 09:15:11AM +0800, Hanjun Guo wrote:
> [+Cc Lorenzo]
>
> Hi Neil,
>
> On 2018/4/3 1:59, Neil Leeder wrote:
> > Hi Hanjun,
> >
> > On 4/2/2018 10:24 AM, Hanjun Guo wrote:
> >
> >>
> >> I think we need to wait for the new version of IORT spec,
> >> which includes the fix fo
On Wed, Mar 28, 2018 at 12:38:33PM +0100, Gustavo Pimentel wrote:
Please always write a commit log even if it is trivial.
Thanks,
Lorenzo
> Signed-off-by: Gustavo Pimentel
> ---
> Documentation/devicetree/bindings/pci/designware-pcie.txt | 13 +
> 1 file changed, 13 insertions(+)
>
[+cc Robin]
On Thu, Mar 29, 2018 at 03:01:00AM -0700, Wang Dongsheng wrote:
> If SMMU probe failed, master should use swiotlb as dma ops.
> SMMU may probe failed with specified environment, so there
> are not any iommu resources in iommu_device_list.
>
> The master will always get EPROBE_DEFER fr
On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
> Adds a seconds entry on the pci_epf_test_ids structure that disables the
"Add a second entry to..."
> linkup_notifier parameter on driver for the designware EP.
>
> This allows designware EPs that doesn't have linkup notificatio
> >disabling them"
Yes, I think that's the best course of action and it was the outcome
of that email thread.
Lorenzo
> Thanks
> Rohit
>
> From: Lorenzo Pieralisi
> Sent: Thursday, April 26, 2018 3:18 AM
> To: Catali
On Fri, Apr 27, 2018 at 12:59:58PM +0100, Gustavo Pimentel wrote:
> Add a seconds entry on the pci_epf_test_ids structure that disables the
"Add a second entry..."
> linkup_notifier parameter on driver for the DesignWare EP.
>
> Allow DesignWare EPs that doesn't have linkup notification signal t
On Tue, May 01, 2018 at 03:37:47PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On Thursday 26 April 2018 10:26 PM, Lorenzo Pieralisi wrote:
> > On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
> >> Adds a seconds entry on the pci_epf_test_ids
On Tue, May 01, 2018 at 05:53:59PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On Tuesday 01 May 2018 05:24 PM, Lorenzo Pieralisi wrote:
> > On Tue, May 01, 2018 at 03:37:47PM +0530, Kishon Vijay Abraham I wrote:
> >> Hi Lorenzo,
> >>
> >> O
On Wed, May 02, 2018 at 11:39:00AM +0100, Gustavo Pimentel wrote:
> Hi Lorenzo,
>
> On 01/05/2018 15:26, Lorenzo Pieralisi wrote:
> > On Tue, May 01, 2018 at 05:53:59PM +0530, Kishon Vijay Abraham I wrote:
> >> Hi Lorenzo,
> >>
> >> On Tuesday 01
On Tue, May 15, 2018 at 03:41:40PM +0100, Gustavo Pimentel wrote:
> Patch set was made against the Lorenzo's pci/dwc branch.
>
> The PCIe controller dual mode is capable of operating in RC mode as well
> as EP mode by configuration option. Till now only RC mode was supported,
> with this patch is
On Wed, Mar 07, 2018 at 12:41:05PM +, Lorenzo Pieralisi wrote:
> On Fri, Mar 02, 2018 at 11:42:07AM +0100, Thierry Reding wrote:
> > On Fri, Mar 02, 2018 at 12:37:24AM +0100, Rasmus Villemoes wrote:
> > > Simplify the code slightly by having seq_open_data do the ->pri
compilation unit,
pci_get_new_domain_nr() can be made static, which also simplifies
preprocessor conditionals.
No functional change intended."
> Signed-off-by: Jan Kiszka
> ---
> drivers/pci/pci.c | 6 ++
> include/linux/pci.h | 3 ---
> 2 files changed, 2 insertions(+), 7 dele
On Tue, Apr 24, 2018 at 05:13:42PM +0200, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Required when running over Jailhouse, and there is already a physical
> host controller that Jailhouse does not intercept and rather adds a
> virtual one. That is the case for the Tegra TK1, e.g.
>
> Signed-off-by
On Thu, Apr 26, 2018 at 08:25:14AM +0100, Catalin Marinas wrote:
> On Wed, Apr 25, 2018 at 11:36:06PM +, Rohit Khanna wrote:
> > Adding few other folks.
>
> It looks fine to me but cc'ing Mark and Lorenzo (and it should have been
> posted on linux-arm-ker...@lists.infradead.org).
>
> > From:
On Wed, Feb 27, 2019 at 05:51:46PM -0600, Bjorn Helgaas wrote:
> On Wed, Feb 27, 2019 at 3:01 PM Stephen Rothwell
> wrote:
> >
> > Hi Bjorn,
> >
> > Commit
> >
> > a048671aa0c8 ("PCI: qcom: Don't deassert reset GPIO during probe")
> >
> > is missing a Signed-off-by from its committer.
>
> Lore
On Thu, Feb 28, 2019 at 02:35:06AM +, Maya Nakamura wrote:
> Remove a duplicate definition of VP set (hv_vp_set) and use the common
> definition (hv_vpset) that is used in other places.
>
> Change the order of the members in struct hv_pcibus_device so that the
> declaration of retarget_msi_int
On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
[...]
> +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
> +{
> + int i;
> + u32 ctrl;
> + u32 comp_status;
> + u32 dw[4];
> + u32 count;
> +
> + for (i = 0; i < TLP_LOOP; i++) {
> +
On Wed, Feb 20, 2019 at 10:03:55PM +0530, Srinath Mannam wrote:
> In the present driver outbound window configuration is done to map above
> 32-bit address I/O regions with corresponding PCI memory range given in
> ranges DT property.
>
> This patch add outbound window configuration to map below 3
On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The PCIE_AXI_WINDOW0 defines the translate window size for the request
> from EP side. Request outside of this window will be treated as
> unsupported request.
>
> Enlarge this window size from
On Fri, Feb 01, 2019 at 01:36:05PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Two patches:
> patch 1 enable whole MMIO range which also fix the complain of
> scripts/coccinelle/api/resource_size.cocci
> patch 2 enlarge the PCIe2AHB window size to support fully access of 4
On Fri, Mar 01, 2019 at 12:55:59AM -0800, Andrey Smirnov wrote:
> The clock in question is not present on i.MX7, so move the code
> requesting it into i.MX8MQ-only path.
>
> Fixes: eeb61c4e8530 ("PCI: imx6: Add code to request/control
> "pcie_aux" clock for i.MX8MQ")
> Reported-by: Trent Piepho
>
On Fri, Mar 01, 2019 at 06:54:45AM +, Maya Nakamura wrote:
> This patchset removes a duplicate definition of VP set (hv_vp_set) and
> uses the common definition (hv_vpset) that is used in other places. It
> changes the order of the members in struct hv_pcibus_device due to
> flexible array in h
On Fri, Mar 01, 2019 at 08:50:48AM +0800, Ley Foon Tan wrote:
> On Thu, 2019-02-28 at 10:56 +0000, Lorenzo Pieralisi wrote:
> > On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote:
> >
> > [...]
> >
> > >
> > > +static int s10_tlp_read_pack
On Mon, Apr 15, 2019 at 04:53:49PM +0800, Mao Wenan wrote:
> There is one warning exist while compiling
> drivers/pci/controller/dwc/pcie-hisi.c.
> make allmodconfig ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-
> make C=2 drivers/pci/controller/dwc/pcie-hisi.o ARCH=arm64
> CROSS_COMPILE=aarch64-li
On Wed, Apr 10, 2019 at 10:09:49PM +0800, Yue Haibing wrote:
> From: YueHaibing
>
> Fix sparse warning:
>
> drivers/pci/controller/pci-mvebu.c:557:28: warning:
> symbol 'mvebu_pci_bridge_emul_ops' was not declared. Should it be static?
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
On Sat, Apr 13, 2019 at 11:00:53AM -0500, Bjorn Helgaas wrote:
> On Mon, Mar 25, 2019 at 02:04:58PM +0530, Kishon Vijay Abraham I wrote:
> > Configure RESBAR capability to advertise the smallest size (1MB) for
> > couple of reasons. A) Host side resource allocation of BAR fails for
> > larger sizes
5 files changed, 113 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-al.c
I think Bjorn can take this if he is OK with it, it is not really
necessary to queue it via the controller/dwc tree so:
Acked-by: Lorenzo Pieralisi
> diff --git a/MAINTAINERS b/MAINTAINERS
>
On Sat, Apr 13, 2019 at 10:44:37AM -0500, Bjorn Helgaas wrote:
> On Mon, Mar 25, 2019 at 03:09:41PM +0530, Kishon Vijay Abraham I wrote:
> > commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while
> > adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and
> > __dw_
On Sat, Apr 13, 2019 at 10:26:33AM -0500, Bjorn Helgaas wrote:
> On Mon, Mar 25, 2019 at 03:09:35PM +0530, Kishon Vijay Abraham I wrote:
> > Add PCIe RC support for AM654x Platforms in pci-keystone.c
>
> > +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp)
> > +{
> > + struct dw_pcie
On Wed, Apr 24, 2019 at 12:29:18AM +0200, Remi Pommarel wrote:
> Hi,
>
> On Tue, Apr 23, 2019 at 05:32:15PM +0100, Lorenzo Pieralisi wrote:
> > On Wed, Mar 13, 2019 at 10:37:52PM +0100, Remi Pommarel wrote:
> > > When configuring pcie reset pin from gpio (e.g. initially
On Sat, Mar 16, 2019 at 05:12:43PM +0100, Remi Pommarel wrote:
> The PCI_EXP_LNKSTA_LT flag in the emulated root device's PCI_EXP_LNKSTA
> config register does not reflect the actual link training state and is
> always cleared. The Link Training and Status State Machine (LTSSM) flag
> in LMI config
On Mon, Feb 18, 2019 at 05:46:38PM +0800, Xiaowei Bao wrote:
> Add the EP mode support for Mobiveil base on endpoint framework.
>
> Signed-off-by: Xiaowei Bao
> ---
> depends on: http://patchwork.ozlabs.org/project/linux-pci/list/?series=88754
You will have to rebase it on top of the updated ser
On Thu, Apr 25, 2019 at 04:23:53PM +0200, Remi Pommarel wrote:
> Hi Lorenzo,
>
> On Thu, Apr 25, 2019 at 12:08:30PM +0100, Lorenzo Pieralisi wrote:
> > On Sat, Mar 16, 2019 at 05:12:43PM +0100, Remi Pommarel wrote:
> > > The PCI_EXP_LNKSTA_LT flag in the emulated root
On Mon, Mar 25, 2019 at 03:09:43PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe EP support for AM654x Platforms in pci-keystone.c
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/pci/controller/dwc/Kconfig| 23 +-
> drivers/pci/controller/dwc/pci-keystone.c | 242 +++
On Tue, Dec 18, 2018 at 12:02:42PM +, Fabrizio Castro wrote:
> Add PCIe support for the RZ/G2E (a.k.a. R8A774C0).
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Geert Uytterhoeven
> ---
> v1->v2:
> * Dropped change to the description of "phys" optional property according
> to Geert's co
On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> Reviewed-by: Subrahmanya Lingappa
I have a feeling you do not read what I write. Please never top-post.
Read this, especially the email etiquette section:
https://kernelnewbies.org/PatchCulture
>
>
>
> On Tue, Jan 29, 2
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
> Reviewed-by: Rob Herring
> ---
> v2:
>
On Wed, Feb 06, 2019 at 10:57:31AM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_conf() do not read/write beyond that point.
>
> Suggested-by: Trent Piepho
> Signed-off-by: Stefan Agner
> ---
> Changes in v4:
> - Move length check to
On Fri, Jan 25, 2019 at 11:05:30AM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Wed, 23 Jan 2019
> 17:05:09 +:
>
> > On Tue, Jan 08, 2019 at 05:24:25PM +0100, Miquel Raynal wrote:
> > > Hello,
> > >
> > > As part
On Fri, Jan 25, 2019 at 01:57:57PM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Fri, 25 Jan 2019
> 12:40:11 +:
>
> > On Fri, Jan 25, 2019 at 11:05:30AM +0100, Miquel Raynal wrote:
> > > Hi Lorenzo,
> > >
> > &
On Fri, Mar 01, 2019 at 08:17:27AM +0100, Greg KH wrote:
> On Thu, Feb 28, 2019 at 11:37:45PM -0600, Parav Pandit wrote:
> > Introduce a new subdev bus which holds sub devices created from a
> > primary device. These devices are named as 'subdev'.
> > A subdev is identified similarly to pci device
[+Zhou, Gustavo]
On Tue, Mar 26, 2019 at 12:00:55PM +0200, Jonathan Chocron wrote:
> Adding support for Amazon's Annapurna Labs PCIe driver.
> The HW controller is based on DesignWare's IP.
>
> The HW doesn't support accessing the Root Port's config space via
> ECAM, so we obtain its base address
On Tue, Mar 26, 2019 at 01:24:41PM +, David Woodhouse wrote:
> On Tue, 2019-03-26 at 12:17 +0000, Lorenzo Pieralisi wrote:
> > [+Zhou, Gustavo]
> >
> > On Tue, Mar 26, 2019 at 12:00:55PM +0200, Jonathan Chocron wrote:
> > > Adding support for Amazon's Annap
On Mon, Mar 11, 2019 at 09:32:04AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> As the Mobiveil PCIe controller support RC&EP DAUL mode, and to
> make platforms which integrated the Mobiveil PCIe IP more easy
> to add their drivers, this patch moved the Mobiveil driver to
> a new directory 'dr
On Mon, Mar 11, 2019 at 09:29:54AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> This patch set is aim to refactor the Mobiveil driver and add
> PCIe support for NXP Layerscape series SoCs integrated Mobiveil's
> PCIe Gen4 controller.
>
> Hou Zhiqiang (28):
> PCI: mobiveil: uniform the regis
On Wed, Mar 27, 2019 at 09:52:15AM +, David Woodhouse wrote:
> On Tue, 2019-03-26 at 15:58 +0000, Lorenzo Pieralisi wrote:
> > > We did that internally. You really don't want me telling engineers to
> > > post to the list *first* without running things by me to get t
On Wed, Mar 27, 2019 at 09:43:26AM +, David Woodhouse wrote:
> On Tue, 2019-03-26 at 12:17 +0000, Lorenzo Pieralisi wrote:
> > This code is basically identical to (apart from the string matching
> > the DBI resource)
> >
> > drivers/pci/controller/pcie-hisi.c
&g
patch set extends support of new IPROC PCIe host controller features
> > - Add CRS check using controller register status flags
> > - Add outbound window mapping configuration for 32-bit I/O region
> >
> > This patch set is based on Linux-5.0-rc2.
> >
> > Changes
On Wed, Mar 27, 2019 at 02:04:00AM +, Z.q. Hou wrote:
> Hi Lorenzo,
>
> Thanks for your comments!
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2019年3月27日 1:34
> > To: Z.q. Hou
> > Cc: linux-...@vger.kernel.org; linux-a
On Wed, Mar 27, 2019 at 06:40:07PM +, Leonard Crestez wrote:
> On Wed, 2019-03-27 at 17:45 +, Marc Zyngier wrote:
> > On 27/03/2019 16:06, Lucas Stach wrote:
> > > Am Mittwoch, den 27.03.2019, 15:57 + schrieb Marc Zyngier:
> > > > On 27/03/2019 15:44, Lucas Stach wrote:
> > > > > Am Mit
it message again and indeed it looks quite confusing.
> >
> > I'll add my comment inline in the code section. I hope that will help to
> > make it more clear.
> >
> > On 4/1/2019 9:44 AM, Lorenzo Pieralisi wrote:
> > > On Mon, Apr 01, 2019 at 11:04:48AM +
On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Mannam wrote:
[...]
> > Ok - I start to understand. What does it mean in HW terms that your
> > 32bit AXI address region size is 32MB ? Please explain to me in details.
> >
> In our PCIe controller HW, AXI address from 0x4200 to 0x4400
> o
On Mon, Apr 01, 2019 at 05:00:40PM +, Bharat Kumar Gogada wrote:
> Hi All,
>
> Please let me know if anyone has any inputs on this.
>
> Regards,
> Bharat
> >
> > The current Multi MSI data programming fails if multiple end points
> > requesting MSI and multi MSI are connected with switch, i.
On Wed, Apr 03, 2019 at 08:41:44AM +0530, Srinath Mannam wrote:
> Hi Lorenzo,
>
> Please see my reply below,
>
> On Tue, Apr 2, 2019 at 7:08 PM Lorenzo Pieralisi
> wrote:
> >
> > On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Mannam wrote:
> >
> > [.
On Thu, Mar 21, 2019 at 03:29:19PM +0530, Kishon Vijay Abraham I wrote:
> This series tries to address the comments discussed in [1] w.r.t
> removing Keystone specific callbacks defined in dw_pcie_host_ops.
>
> This series also tries to cleanup the Keystone interrupt handling
> part.
>
> Changes
On Thu, Mar 21, 2019 at 03:29:27PM +0530, Kishon Vijay Abraham I wrote:
> Platforms which populate msi_host_init, has it's own MSI controller
> logic. Writing to MSI control registers on platforms which doesn't use
> Designware's MSI controller logic might have side effects. To
> be safe, do not wr
On Thu, Mar 21, 2019 at 03:29:19PM +0530, Kishon Vijay Abraham I wrote:
> This series tries to address the comments discussed in [1] w.r.t
> removing Keystone specific callbacks defined in dw_pcie_host_ops.
>
> This series also tries to cleanup the Keystone interrupt handling
> part.
>
> Changes
On Wed, Apr 10, 2019 at 02:54:16PM +0800, Chunfeng Yun wrote:
> Use devm_clk_get_optional() to get optional clock
>
> Cc: Ryder Lee
> Cc: Honghui Zhang
> Signed-off-by: Chunfeng Yun
> Acked-by: Ryder Lee
> Acked-by: Honghui Zhang
> ---
> v3: add Acked-by Ryder and Honghui
> ---
> drivers/pci
On Thu, Apr 04, 2019 at 04:36:07PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> This series includes a couple of patches, one which fixes
> inadvertent removal of pcitest.sh from kernel repo when
> doing a "clean" and other lets the user use 'h' option to
> display the list of options su
On Mon, Mar 25, 2019 at 03:09:37PM +0530, Kishon Vijay Abraham I wrote:
> of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled.
> Make of_pci_get_max_link_speed() to be also used by PCI Endpoint
> controllers with just CONFIG_PCI_ENDPOINT enabled.
>
> Signed-off-by: Kishon Vijay Abra
On Mon, Mar 25, 2019 at 03:09:33PM +0530, Kishon Vijay Abraham I wrote:
> hook_fault_code is an ARM32 specific API for hooking into data abort.
> Since pci-keystone.c will be used for AM65X platforms which is an
> ARM64 platform,
Hi Kishon,
How is the problem plugged by the fault hook fixed on AR
On Mon, Mar 25, 2019 at 03:09:39PM +0530, Kishon Vijay Abraham I wrote:
> Modify pci_epf_alloc_space API to take alignment size as argument in
> order to argument in order to allocate aligned buffers to be mapped to
> BARs.
>
> Add 'align' parameter to epc_features which can be used by platform
>
On Wed, Feb 27, 2019 at 01:34:44PM +0100, Vitaly Kuznetsov wrote:
> Maya Nakamura writes:
>
> > Remove the duplicate implementation of cpumask_to_vpset() and use the
> > shared implementation. Export hv_max_vp_index, which is required by
> > cpumask_to_vpset().
> >
> > Apply changes to hv_irq_unm
On Wed, Feb 27, 2019 at 04:53:37PM +0100, Vitaly Kuznetsov wrote:
> Maya Nakamura writes:
>
> > Remove a duplicate definition of VP set (hv_vp_set) and use the common
> > definition (hv_vpset) that is used in other places.
> >
> > Change the order of the members in struct hv_pcibus_device so that
On Tue, Feb 26, 2019 at 05:15:46PM +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix 10 device.
>
> Main differences compare with PCIe Root Port IP on Cyclone V
> and Arria 10 devices:
>
> - HIP interface to access Root Port configuration register.
> - TLP programming flow:
>
hange the state of the register resulting in
> a spurious tag check fault report.
>
> Report asynchronous tag faults before suspend and clear the TFSR_EL1
> register after resume to prevent this to happen.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Lorenzo Pieral
On Fri, Feb 12, 2021 at 12:00:15PM +, Lorenzo Pieralisi wrote:
> On Thu, Feb 11, 2021 at 03:33:52PM +, Vincenzo Frascino wrote:
> > When MTE async mode is enabled TFSR_EL1 contains the accumulative
> > asynchronous tag check faults for EL1 and EL0.
> >
> >
On Wed, Feb 10, 2021 at 07:53:45AM +, Wei Yongjun wrote:
> It's not necessary to free memory allocated with devm_kzalloc
> and using kfree leads to a double free.
>
> Fixes: 363baf7d6051 ("NTB: Add support for EPF PCI-Express Non-Transparent
> Bridge")
Squashed it in the commit it is fixing
On Tue, 9 Feb 2021 15:46:20 +0100, Nadeem Athani wrote:
> Cadence controller will not initiate autonomous speed change if strapped
> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
> Adding a quirk flag for defective IP. In future IP revisions this will not
> be applicabl
On Fri, Jan 29, 2021 at 06:12:56PM +0530, Kishon Vijay Abraham I wrote:
> This series is about implementing SW defined Non-Transparent Bridge (NTB)
> using multiple endpoint (EP) instances. This series has been tested using
> 2 endpoint instances in J7 connected to J7 board on one end and DRA7 boar
On Wed, 6 Jan 2021 16:15:00 +0530, Shradha Todi wrote:
> Since outbound iATU permits size to be greater than 4GB for which the
> support is also available, allow EP function to send u64 size instead of
> truncating to u32.
Applied to pci/dwc, thanks!
[1/1] PCI: dwc: Change size to u64 for EP outb
On Wed, Jan 06, 2021 at 04:20:10PM +0530, Shradha Todi wrote:
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
>
>
On Tue, 2 Feb 2021 01:27:52 +0530, Kishon Vijay Abraham I wrote:
> This series is about implementing SW defined Non-Transparent Bridge (NTB)
> using multiple endpoint (EP) instances. This series has been tested using
> 2 endpoint instances in J7 connected to J7 board on one end and DRA7 board
> on
(.text+0x1b): undefined reference to
> `config_group_init_type_name'
>
> Fixes: 7dc64244f9e9 ("PCI: endpoint: Add EP function driver to provide NTB
> functionality")
>
> Signed-off-by: Randy Dunlap
> Cc: Kishon Vijay Abraham I
> Cc: Lorenzo Pieralisi
>
On Tue, 2 Feb 2021 12:58:38 +0530, Shradha Todi wrote:
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
Applied to
On Thu, Feb 04, 2021 at 07:15:39PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 04/02/21 3:28 pm, Lorenzo Pieralisi wrote:
> > On Tue, Feb 02, 2021 at 12:12:55PM -0800, Randy Dunlap wrote:
> >> The pci-epf-ntb driver uses configfs APIs, so it should depen
On Wed, Dec 30, 2020 at 01:05:15PM +0100, Nadeem Athani wrote:
> Cadence controller will not initiate autonomous speed change if strapped
> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
>
> Signed-off-by: Nadeem Athani
> ---
> drivers/pci/controller/cadence/pci-j721e
hange the state of the register resulting in
> a spurious tag check fault report.
>
> Save/restore the state of the TFSR_EL1 register during the
> suspend/resume operations to prevent this to happen.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Lorenzo Pieral
On Tue, Feb 09, 2021 at 11:55:33AM +, Catalin Marinas wrote:
> On Mon, Feb 08, 2021 at 04:56:16PM +, Vincenzo Frascino wrote:
> > When MTE async mode is enabled TFSR_EL1 contains the accumulative
> > asynchronous tag check faults for EL1 and EL0.
> >
> > During the suspend/resume operation
On Thu, Feb 18, 2021 at 12:43:30PM -0500, Jon Masters wrote:
> Hi Bjorn, all,
>
> On Thu, Jan 28, 2021 at 6:31 PM Bjorn Helgaas wrote:
>
> On Tue, Jan 26, 2021 at 10:46:04AM -0600, Jeremy Linton wrote:
>
>
>
> > Does that mean its open season for ECAM quirks, and we can expect
>
On Fri, May 29, 2020 at 08:05:18PM +0200, Thierry Reding wrote:
> On Thu, May 21, 2020 at 10:47:09AM +0800, Dinghao Liu wrote:
> > pm_runtime_get_sync() increments the runtime PM usage counter even
> > when it returns an error code. Thus a pairing decrement is needed on
> > the error handling path
On Tue, May 19, 2020 at 07:25:02PM +0530, Vidya Sagar wrote:
>
>
> On 18-May-20 9:24 PM, Lorenzo Pieralisi wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, May 13, 2020 at 05:35:08PM -0500, Bjorn Helgaas wrote:
>
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