Hi Liuxiangdong,
On 2021/4/9 16:33, Liuxiangdong (Aven, Cloud Infrastructure Service Product
Dept.) wrote:
Do you have any comments or ideas about it ?
https://lore.kernel.org/kvm/606e5ef6.2060...@huawei.com/
My expectation is that there may be many fewer PEBS samples
on Skylake without any
Em, does anyone want to review these minor changes？
I believe some of them solve the real problem.
On 2021/4/6 11:20, Like Xu wrote:
Hi all, do we have any comments on this patch set?
On 2021/3/26 9:19, Like Xu wrote:
Hi Peter,
Please help review these minor perf/x86 changes in this patch
On 2019/4/24 1:44, Sean Christopherson wrote:
On Tue, Apr 23, 2019 at 11:23:59AM +0800, Like Xu wrote:
On 2019/4/23 2:35, Sean Christopherson wrote:
#define F(x) bit(X86_FEATURE_##x)
int kvm_update_cpuid(struct kvm_vcpu *vcpu)
@@ -426,6 +436,7 @@ static inline int __do_cpuid_ent(struct
On 2019/4/24 22:32, Sean Christopherson wrote:
Now that I understand how min() works...
On Mon, Apr 22, 2019 at 02:40:34PM +0800, Like Xu wrote:
Expose Intel V2 Extended Topology Enumeration Leaf to guest only when
host system has multiple software-visible die within each package.
Signed-off
On 2019/4/25 12:18, Xiaoyao Li wrote:
On Thu, 2019-04-25 at 10:58 +0800, Like Xu wrote:
On 2019/4/24 22:32, Sean Christopherson wrote:
Now that I understand how min() works...
On Mon, Apr 22, 2019 at 02:40:34PM +0800, Like Xu wrote:
Expose Intel V2 Extended Topology Enumeration Leaf to guest
On 2019/4/25 14:30, Xiaoyao Li wrote:
On Thu, 2019-04-25 at 14:02 +0800, Like Xu wrote:
On 2019/4/25 12:18, Xiaoyao Li wrote:
On Thu, 2019-04-25 at 10:58 +0800, Like Xu wrote:
On 2019/4/24 22:32, Sean Christopherson wrote:
Now that I understand how min() works...
On Mon, Apr 22, 2019 at 02
On 2019/4/25 22:19, Sean Christopherson wrote:
On Thu, Apr 25, 2019 at 03:07:35PM +0800, Like Xu wrote:
On 2019/4/25 14:30, Xiaoyao Li wrote:
Besides, the problem of simply using cpuid_exc(0x1f) in Sean's codes is
that we cannot assmue the reserved bits 31:16 of ECX is always 0 for the
f
On 2019/4/26 0:28, Xiaoyao Li wrote:
On Thu, 2019-04-25 at 23:33 +0800, Like Xu wrote:
On 2019/4/25 22:19, Sean Christopherson wrote:
On Thu, Apr 25, 2019 at 03:07:35PM +0800, Like Xu wrote:
On 2019/4/25 14:30, Xiaoyao Li wrote:
Besides, the problem of simply using cpuid_exc(0x1f) in Sean&#
Some new systems have multiple software-visible die within each package.
Add support to expose Intel V2 Extended Topology Enumeration Leaf CPUID.1F.
Co-developed-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
Signed-off-by: Like Xu
---
==changelog==
v2:
- Apply cpuid.1f check rule on Intel SDM page
Here are some of the more common spelling mistakes and typos that I've
found while fixing up spelling mistakes in the kernel.
Signed-off-by: Like Xu
---
scripts/spelling.txt | 579 +++
1 file changed, 492 insertions(+), 87 deletions(-)
diff
On 2019/3/15 11:07, Finn Thain wrote:
Does it makes sense to list every typo that is simply a transposition of
characters or a character omitted? This file will become very large very
quickly if we do that.
We are consistent in one thing: typo hurt eyes.
Those typos are exactly generated from
If lbr_desc->event is successfully created, the intel_pmu_create_
guest_lbr_event() will return 0, otherwise it will return -ENOENT,
and then jump to LBR msrs dummy handling.
Fixes: 1b5ac3226a1a ("KVM: vmx/pmu: Pass-through LBR msrs when the guest LBR
event is ACTIVE")
Signed-of
When the processor that support model-specific LBR generates a debug
breakpoint event, it automatically clears the LBR flag. This action
does not clear previously stored LBR stack MSRs. (Intel SDM 17.4.2)
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/vmx.c | 5 +
1 file changed, 5 insertions
Hi Peter,
Would you help pick up this patch so that we can enable guest Arch LBR?
---
thx,likexu
On 2021/2/3 15:03, Like Xu wrote:
If the platform supports LBR_INFO register, the x86_pmu.lbr_info will
be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO
i
Before KVM exposes guest LBR_FMT perf capabilities, it needs to check
whether VMCS has GUEST_IA32_DEBUGCTL guest status field and vmx switch
support on IA32_DEBUGCTL MSR (including VM_EXIT_SAVE_DEBUG_CONTROLS
and VM_ENTRY_LOAD_DEBUG_CONTROLS). It helps nested LBR enablement.
Signed-off-by: Like
_x
to hold metadata for the operation, including mispredict, TSX, and
elapsed cycle time information.
Cc: Kan Liang
Cc: Peter Zijlstra (Intel)
Signed-off-by: Like Xu
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b
age;
Previous:
https://lore.kernel.org/kvm/20200731074402.8879-1-like...@linux.intel.com/
Like Xu (4):
KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR
KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR
KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field
KVM: x86: Exp
a software write to MSR_ARCH_LBR_DEPTH, all LBR entries are reset
to 0. Emulate the reset behavior by introducing lbr_desc->arch_lbr_reset
and sync it to the host MSR_ARCH_LBR_DEPTH msr when the guest LBR
event is ACTIVE and the LBR records msrs are pass-through to the guest.
Signed-off-by: L
LBR usage and the guest value of MSR_ARCH_LBR_CTL is
written to this field on all VM exits.
Signed-off-by: Like Xu
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/vmx/pmu_intel.c | 14 ++
arch/x86/kvm/vmx/vmx.c | 7 +++
3 files changed, 23 insertions(+)
diff --git
X86_FEATURE_ARCH_LBR
to enable guest LBR, which is equivalent to the legacy LBR_FMT setting.
The Arch LBR feature could bypass the host/guest x86_model check and
the records msrs can still be pass-through to guest as usual and work
like the legacy LBR.
Signed-off-by: Like Xu
---
arch/x86/include/
purposes once IA32_XSS [bit 15] is set.
XSAVE support for Arch LBRs is enumerated in CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Like Xu
---
arch/x86/kvm/cpuid.c | 23 +++
arch/x86/kvm/vmx/vmx.c | 2 ++
arch/x86/kvm/x86.c | 10 +-
3 files changed, 34 insertions(+), 1
To make code responsibilities clear, we may resue and invoke the
vmx_set_intercept_for_msr() in other vmx-specific files (e.g. pmu_intel.c),
so expose it to passthrough LBR msrs later.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/vmx.c | 2 +-
arch/x86/kvm/vmx/vmx.h | 2
4.87% br_instr br_instr [.] cmp_end
[.] lfsr_cond 6
4.70% br_instr br_instr [.] cmp_end
[.] lfsr_cond 5
Conclusion: the profiling results on the gue
new value is kept, the default initialization
path is moved to intel_pmu_init().
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/pmu_intel.c | 5 ++---
arch/x86/kvm/vmx/vmx.c | 5 +
arch/x86/kvm/x86.c | 2 +-
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/x86
: Like Xu
---
arch/x86/kvm/vmx/capabilities.h | 1 +
arch/x86/kvm/vmx/pmu_intel.c| 17 +
arch/x86/kvm/vmx/vmx.c | 7 +++
arch/x86/kvm/vmx/vmx.h | 11 +++
4 files changed, 36 insertions(+)
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm
DEBUGCTLMSR_LBR
based on per-guest LBR setting.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/capabilities.h | 7 ++-
arch/x86/kvm/vmx/pmu_intel.c| 7 +++
arch/x86/kvm/vmx/vmx.c | 28 +---
arch/x86/kvm/vmx/vmx.h | 1 +
4 files changed, 31
released when the vPMU is reset but soon,
the lazy release mechanism would be applied to this event like a vPMC.
Suggested-by: Andi Kleen
Co-developed-by: Wei Wang
Signed-off-by: Wei Wang
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 63
LBR to record
hypervisor on the host side.
Suggested-by: Andi Kleen
Co-developed-by: Wei Wang
Signed-off-by: Wei Wang
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 127 ++-
arch/x86/kvm/vmx/vmx.c | 10 +++
arch/x86/kvm
LBR event as a bland event of a vPMC counter and release it
as usual. Also, the pass-through state of LBR records msrs is cancelled.
Signed-off-by: Like Xu
---
arch/x86/kvm/pmu.c | 3 +++
arch/x86/kvm/pmu.h | 1 +
arch/x86/kvm/vmx/pmu_intel.c | 21 -
3
Hi Paolo,
On 2021/1/27 14:04, Like Xu wrote:
On 2021/1/26 17:42, Paolo Bonzini wrote:
On 08/01/21 02:36, Like Xu wrote:
@@ -401,6 +398,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu)
pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
pmu->fixed_coun
When the LBR records msrs has already been pass-through, there is no
need to call vmx_update_intercept_for_lbr_msrs() again and again, and
vice versa.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 13 +
arch/x86/kvm/vmx/vmx.h | 3 +++
2
()) and the vcpu model is compatible
with the host one.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/capabilities.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index 57b940c613ab..c49f3ee8eca8 100644
LBR event as a bland event of a vPMC counter and release it
as usual. Also, the pass-through state of LBR records msrs is cancelled.
Signed-off-by: Like Xu
---
arch/x86/kvm/pmu.c | 3 +++
arch/x86/kvm/pmu.h | 1 +
arch/x86/kvm/vmx/pmu_intel.c | 21 -
3
This test will check the effect of various CPUID settings on the
MSR_IA32_PERF_CAPABILITIES MSR, check that whatever user space writes
with KVM_SET_MSR is _not_ modified from the guest and can be retrieved
with KVM_GET_MSR, and check that invalid LBR formats are rejected.
Signed-off-by: Like Xu
lso, guest needs to re-enable IA32_DEBUGCTL.LBR
to resume recording branches.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/pmu.c | 5 -
arch/x86/kvm/pmu.h | 1 +
arch/x86/kvm/vmx/capabilities.h | 4 +++-
arch/x86/kvm/vmx/pmu_intel
lso, guest needs to re-enable IA32_DEBUGCTL.LBR
to resume recording branches.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/pmu.c | 5 -
arch/x86/kvm/pmu.h | 1 +
arch/x86/kvm/vmx/capabilities.h | 4 +++-
arch/x86/kvm/vmx/pmu_intel
This test will check the effect of various CPUID settings on the
MSR_IA32_PERF_CAPABILITIES MSR, check that whatever user space writes
with KVM_SET_MSR is _not_ modified from the guest and can be retrieved
with KVM_GET_MSR, and check that invalid LBR formats are rejected.
Signed-off-by: Like Xu
()) and the vcpu model is compatible
with the host one.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/capabilities.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index 57b940c613ab..c49f3ee8eca8 100644
When the LBR records msrs has already been pass-through, there is no
need to call vmx_update_intercept_for_lbr_msrs() again and again, and
vice versa.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 13 +
arch/x86/kvm/vmx/vmx.h | 3 +++
2
Hi Peter,
Thanks for the clear attitude and code refinement.
On 2020/5/18 20:02, Peter Zijlstra wrote:
On Thu, May 14, 2020 at 04:30:48PM +0800, Like Xu wrote:
@@ -544,7 +562,12 @@ void intel_pmu_lbr_enable_all(bool pmi)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_ev
[2] https://lore.kernel.org/kvm/20200726153229.27149-1-like...@linux.intel.com/
Please check more details in each commit and feel free to comment.
Like Xu (6):
KVM: vmx/pmu: Add VMCS field check before exposing LBR_FMT
perf/x86/lbr: Unify LBR_INFO registers exposure check condition
KVM: vm
X86_FEATURE_ARCH_LBR
to enable guest LBR, which is equivalent to the legacy LBR_FMT setting.
The Arch LBR feature could bypass the host/guest x86_model check and
the records msrs can still be pass-through to guest as usual and work
like the legacy LBR.
Signed-off-by: Like Xu
---
arch/x86/include/
purposes once IA32_XSS [bit 15] is set.
XSAVE support for Arch LBRs is enumerated in CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Like Xu
---
arch/x86/kvm/cpuid.c | 19 +++
arch/x86/kvm/vmx/vmx.c | 2 ++
arch/x86/kvm/x86.c | 6 ++
3 files changed, 27 insertions(+)
diff
If guest LBR_FMT is exposed on KVM, KVM needs to have guest state
field GUEST_IA32_DEBUGCTL and MSR_IA32_DEBUGCTLMSR vmx switch support.
Fixes: f93d622139de ("KVM: vmx/pmu: Expose LBR_FMT in the
MSR_IA32_PERF_CAPABILITIES")
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/capabili
LBR usage and the guest value of MSR_ARCH_LBR_CTL is
written to this field on all VM exits.
Signed-off-by: Like Xu
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/vmx/pmu_intel.c | 13 +
arch/x86/kvm/vmx/vmx.c | 8
3 files changed, 23 insertions(+)
diff --git
a software write to MSR_ARCH_LBR_DEPTH, all LBR entries are reset
to 0. Emulate the reset behavior by introducing lbr_desc->arch_lbr_reset
and sync it to the host MSR_ARCH_LBR_DEPTH msr when the guest LBR
event is ACTIVE and the LBR records msrs are pass-through to the guest.
Signed-off-by: L
stead of
relying solely on 'lbr_format == LBR_FORMAT_INFO' check.
Cc: Kan Liang
Cc: Peter Zijlstra (Intel)
Signed-off-by: Like Xu
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/in
in the KVM context.
Message-ID: <20200811084548.gw3...@worktop.programming.kicks-ass.net>
Signed-off-by: Like Xu
---
arch/x86/kvm/pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 67741d2a0308..6a30763a10d7 100644
--- a/arch/x86/kvm/pmu.
to
fix that.
2. On guest, exclude_guest = 0 and exclude_hv = 0.
For exclude_hv = 0, it looks like a bug but x86 doesn't use exclude_hv. But
yes, we should fix that.
CC Like Xu .
Thanks
Jin Yao
Please hold the horse and allow this possibility.
Some authorized perf users on the host may
only want to count (KVM) guest user space events.
Thanks,
Like Xu
To keep perf semantics consistent and clear, this patch sets
exclude_guest for user-space counting.
Applied, and also added this,
Hi Yao,
On 2020/8/13 11:11, Jin, Yao wrote:
Hi Like,
On 8/12/2020 9:02 PM, Like Xu wrote:
On 2020/8/12 20:15, Arnaldo Carvalho de Melo wrote:
Em Wed, Aug 12, 2020 at 02:59:53PM +0800, Jin Yao escreveu:
Currently if we run 'perf record -e cycles:u', exclude_guest is 0.
But it do
On 2020/8/13 15:08, Jin, Yao wrote:
On 8/13/2020 2:57 PM, Like Xu wrote:
Hi Yao,
On 2020/8/13 11:11, Jin, Yao wrote:
Hi Like,
On 8/12/2020 9:02 PM, Like Xu wrote:
On 2020/8/12 20:15, Arnaldo Carvalho de Melo wrote:
Em Wed, Aug 12, 2020 at 02:59:53PM +0800, Jin Yao escreveu:
Currently if
't assume the guest counter 0 and 1 are not used for this
PEBS task at the same time. And what's more, KVM can't aware the guest
read/write to the DS AREA because it just a general memory for guest.
What is your opinion or do you have a better proposal?
Do we have any update or clear a
Anyway, I think that with what we have, your patch makes sense, having a
way to, without using 'perf kvm' still be able to sample the guest can
be done on top. of this.
Xu, can we get your Reviewed-by if this addresses your concerns?
My concern is about do not break the perf kvm usa
a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Like-Xu/x86-perf-Use-static_call-for-x86_pmu-guest_get_msrs/20210118-153219
base: https://git.kernel.org/pub/scm/li
[.] lfsr_cond 6
4.70% br_instr br_instr [.] cmp_end
[.] lfsr_cond 5
Conclusion: the profiling results on the guest are similar to that on the host.
Like X
To make code responsibilities clear, we may resue and invoke the
vmx_set_intercept_for_msr() in other vmx-specific files (e.g. pmu_intel.c),
so expose it to passthrough LBR msrs later.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/vmx.c | 2 +-
arch/x86/kvm/vmx/vmx.h | 2
SVM already has specific handlers of MSR_IA32_DEBUGCTLMSR in the
svm_get/set_msr, so the x86 common part can be safely moved to VMX.
Add vmx_supported_debugctl() to refactor the throwing logic of #GP.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/capabilities.h | 5
records would be cleared.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/capabilities.h | 1 +
arch/x86/kvm/vmx/pmu_intel.c| 40 +
arch/x86/kvm/vmx/vmx.h | 12 ++
3 files changed, 53 insertions(+)
diff --git a/arch/x86
the adjustment in intel_pmu_refresh() will be triggered. To ensure the
sustainability of the new value, the default initialization path is
moved to intel_pmu_init().
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 6 +++---
arch/x86/kvm/vmx/vmx.c | 5 +
a
-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/capabilities.h | 7 +++-
arch/x86/kvm/vmx/pmu_intel.c| 61 +
arch/x86/kvm/vmx/vmx.c | 31 +++--
arch/x86/kvm/vmx/vmx.h | 10 ++
4 files changed, 97 insertions(+), 12
LBR to record
hypervisor on the host side.
Suggested-by: Andi Kleen
Co-developed-by: Wei Wang
Signed-off-by: Wei Wang
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 127 ++-
arch/x86/kvm/vmx/vmx.c | 10 +++
arch/x86/kvm
LBR event as a bland event of a vPMC counter and release it
as usual. Also, the pass-through state of LBR records msrs is cancelled.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/pmu.c | 7 +++
arch/x86/kvm/pmu.h | 4
arch/x86/kvm/vmx/pmu
When the LBR records msrs has already been pass-through, there is no
need to call vmx_update_intercept_for_lbr_msrs() again and again, and
vice versa.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 13 +
arch/x86/kvm/vmx/vmx.h | 3 +++
2
lso, guest needs to re-enable IA32_DEBUGCTL.LBR
to resume recording branches.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/pmu.c | 5 -
arch/x86/kvm/pmu.h | 1 +
arch/x86/kvm/vmx/capabilities.h | 4 +++-
arch/x86/kvm/vmx/pmu_intel
Userspace could enable guest LBR feature when the exactly supported
LBR format value is initialized to the MSR_IA32_PERF_CAPABILITIES
and the LBR is also compatible with vPMU version and host cpu model.
Signed-off-by: Like Xu
Reviewed-by: Andi Kleen
---
arch/x86/kvm/vmx/capabilities.h | 9
Ping ?
On 2020/12/30 16:19, Like Xu wrote:
The HW_REF_CPU_CYCLES event on the fixed counter 2 is pseudo-encoded as
0x0300 in the intel_perfmon_event_map[]. Correct its usage.
Fixes: 62079d8a4312 ("KVM: PMU: add proper support for fixed counter 2")
Signed-off-by: Like Xu
---
arch/x
Ping ?
On 2020/12/29 15:11, Like Xu wrote:
Since we know vPMU will not work properly when the guest bit_width(s) of
the [gp|fixed] counters are greater than the host ones, so we can setup a
smaller left shift value and refresh the guest pmu cpuid entry, thus fixing
the following UBSAN shift-out
136a4cc6ba...@syzkaller.appspotmail.com
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/pmu_intel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index a886a47daebd..a86a1690e75c 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
The HW_REF_CPU_CYCLES event on the fixed counter 2 is pseudo-encoded as
0x0300 in the intel_perfmon_event_map[]. Correct its usage.
Fixes: 62079d8a4312 ("KVM: PMU: add proper support for fixed counter 2")
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/pmu_intel.c | 2 +-
1 file
On 2021/3/24 5:38, Peter Zijlstra wrote:
On Mon, Mar 22, 2021 at 02:06:32PM +0800, Like Xu wrote:
If the platform supports LBR_INFO register, the x86_pmu.lbr_info will
be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO
You mean: intel_pmu_lbr_*init*(). '?&#x
On 2021/3/24 5:49, Peter Zijlstra wrote:
On Mon, Mar 22, 2021 at 02:06:34PM +0800, Like Xu wrote:
The Architecture LBR does not have MSR_LBR_TOS (0x01c9). KVM will
generate #GP for this MSR access, thereby preventing the initialization
of the guest LBR.
Fixes: 47125db27e47 ("perf/x86/
Hi Namhyung,
On 2021/3/24 9:32, Namhyung Kim wrote:
Hello,
On Mon, Mar 22, 2021 at 3:14 PM Like Xu wrote:
+void reserve_lbr_buffers(struct perf_event *event)
+{
+ struct kmem_cache *kmem_cache = x86_get_pmu()->task_ctx_cache;
+ struct cpu_hw_events *cpuc;
+ int
On 2021/3/24 12:04, Namhyung Kim wrote:
On Wed, Mar 24, 2021 at 12:47 PM Like Xu wrote:
Hi Namhyung,
On 2021/3/24 9:32, Namhyung Kim wrote:
Hello,
On Mon, Mar 22, 2021 at 3:14 PM Like Xu wrote:
+void reserve_lbr_buffers(struct perf_event *event)
+{
+ struct kmem_cache *kmem_cache
Starting from v5.12, KVM reports guest LBR and extra_regs
support when the host has relevant support.
Cc: Peter Zijlstra
Reviewed-by: Kan Liang
Signed-off-by: Like Xu
---
arch/x86/events/intel/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel
_x
to hold metadata for the operation, including mispredict, TSX, and
elapsed cycle time information.
Cc: Peter Zijlstra
Reviewed-by: Kan Liang
Signed-off-by: Like Xu
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b
pu_reset();
- Refine intel_pmu_lbr_is_compatible();
- Simplify lbr_enable check and its usage;
- Add Arch LBR msrs to is_valid_passthrough_msr();
- Make XSAVE support for Arch LBR as a separate patch;
Previous:
https://lore.kernel.org/kvm/20210203135714.318356-1-like...@linux.intel.com/
Like Xu
The Architecture LBR does not have MSR_LBR_TOS (0x01c9). KVM will
generate #GP for this MSR access, thereby preventing the initialization
of the guest LBR.
Cc: Peter Zijlstra
Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
Signed-off-by: Like Xu
Reviewed-by:
x50
[ 54.317698] do_syscall_64+0x33/0x40
[ 54.318390] entry_SYSCALL_64_after_hwframe+0x44/0xa9
Fix it by allocating this part of memory with GFP_ATOMIC mask.
Cc: Peter Zijlstra
Fixes: c085fb8774 ("perf/x86/intel/lbr: Support XSAVES for arch LBR read")
Suggested-by: Kan Liang
Signed
t Arch LBR, MSR_IA32_DEBUGCTLMSR[bit 0] has no
meaning. It can be written to 0 or 1, but reads will always return 0. On
the vmx_vcpu_reset(), the IA32_LBR_CTL will be cleared to 0.
Signed-off-by: Like Xu
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/vmx/pmu_intel.c | 27 ++-
leakage of host records via XSAVES. In this
case, the guest results may be inaccurate as the legacy LBR.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/pmu_intel.c | 2 ++
arch/x86/kvm/vmx/vmx.c | 2 ++
arch/x86/kvm/x86.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch
usual and work like a model-specific LBR.
KVM is consistent with the host and does not support the LER entry.
Signed-off-by: Like Xu
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/kvm/vmx/capabilities.h | 25 +
arch/x86/kvm/vmx/pmu_intel.c| 27 +++
guest
taken in the LBR entries for guest to read.
Signed-off-by: Like Xu
---
x86/pmu_lbr.c | 62 ++-
1 file changed, 52 insertions(+), 10 deletions(-)
diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c
index 3bd9e9f..588aec8 100644
--- a/x86/pmu_lbr.c
+++
en the Arch LBR
records MSRs are pass-through to the guest.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/pmu_intel.c | 43
arch/x86/kvm/vmx/vmx.h | 3 +++
2 files changed, 46 insertions(+)
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kv
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, then KVM supports Arch
LBRs and CPUID leaf 01CH indicates details of the Arch LBRs capabilities.
Currently, KVM only supports the current host LBR depth for guests,
which is also the maximum supported depth on the host.
Signed-off-by: Like Xu
On 2021/3/4 2:03, Sean Christopherson wrote:
On Wed, Mar 03, 2021, Like Xu wrote:
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 034708a3df20..ec4593e0ee6d 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7268,6 +7268,8 @@ static __init void
uggested-by: Kan Liang
Signed-off-by: Like Xu
---
arch/x86/events/core.c | 8 +---
arch/x86/events/intel/bts.c | 2 +-
arch/x86/events/intel/lbr.c | 22 --
arch/x86/events/perf_event.h | 8 +++-
4 files changed, 29 insertions(+), 11 deletions(-)
diff --git a
The ARCH_LBR_CTL_MASK will be reused for Arch LBR emulation in the KVM.
Signed-off-by: Like Xu
---
arch/x86/events/intel/lbr.c | 2 --
arch/x86/include/asm/msr-index.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel
more details in each commit and feel free to comment.
Like Xu (5):
perf/x86/intel: Fix the comment about guest LBR support on KVM
perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region
perf/x86/lbr: S
Starting from v5.12, KVM reports guest LBR and extra_regs support
when the host has relevant support. Just delete this part of the
comment and fix a typo incidentally.
Signed-off-by: Like Xu
Reviewed-by: Kan Liang
Reviewed-by: Andi Kleen
---
arch/x86/events/intel/core.c | 3 +--
1 file
The Architecture LBR does not have MSR_LBR_TOS (0x01c9). KVM will
generate #GP for this MSR access, thereby preventing the initialization
of the guest LBR.
Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
Signed-off-by: Like Xu
Reviewed-by: Kan Liang
Reviewe
_x
to hold metadata for the operation, including mispredict, TSX, and
elapsed cycle time information.
Signed-off-by: Like Xu
Reviewed-by: Kan Liang
Reviewed-by: Andi Kleen
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lb
/20210322060635.821531-1-like...@linux.intel.com/
v4->v5 Changelog:
- Add "Tested-by: Kan Liang"
- Make the commit message simpler
- Make check_msr() to ignore msr==0
- Use kmem_cache_alloc_node() [Namhyung]
Like Xu (5):
perf/x86/intel: Fix the comment about guest LBR support on KVM
Starting from v5.12, KVM reports guest LBR and extra_regs support
when the host has relevant support. Just delete this part of the
comment and fix a typo incidentally.
Signed-off-by: Like Xu
Reviewed-by: Kan Liang
Reviewed-by: Andi Kleen
---
arch/x86/events/intel/core.c | 3 +--
1 file
The ARCH_LBR_CTL_MASK will be reused for LBR emulation in the KVM.
Signed-off-by: Like Xu
---
arch/x86/events/intel/lbr.c | 2 --
arch/x86/include/asm/msr-index.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
The x86_pmu.lbr_info is 0 unless explicitly initialized, so there's
no point checking x86_pmu.intel_cap.lbr_format.
Signed-off-by: Like Xu
Reviewed-by: Kan Liang
Reviewed-by: Andi Kleen
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a
ed for each cpu like the legacy ds_buffer.
Fixes: c085fb8774 ("perf/x86/intel/lbr: Support XSAVES for arch LBR read")
Suggested-by: Kan Liang
Tested-by: Kan Liang
Signed-off-by: Like Xu
---
arch/x86/events/core.c | 8 +---
arch/x86/events/intel/bts.c | 2 +-
arc
hitectural LBR")
Signed-off-by: Like Xu
Reviewed-by: Kan Liang
---
arch/x86/events/intel/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 382dd3994463..564c9851dd34 100644
--- a/arch/x86/even
not set;
- Make vmx_icl_pebs_cpu specific for PEBS-PDIR emulation;
- Fix a bug for fixed_ctr_ctrl_mask;
- Add two minor refactoring patches for reuse;
Like Xu (16):
perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers
perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest
perf/x86
d-off-by: Like Xu
---
arch/x86/events/core.c| 4 ++--
arch/x86/events/intel/core.c | 4 ++--
arch/x86/events/perf_event.h | 2 +-
arch/x86/include/asm/perf_event.h | 4 ++--
arch/x86/kvm/vmx/vmx.c| 3 ++-
5 files changed, 9 insertions(+), 8 deletions(-)
diff --
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