speed modes of operation (10/100/1000 Mb/s).
MDIO interface is used to set operating speed of Ethernet MAC.
Signed-off-by: Kedareswara rao Appana
---
--> Tried to include this Coverter support in the
PHY layer but it won't fit into the PHY framework as the
coverter won't have vaild
Device-tree binding documentation for xilinx gmiitorgmii converter.
Signed-off-by: Kedareswara rao Appana
---
Changes for v4:
--> Modified compatible as suggested by Rob.
--> Removed underscores from the converter node name as suggested by Rob.
Changes for v3:
--> None.
Changes for v2
Operation by configuring the converter register through mdio write.
MDIO interface is used to set operating speed of Ethernet MAC.
Signed-off-by: Kedareswara rao Appana
---
Thanks a lot Andrew for your inputs.
Changes for v4:
--> Updated phydev speed for all 3 speeds as suggested by zhuyj.
Chan
Microblaze platforms.
Signed-off-by: Kedareswara rao Appana
---
Changes in v6:
- Used the readl_poll_timeout instead of do while loops in the driver
- Improved the SG list handling by chaining the bds.
- Removed the unnecessary xilinx_cdma_channel_set_config API the properties
in this API is not being
Device-tree binding documentation of Xilinx Central DMA Engine.
Signed-off-by: Kedareswara rao Appana
---
Changes in v6:
- None.
Changes in v5:
- None.
Changes in v4:
- None.
Changes in v3:
- Used proper alignment for all the properties.
Changes in v2:
- Change property 'xlnx,data-widt
Instead of enabling/disabling clocks at several locations in the driver,
Use the runtime_pm framework. This consolidates the actions for runtime PM
In the appropriate callbacks and makes the driver more readable and mantainable.
Signed-off-by: Kedareswara rao Appana
---
Sorry for the long delay
register write fixes this issue
Instead of barriers using writel also fixed this issue.
Signed-off-by: Kedareswara rao Appana
---
drivers/net/can/xilinx_can.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index
Simply resetting the peripheral on bus off condition is not enough,
Because we also need to re-initialize the whole device.
This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana
---
drivers/net/can/xilinx_can.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
Instead of enabling/disabling clocks at several locations in the driver,
Use the runtime_pm framework. This consolidates the actions for runtime PM
In the appropriate callbacks and makes the driver more readable and mantainable.
Signed-off-by: Kedareswara rao Appana
---
Changes for v7
Instead of enabling/disabling clocks at several locations in the driver,
Use the runtime_pm framework. This consolidates the actions for runtime PM
In the appropriate callbacks and makes the driver more readable and mantainable.
Signed-off-by: Kedareswara rao Appana
---
Changes for v8
Instead of enabling/disabling clocks at several locations in the driver,
use the runtime_pm framework. This consolidates the actions for
runtime PM in the appropriate callbacks and makes the driver more
readable and mantainable.
Signed-off-by: Soren Brinkmann
Signed-off-by: Kedareswara rao
This property is no longer used in the code yet the code looks for it in the
device tree.
It does not cause an error if it's not in the tree.
Signed-off-by: Kedareswara rao Appana
---
drivers/net/ethernet/xilinx/xilinx_axienet.h |2 --
drivers/net/ethernet/xilinx/xilinx_axienet_m
Instead of enabling/disabling clocks at several locations in the driver,
Use the runtime_pm framework. This consolidates the actions for runtime PM
In the appropriate callbacks and makes the driver more readable and mantainable.
Signed-off-by: Soren Brinkmann
Signed-off-by: Kedareswara rao
drivers/dma/xilinx/xilinx_vdma.c:26:0:
include/linux/dmapool.h:17:18: note: expected 'struct device *' but argument is
of type 'struct device *'
struct dma_pool *dma_pool_create(const char *name, struct device *dev, .
Signed-off-by: Kedareswara rao Appana
---
This patch is r
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
The deivce tree
Microblaze platforms.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the commit
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Changes in v5:
- updated license in the driver as suggested by Paul.
- Corrected return value in is_idle
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc4 kernel.
Changes for v4:
- Added check for the tx fifo full interrupt condition in
Tx interrupt
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc5 kernel.
Changes for v5:
- Updated the driver with the review comments.
- Remove the check for the tx
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS IP and
Soft IP AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc2 kernel.
Changes for v2:
- Updated with the review comments.
- Removed unnecessary debug prints
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
Changes for v7:
- Updated the driver with review comments.
- Moved the driver bindings doc as a separte patch.
Changes for v6:
- Updated
Add xilinx CAN bindings documentation.
Signed-off-by: Kedareswara rao Appana
---
.../devicetree/bindings/net/can/xilinx_can.txt | 44
1 files changed, 44 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/can/xilinx_can.txt
diff
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc3 kernel.
Changes for v3:
- Updated the driver with the review comments
- Modified the transmit logic
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc8 kernel
Chnages for v6:
- Updated the driver with review comments.
- Used the clock names specified
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS and Soft IP
AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
Changes for v8:
- call can_led_event only once in xcan_tx_interrupt();
- proceed with error handling if alloc_can_err_skb() failed in
Add xilinx CAN bindings documentation.
Signed-off-by: Kedareswara rao Appana
---
Changes for v8:
- None.
Changes for v7:
- Split the devicetree bindings doc as a seperate patch
---
.../devicetree/bindings/net/can/xilinx_can.txt | 44
1 files changed, 44 insertions
Add xilinx CAN bindings documentation.
Signed-off-by: Kedareswara rao Appana
---
Changes for v8:
- None.
Changes for v7:
- Split the devicetree bindings doc as a seperate patch
---
.../devicetree/bindings/net/can/xilinx_can.txt | 44
1 files changed, 44 insertions
This patch adds xilinx CAN controller support.
This driver supports both ZYNQ CANPS IP and
Soft IP AXI CAN controller.
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the 3.14 rc1 kernel.
---
.../devicetree/bindings/net/can/xilinx_can.txt | 43 +
drivers/net/can/Kconfig
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
The deivce tree
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
The deivce tree
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory and
memory to I/O buffer transfers.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes in v6:
- Removed unnecessary axcache properties
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes in v6:
- Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
from the binding doc as it allow
This patch series adds basic clock support for AXI DMAS
This patch series is created on top of the dma-next branch.
Kedareswara rao Appana (3):
dmaengine: vdma: Add config structure to differentiate dmas
Documentation: DT: vdma: Add clock support for dmas
dmaengine: vdma: Add clock support
Added basic clock support for axi dma's.
The clocks are requested at probe and released at remove.
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 226 ++-
1 file changed, 224 insertions(
This patch updates the binding doc with clock description
for AXI DMA's.
Acked-by: Sören Brinkmann
Signed-off-by: Kedareswara rao Appana
---
.../devicetree/bindings/dma/xilinx/xilinx_vdma.txt| 15 +++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devic
This patch adds config structure in the driver to differentiate
AXI DMA's and to add more features(clock support etc..) to these DMA's.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 83
1 file changed, 51 inserti
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes in v8:
- Removed all the software runtime configuration parameters
from the binding doc as suggested by the
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and memory to I/O buffer transfers.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes for v8:
- Derive the software runtime configuration
address.
So we need to program two registers at a time.
This patch adds the 64 bit addressing support for the axidma
IP in the driver.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
--> New patch.
drivers/dma/xilinx/xilinx_vdma.c | 79 ++--
1 f
program two registers at a time.
This patch adds the 64 bit addressing support to the axicdma
IP in the driver.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
--> New patch.
drivers/dma/xilinx/xilinx_vdma.c | 44 +---
1 file changed, 32 inserti
This patch series does the following
---> Add support for cyclic DMA mode for the AXI DMA IP.
---> use dma_poll_zalloc instead of dma_pool_alloc.
---> Add 64-bit addressing support for AXI DMA IP.
---> Add 64-bit addressing support for AXI CDMA IP.
Kedareswara rao Appana (4):
dma
dma_pool_zalloc combines dma_pool_alloc and memset 0
this patch updates the driver to use dma_pool_zalloc.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
--> New patch.
drivers/dma/xilinx/xilinx_vdma.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/driv
This patch adds support for AXI DMA cyclic dma mode.
In cyclic mode, DMA fetches and processes the same
BDs without interruption. The DMA continues to fetch and process
until it is stopped or reset.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
---> Removed unnecessary memset() c
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory and
memory to I/O buffer transfers.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes for v7:
- Fixed kbuild compilation warnings
Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes in v7:
- None.
Changes in v6:
- Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
from the
This patch updates the binding doc with clock description
for AXI DMA's.
Acked-by: Rob Herring
Acked-by: Sören Brinkmann
Signed-off-by: Kedareswara rao Appana
---
Changes for v5:
---> None.
Changes for v4:
---> None.
Changes for v3:
---> Added clock support for all the AXI DMA&
Added basic clock support for axi dma's.
The clocks are requested at probe and released at remove.
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Kedareswara rao Appana
---
Changes for v5:
---> None.
Changes for v4:
---> Documented struct members as suggested by Soren.
---> Fixed
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and memory to I/O buffer transfers.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changes for v9:
- Derive the include sg software runtime
This patch series adds basic clock support for AXI DMAS
This patch series is created on top of the dma-next branch.
Kedareswara rao Appana (3):
dmaengine: vdma: Add config structure to differentiate dmas
Documentation: DT: vdma: Add clock support for dmas
dmaengine: vdma: Add clock support
Device-tree binding documentation for Xilinx zynqmp dma engine
used in Zynq UltraScale+ MPSoC.
Signed-off-by: Punnaiah Choudary Kalluri
Signed-off-by: Kedareswara rao Appana
---
Changs in v9:
- Removed include sg runtime configuration parameter
from the binding doc as suggested by Lars
This patch adds config structure in the driver to differentiate
AXI DMA's and to add more features(clock support etc..) to these DMA's.
Signed-off-by: Kedareswara rao Appana
---
Changes for v5:
---> Rename dma_config struct to xilinx_dma_config
as suggested by vinod.
C
This patch adds support for AXI DMA cyclic dma mode.
In cyclic mode, DMA fetches and processes the same
BDs without interruption. The DMA continues to fetch and process
until it is stopped or reset.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 179
ng the frame count register.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 193 ++-
1 file changed, 91 insertions(+), 102 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c
index 6f4b501..a
This patch simplifies the spin lock handling in the driver
by moving locking out of xilinx_dma_start_transfer() API
and xilinx_dma_update_completed_cookie() API.
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> Updated commit message as suggested by vinod.
---> Added descript
prevents the user to prepare multiple trasactions at same time as
we are overwrite with the allocated_desc.
The best utilization of HW SG engine would happen if we collate the pending
list when we start dma this patch updates the same.
Signed-off-by: Kedareswara rao Appana
---
Changes for v3
It is sometimes necessary to poll a memory-mapped register until its
value satisfies some condition use convenience macros
that do this instead of do while loop's.
This patch updates the same in the driver.
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> removed patch d
rao Appana
---
Changes for v3:
---> None.
Changes for v2:
---> splitted the changes into multiple patches.
drivers/dma/xilinx/xilinx_vdma.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c
index ce330d4..70b2b32
When accessing the priv structure use container_of instead of dev_get_drvdata.
Enable the clocks in the suspend before accessing the registers of the CAN.
Signed-off-by: Kedareswara rao Appana
---
drivers/net/can/xilinx_can.c | 20 ++--
1 files changed, 18 insertions(+), 2
The drvdata in the suspend/resume is of type struct net_device,
not the platform device.Enable the clocks in the suspend before
accessing the registers of the CAN.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
- Removed the struct platform_device* from suspend/resume
as suggest
Instead of enabling/disabling clocks at several locations in the driver,
use the runtime_pm framework. This consolidates the actions for
runtime PM in the appropriate callbacks and makes the driver more
readable and mantainable.
Signed-off-by: Soren Brinkmann
Signed-off-by: Kedareswara rao
Microblaze platforms.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the commit
Merge tag 'nfs-for-4.1-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
Changes in v4:
- used GFP_NOWAIT instead of GFP_KERNEL during the desc
Device-tree binding documentation of Xilinx Central DMA Engine.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on the commit
Merge tag 'nfs-for-4.1-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
Changes in v4:
- None.
Cha
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
The deivce tree
drivers/dma/xilinx/xilinx_vdma.c:26:0:
include/linux/dmapool.h:17:18: note: expected 'struct device *' but argument is
of type 'struct device *'
struct dma_pool *dma_pool_create(const char *name, struct device *dev, .
Signed-off-by: Kedareswara rao Appana
---
- This patch
Microblaze platforms.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on top of dma: xilinx-dma: move header file
to common location.
Changes in v3:
- Check for CDMA idle condition before changing the configuration.
- Modified the xilinx_dma.h header file
Microblaze platforms.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is rebased on top of dma: xilinx-dma: move header file
to common location.
Changes in v3:
- Check for CDMA idle condition before changing the configuration.
- Modified the xilinx_dma.h header file
This patch moves the xilinx_dma.h header file
to the include/linux/dma.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 2 +-
include/linux/{amba => dma}/xilinx_dma.h | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename include/linux/{amba =&g
Device-tree binding documentation of Xilinx Central DMA Engine.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
Changes in v3:
- Used proper alignment for all the properties.
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is
This patch updates the binding doc with clock description
for vdma.
Signed-off-by: Kedareswara rao Appana
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
b
Added basic clock support. The clocks are requested at probe
and released at remove.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 56
1 file changed, 56 insertions(+)
diff --git a/drivers/dma/xilinx/xilinx_vdma.c b
Added basic clock support. The clocks are requested at probe
and released at remove.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
--> None.
drivers/dma/xilinx/xilinx_vdma.c | 56
1 file changed, 56 insertions(+)
diff --git a/drivers/
This patch updates the binding doc with clock description
for vdma.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
--> Listed down all the clocks supported by the h/w
as suggested by the Datta.
--> Used IP clock names instead of shortcut clock names.
Documentation/devi
Added basic clock support for axi dma's.
The clocks are requested at probe and released at remove.
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> Added clock support for all the AXI DMA's.
---> Fixed clk_unprepare leak duri
This patch updates the binding doc with clock description
for AXI DMA's.
Acked-by: Sören Brinkmann
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> Added clock support for all the AXI DMA's.
Changes for v2:
--> Listed down all the clocks supported by the h/w
This patch series adds basic clock support for AXI DMAS
This patch series is created on top of the
"dmaengine: vdma: AXI DMA's enhancments" patch series.
Kedareswara rao Appana (3):
dmaengine: vdma: Add config structure to differentiate dmas
Documentation: DT: vdma: Add cl
This patch adds config structure in the driver to differentiate
AXI DMA's and to add more features(clock support etc..) to these DMA's.
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> New patch.
drivers/dma/xilinx/xilinx_vdma.c | 81 +-
This patch series adds basic clock support for AXI DMAS
This patch series is created on top of the
"dmaengine: vdma: AXI DMA's enhancments" patch series.
Kedareswara rao Appana (3):
dmaengine: vdma: Add config structure to differentiate dmas
Documentation: DT: vdma: Add clock s
This patch adds config structure in the driver to differentiate
AXI DMA's and to add more features(clock support etc..) to these DMA's.
Signed-off-by: Kedareswara rao Appana
---
Changes for v4:
---> None.
Changes for v3:
---> New patch.
drivers/dma/xilinx/xi
Added basic clock support for axi dma's.
The clocks are requested at probe and released at remove.
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Kedareswara rao Appana
---
Changes for v4:
---> Documented struct members as suggested by Soren.
---> Fixed required clock according to bi
This patch updates the binding doc with clock description
for AXI DMA's.
Acked-by: Sören Brinkmann
Signed-off-by: Kedareswara rao Appana
---
Changes for v4:
---> None.
Changes for v3:
---> Added clock support for all the AXI DMA's.
Changes for v2:
--> Listed down all the cloc
This patch updates the device-tree binding doc for
adding support for AXI DMA.
Signed-off-by: Kedareswara rao Appana
---
.../devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree
This patch updates the device-tree binding doc for
adding support for AXI CDMA.
Signed-off-by: Kedareswara rao Appana
---
.../devicetree/bindings/dma/xilinx/xilinx_vdma.txt| 15 +++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/xilinx
This patch adds support for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 385
This patch adds support for the AXI Central Direct Memory Access (AXI
CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth
Direct Memory Access (DMA) between a memory-mapped source address and a
memory-mapped destination address.
Signed-off-by: Kedareswara rao Appana
AXI DMA support is added to the existing AXI VDMA driver.
The binding doc for AXI DMA should also be updated in the
VDMA device-tree binding doc.
Signed-off-by: Kedareswara rao Appana
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65 --
1 file changed, 65
This patch series does some enhancments to the VDMA driver
which includes
--> Adding support for AXI DMA IP.
--> Adding support for AXI CDMA IP.
--> Fixing checkpatch warnings.
Kedareswara rao Appana (7):
dmaengine: xilinx_vdma: Fix checkpatch.pl warnings
dmaengine: xilinx_vdma: A
This patch adds quirks support in the driver to differentiate differnet IP
cores.
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 36 ++--
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/xilinx
errors = status & XILINX_VDMA_DMASR_ALL_ERR_MASK;
+ vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR,
Signed-off-by: Kedareswara rao Appana
---
drivers/dma/xilinx/xilinx_vdma.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/dri
When VDMA is configured in Non-sg mode
Users can queue descriptors greater than h/w configured frames.
Current driver allows the user to queue descriptors upto h/w configured.
Which is wrong for non-sg mode configuration.
This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.
This patch adds the 64 bit addressing support to the vdma driver.
Signed-off-by: Anurag Kumar Vulisha
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
--> Improved commit message as sugges
This patch renames the xilinx_vdma_ prefix to xilinx_dma
for the API's and masks that will be shared b/w three DMA
IP cores.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
---> New patch as suggested by Laurent Pinchart.
drivers/dma/xilinx/xilinx_vdma
errors = status & XILINX_VDMA_DMASR_ALL_ERR_MASK;
+ vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR,
Acked-by: Laurent Pinchart
Acked-by: Moritz Fischer
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
---> None.
drivers/dma/xilinx/xilinx_vdma.c | 5 +
1 file cha
This patch updates the device-tree binding doc for
adding support for AXI DMA.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
---> Modified commit message as suggested by Vinod.
---> Moved the patch to forward in the series as suggested by vinod.
.../devicetree/bindings/dma/
This patch adds support for the AXI Direct Memory Access (AXI DMA)
core in the existing vdma driver, AXI DMA Core is a
soft Xilinx IP core that provides high-bandwidth
direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Kedareswara rao Appana
---
Changes
This patch series does some enhancments to the VDMA driver
which includes
--> Adding support for AXI DMA IP.
--> Adding support for AXI CDMA IP.
--> Fixing checkpatch warnings.
Kedareswara rao Appana (6):
dmaengine: vdma: Fix checkpatch.pl warnings
dmaengine: vdma: Rename xilinx_vdm
: Kedareswara rao Appana
---
Changes for v2:
---> have differenet structures for h/w desc.
---> Added comments to the relevant sections as suggested by Laurent Pinchart.
---> Fixed trival code clean up/spacing issues as suggested by Laurent Pinchart.
drivers/dma/xilinx/xilinx_vdm
This patch updates the device-tree binding doc for
adding support for AXI CDMA.
Signed-off-by: Kedareswara rao Appana
---
Changes for v2:
---> Modified commit message as suggested by Vinod.
---> Moved the patch to forward in the series as suggested by vinod.
.../devicetree/bindings/dma/
This patch renames the vdma-mm2s-channel/vdma-s2mm-channel
property with dma-mm2s-channel/dma-s2mm-channel to sync with
the driver.
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> New patch.
Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 8
1 f
: Kedareswara rao Appana
---
Changes for v3:
---> None.
Changes for v2:
---> have differenet structures for h/w desc.
---> Added comments to the relevant sections as suggested by Laurent Pinchart.
---> Fixed trival code clean up/spacing issues as suggested by Laurent Pinchart.
driver
This patch updates the device-tree binding doc for
adding support for AXI CDMA.
Signed-off-by: Kedareswara rao Appana
---
Changes for v3:
---> Removed CDMA DT example from the patch as suggested by the Rob.
Changes for v2:
---> Modified commit message as suggested by Vinod.
---> Moved
1 - 100 of 220 matches
Mail list logo
