On 11.07.2019 08:22, Viresh Kumar wrote:
> On 08-07-19, 16:11, k.koniec...@partner.samsung.com wrote:
>> From: Kamil Konieczny
>>
>> Add enable regulators to dev_pm_opp_set_regulators() and disable
>> regulators to dev_pm_opp_put_regulators(). This prepares for
>&
On 10.07.2019 19:04, Krzysztof Kozlowski wrote:
> On Mon, 8 Jul 2019 at 16:12, wrote:
>>
>> From: Kamil Konieczny
>>
>> Reuse opp core code for setting bus clock and voltage. As a side
>> effect this allow useage of coupled regulators feature (required
>>
n add that Exynos5433 has both slimSSS and SSS IPs.
Kamil Konieczny (3):
arm64: dts: exynos: add SlimSSS for Exynos5433
dt-bindings: crypto: document Exynos5433 SlimSSS
crypto: s5p: add AES support for Exynos5433
.../bindings/crypto/samsung-slimsss.txt | 19 +++
arch/arm64/boot/
Add DT node for SlimSSS (aka Slim SecuritySubSystem) in Exynos5433 SoC.
The users can use compatibility "samsung,exynos5433-slim-sss".
Signed-off-by: Kamil Konieczny
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm6
Document DT bindings for crypto Samsung Exynos5433 SlimSSS (Slim Security
SubSystem) IP.
Signed-off-by: Kamil Konieczny
---
.../bindings/crypto/samsung-slimsss.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto
Add AES crypto HW acceleration for Exynos5433, with the help of SlimSSS IP.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kamil Konieczny
---
drivers/crypto/s5p-sss.c | 50
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto
Fix bug "s5p-sss crypto driver doesn't set next AES-CBC IV". This should
also fix AES-CTR mode. Tested on Odroid U3 with Eric Biggers branch
"iv-out-testing".
Signed-off-by: Kamil Konieczny
---
drivers/crypto/s5p-sss.c | 8
1 file changed, 8 insertions(+)
di
> prefixes has no bearing on its value.
>
> The signature length, however was incorrect, which is a problem for RSA
> implementations that need it to be exactly correct (like AMD CCP).
>
> Signed-off-by: Maciej S. Szmigiero
your e-mail address looks incorrect
[...]
--
B
rflow threshold to value i.e. 1000 and we know that at 1000MHz
> and full utilization (100%) the counter will reach that threshold
> after 500ms (which we want, because we don't want too many interrupts
> per sec). What if suddenly utilization drops to 2% (i.e. from 5GB/s
>
On 25.06.2020 14:02, Lukasz Luba wrote:
>
>
> On 6/25/20 12:30 PM, Kamil Konieczny wrote:
>> Hi Lukasz,
>>
>> On 25.06.2020 12:02, Lukasz Luba wrote:
>>> Hi Sylwester,
>>>
>>> On 6/24/20 4:11 PM, Sylwester Nawrocki wrote:
>>>> Hi
tions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index 341433fbcc4a..fdcbfd45c884 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -2307,8 +2307,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
> [...]
Acked-by: Kamil Konieczny
= dev_err_probe(dev, PTR_ERR(pdata->pclk),
> + "failed to find clock %s\n",
> + variant->clk_names[1]);
> goto err_clk;
> }
>
>
Reviewed-by: Kamil Konieczny
Acked-by: Kamil Konieczny
cumentation/devicetree/bindings/crypto/samsung-slimsss.yaml
> @@ -19,7 +19,7 @@ description: |+
> properties:
>compatible:
> items:
> - - const: samsung,exynos5433-slim-ss
> + - const: samsung,exynos5433-slim-sss
>
> reg:
> maxItems: 1
>
Reviewed-by: Kamil Konieczny
Acked-by: Kamil Konieczny
struct s5p_hash_reqctx {
> struct s5p_aes_dev *dd;
> @@ -1125,7 +1126,7 @@ static int s5p_hash_copy_sg_lists(struct
> s5p_hash_reqctx *ctx,
> * s5p_hash_prepare_sgs() - prepare sg for processing
> * @ctx: request context
> * @sg: source scatterlist request
> - * @nbytes: number of bytes to process from sg
> + * @new_len: number of bytes to process from sg
> * @final: final flag
> *
> * Check two conditions: (1) if buffers in sg have len aligned data, and (2)
>
Reviewed-by: Kamil Konieczny
Acked-by: Kamil Konieczny
Hi,
On 30.01.2019 17:51, Rob Herring wrote:
> On Thu, Jan 24, 2019 at 04:45:20PM +0100, Kamil Konieczny wrote:
>> Document DT bindings for crypto Samsung Exynos5433 SlimSSS (Slim Security
>> SubSystem) IP.
>>
>> Reviewed-by: Krzysztof Kozlowski
>&g
frequency. They both are
> done by the governor but the workqueue must be scheduled periodically.
>
> I couldn't do much with this back then. I have given the example that
> this is causing issues with the DMC [2]. There is also a description
> of your situation staying at 633MHz for long time:
> ' When it is missing opportunity
> to change the frequency, it can either harm the performance or power
> consumption, depending of the frequency the device stuck on.'
>
> The patches were not accepted because it will cause CPU wake-up from
> idle, which increases the energy consumption. I know that there were
> some other attempts, but I don't know the status.
>
> I had also this devfreq workqueue issue when I have been working on
> thermal cooling for devfreq. The device status was not updated, because
> the devfreq workqueue didn't check the device [3].
>
> Let me investigate if that is the case.
>
> Regards,
> Lukasz
>
> [1] https%3A%2F%2Flkml.org%2Flkml%2F2019%2F2%2F11%2F1146
> [2] https%3A%2F%2Flkml.org%2Flkml%2F2019%2F2%2F12%2F383
> [3]
> https%3A%2F%2Flwn.net%2Fml%2Flinux-kernel%2F2020051912.3001-11-lukasz.luba%40arm.com%2F
and here was another try to fix wq: "PM / devfreq: add possibility for delayed
work"
https://lkml.org/lkml/2019/12/9/486
--
Best regards,
Kamil Konieczny
Samsung R&D Institute Poland
On 15.02.2018 17:27, Marek Vasut wrote:
> On 02/15/2018 04:41 PM, Herbert Xu wrote:
>> On Thu, Jan 18, 2018 at 07:33:59PM +0100, Kamil Konieczny wrote:
>>> First four patches add empty hash export and import functions to each
>>> driver,
>>> with the same b
On 15.02.2018 18:06, Marek Vasut wrote:
> On 02/15/2018 06:00 PM, Kamil Konieczny wrote:
>>
>>
>> On 15.02.2018 17:27, Marek Vasut wrote:
>>> On 02/15/2018 04:41 PM, Herbert Xu wrote:
>>>> On Thu, Jan 18, 2018 at 07:33:59PM +0100, Kamil Konieczny wrot
On 15.02.2018 19:32, Marek Vasut wrote:
> On 02/15/2018 07:06 PM, Kamil Konieczny wrote:
>>
>>
>> On 15.02.2018 18:06, Marek Vasut wrote:
>>> On 02/15/2018 06:00 PM, Kamil Konieczny wrote:
>>>>
>>>>
>>>> On 15.02.2018 17:27,
In AES-ECB mode crypt is done with key only, so any use of IV
can cause kernel Oops, as reported by Anand Moon.
Fixed it by using IV only in AES-CBC and AES-CTR.
Signed-off-by: Kamil Konieczny
Reported-by: Anand Moon
---
Tested on Odroid XU4/HC1, kernel 4.15 with following command:
fallocate
On 16.02.2018 15:54, Boris Brezillon wrote:
> Adding back all the people that were Cc-ed on the initial email.
>
> On Fri, 16 Feb 2018 15:18:21 +0100
> Kamil Konieczny wrote:
>
>> On 16.02.2018 15:00, Boris Brezillon wrote:
>>> On Fri, 16 Feb 2018 12:21:53 +0
On 06.02.2018 17:48, Anand Moon wrote:
> Hi Kamil,
>
> Thanks for providing the fix to this issue.
>
> On 5 February 2018 at 23:10, Kamil Konieczny
> wrote:
>>
>> In AES-ECB mode crypt is done with key only, so any use of IV
>> can cause kernel Oops, as repo
In AES-ECB mode crypt is done with key only, so any use of IV
can cause kernel Oops. Use IV only in AES-CBC and AES-CTR.
Signed-off-by: Kamil Konieczny
Reported-by: Anand Moon
Reviewed-by: Krzysztof Kozlowski
Tested-by: Anand Moon
Cc: sta...@vger.kernel.org
Fixes: 8f9702aad138 ("crypto
In AES-ECB mode crypt is done with key only, so any use of IV
can cause kernel Oops. Use IV only in AES-CBC and AES-CTR.
Signed-off-by: Kamil Konieczny
Reported-by: Anand Moon
Reviewed-by: Krzysztof Kozlowski
Tested-by: Anand Moon
Cc: sta...@vger.kernel.org # can be applied after commit
where N=402, 403, 404 (MD5, SHA1, SHA256).
Modifications in drivers/crypto/Kconfig:
- Select sw algorithms MD5, SHA1 and SHA256 in S5P
as they are nedded for fallback.
Signed-off-by: Kamil Konieczny
---
drivers/crypto/Kconfig |6 +
drivers/crypto/s5p-sss.c | 2062
Hi Krzysztof,
On 13.09.2017 15:18, Krzysztof Kozlowski wrote:
> On Wed, Sep 13, 2017 at 2:44 PM, Kamil Konieczny
> wrote:
>> Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
>> It uses the crypto framework asynchronous hash api.
>> It is based on omap-s
tcrypt sec=1 mode=N
where N=402, 403, 404 (MD5, SHA1, SHA256).
Modifications in drivers/crypto/Kconfig:
- Add new CRYPTO_DEV_EXYNOS_HASH, depend on !EXYNOS_RNG
and CRYPTO_DEV_S5P
- Select sw algorithms MD5, SHA1 and SHA256 in EXYNOS_HASH
as they are nedded for fallback.
Signed-off-by: Kamil
On 03.10.2017 21:30, Krzysztof Kozlowski wrote:
> On Tue, Oct 03, 2017 at 04:57:43PM +0200, Kamil Konieczny wrote:
>
>>>> [...]
>>>> +static struct ahash_alg algs_sha256[] = {
>>>> +{
>>>> + .init = s5p_hash_init,
>
tcrypt sec=1 mode=N
where N=402, 403, 404 (MD5, SHA1, SHA256).
Modifications in drivers/crypto/Kconfig:
- Add new CRYPTO_DEV_EXYNOS_HASH, depend on !EXYNOS_RNG
and CRYPTO_DEV_S5P
- Select sw algorithms MD5, SHA1 and SHA256 in EXYNOS_HASH
as they are nedded for fallback.
Signed-off-by: Kamil
On 19.09.2017 21:03, Krzysztof Kozlowski wrote:
> On Fri, Sep 15, 2017 at 07:50:06PM +0200, Kamil Konieczny wrote:
>> Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
>> It uses the crypto framework asynchronous hash api.
>> It is based on omap-sham.c drive
On 25.09.2017 21:03, Javier Romero wrote:
> Hi,
>
> Last question, it will be the same to do Kernel testing on a virtual machine,
> or it will be better to do kernel testing over a no virtual machine?
>
> El 24/09/17 a las 17:25, Ken Moffat escribió:
>> On Sun, Sep 24, 2017 at 12:52:08PM -0300,
On 25.09.2017 20:27, Krzysztof Kozlowski wrote:
> On Fri, Sep 22, 2017 at 08:00:17PM +0200, Kamil Konieczny wrote:
>> On 19.09.2017 21:03, Krzysztof Kozlowski wrote:
>>> On Fri, Sep 15, 2017 at 07:50:06PM +0200, Kamil Konieczny wrote:
>
> (...)
>
>>>> +
>
t's intended as a single-user
> /sbin/init replacement. You'll need a full-featured userspace with an actual
> init daemon (sysvinit, systemd, etc) and an ssh daemon (openssh, or if you
> want [...]
What about /usr/bin/ssh as init replacement ?
--
Best regards,
Kamil Konieczny
Samsung R&D Institute Poland
On 30.09.2017 21:50, Krzysztof Kozlowski wrote:
> On Wed, Sep 27, 2017 at 02:25:50PM +0200, Kamil Konieczny wrote:
>> Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
>> It uses the crypto framework asynchronous hash api.
>> It is based on omap-sham.c drive
On 26.09.2017 21:28, Krzysztof Kozlowski wrote:
> On Tue, Sep 26, 2017 at 05:54:42PM +0200, Kamil Konieczny wrote:
>> On 25.09.2017 20:27, Krzysztof Kozlowski wrote:
>> [...]
>>>>>> +struct tasklet_struct hash_tasklet;
>>>>>>
tcrypt sec=1 mode=N
where N=402, 403, 404 (MD5, SHA1, SHA256).
Modifications in drivers/crypto/Kconfig:
- Add new CRYPTO_DEV_EXYNOS_HASH, depend on !EXYNOS_RNG
and CRYPTO_DEV_S5P
- Select sw algorithms MD5, SHA1 and SHA256 in EXYNOS_HASH
as they are nedded for fallback.
Signed-off-by: Kamil
ience.
see
https://kernelnewbies.org/
gmane.linux.kernel.kernelnewbies
You can also contribute by testing, see
https://lists.kernelnewbies.org/pipermail/kernelnewbies/2017-April/017765.html
http://tobin.cc/blog
Regards,
Kamil Konieczny
On 19.09.2017 21:03, Krzysztof Kozlowski wrote:
> On Fri, Sep 15, 2017 at 07:50:06PM +0200, Kamil Konieczny wrote:
>> Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
>> It uses the crypto framework asynchronous hash api.
>> It is based on omap-sham.c drive
tcrypt sec=1 mode=N
where N=402, 403, 404 (MD5, SHA1, SHA256).
Modifications in drivers/crypto/Kconfig:
- Add new CRYPTO_DEV_EXYNOS_HASH, depend on !EXYNOS_RNG
and CRYPTO_DEV_S5P
- Select sw algorithms MD5, SHA1 and SHA256 in EXYNOS_HASH
as they are nedded for fallback.
Signed-off-by: Kamil
long with
> software-based Tursted Executation Environment (TEE) to enable the
- ^ Trusted
> third-party tursted applications.
-- ^ trusted
[...]
--
Best regards,
Kamil Konieczny
Samsung R&D Institute Poland
(struct ahash_request *req, int err)
+{
+ struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
+ struct stm32_hash_dev *hdev = rctx->hdev;
+
+ if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {
--
Best regards,
Kamil Konieczny
Samsung R&D Institute Poland
Add myself as co-maintainer for Samsung Security SubSystem driver.
Signed-off-by: Kamil Konieczny
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52fd76..3f6cadf2e087 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11982,6 +11982,7 @@ F
-by: Kamil Konieczny
---
Changes:
v2: clarify reasons for co-maintenance.
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52fd76..3f6cadf2e087 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11982,6 +11982,7 @@ F: drivers/media/i2c
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