Before performing additional cleanups to this driver, do the easy
cleanups first.
Signed-off-by: Josh Cartwright
Reviewed-by: Stephen Boyd
---
drivers/rtc/rtc-pm8xxx.c | 97 ++--
1 file changed, 53 insertions(+), 44 deletions(-)
diff --git a/drivers
Setup wakeup capability before rtc_register to ensure the rtc class core
properly sets up our 'wakealarm' sysfs attribute.
Signed-off-by: Josh Cartwright
Reviewed-by: Stephen Boyd
---
drivers/rtc/rtc-pm8xxx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
Make use of the devm_* variant of request_any_context_irq to allow for
elimination of remove().
Signed-off-by: Josh Cartwright
Reviewed-by: Stephen Boyd
---
drivers/rtc/rtc-pm8xxx.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/rtc/rtc-pm8xxx.c
Now that the parent mfd driver has been made to work again, and has been
reworked to create a regmap instance intended for it's children to use,
rework the pm8xxx driver to use the regmap API for it's register
accesses.
Reviewed-by: Stephen Boyd
Signed-off-by: Josh Cartwright
---
d
This RTC is found on the Qualcomm 8921 and 8058 PMICs.
Signed-off-by: Josh Cartwright
---
.../devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt
diff --git a
-by: Josh Cartwright
Reviewed-by: Stephen Boyd
Acked-by: Lee Jones
---
drivers/rtc/rtc-pm8xxx.c | 52 +++---
include/linux/mfd/pm8xxx/rtc.h | 25
2 files changed, 29 insertions(+), 48 deletions(-)
delete mode 100644 include/linux/mfd
On Mon, Mar 10, 2014 at 01:47:41PM -0700, Andrew Morton wrote:
> On Mon, 10 Mar 2014 13:44:45 -0500 Josh Cartwright
> wrote:
> > Now that the parent mfd driver has been made to work again, and has been
> > reworked to create a regmap instance intended for it's children
On Mon, Mar 10, 2014 at 01:47:48PM -0700, Andrew Morton wrote:
> On Mon, 10 Mar 2014 13:44:47 -0500 Josh Cartwright
> wrote:
>
> > Add support for describing the PM8921/PM8058 RTC in device tree.
> >
> > Additionally:
> >- drop support for descr
On Mon, Mar 10, 2014 at 04:22:51PM -0500, Rob Herring wrote:
> On Mon, Mar 10, 2014 at 1:44 PM, Josh Cartwright wrote:
> > This RTC is found on the Qualcomm 8921 and 8058 PMICs.
> >
> > Signed-off-by: Josh Cartwright
> > ---
> > .../devicetree/bindings
On Tue, Mar 11, 2014 at 01:06:09PM +, Lee Jones wrote:
> > > > Something in the MFD_PM8XXX driver must have changed recently that now
> > > > allows
> > > > the KEYBOARD_PMIC8XXX driver to be enabled. Unfortunately, it does not
> > > > build
> > > > because of a dependency on the header file
On Fri, Apr 25, 2014 at 03:32:51PM +0300, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> Currently functions that exist in both the controller at the
> same address offset can not be specified with the same names.
The terminology here is a bit confusing. When I read "controller", I
hear "SP
On Tue, Feb 11, 2014 at 09:27:36PM +0100, Tomasz Figa wrote:
> On 11.02.2014 21:19, Josh Cartwright wrote:
> >On Tue, Feb 11, 2014 at 09:04:21PM +0100, Tomasz Figa wrote:
> > >On 11.02.2014 21:02, Benjamin Herrenschmidt wrote:
> > > >On Tue, 2014-02-11 at 1
The acpi_dev_pm_attach/_detach functions perform their own checks to
ensure the device has an ACPI companion. It is not necessary for the
caller to do so.
This mirrors what other busses with ACPI dev PM support do (i2c, spi,
sdio).
Cc: Len Brown
Cc: Rafael J. Wysocki
Signed-off-by: Josh
On Fri, Feb 14, 2014 at 04:53:08PM +0100, Laurent Pinchart wrote:
> On Friday 14 February 2014 10:58:22 Mark Rutland wrote:
> > On Fri, Feb 14, 2014 at 01:00:01AM +, Laurent Pinchart wrote:
> > > +Channels Optional Properties:
> > > +
> > > + - clock-source-rating: rating of the timer as a clo
Hey Ivan-
Nit below.
On Tue, Feb 18, 2014 at 03:21:20PM +0200, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> Allows controller to be specified via device tree.
> Pass PHY phandle specified in DT to core driver.
>
> Signed-off-by: Ivan T. Ivanov
> ---
> drivers/usb/chipidea/ci_hdrc_msm.c
The generic SPMI example was missing an equal sign in the assignment
of the #size-cells property.
Signed-off-by: Josh Cartwright
---
Documentation/devicetree/bindings/spmi/spmi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spmi
On Fri, Mar 21, 2014 at 03:52:23PM +0200, Matei Oprea wrote:
> Fix different address spaces when unmapping IO. hi->addr_mapped[0]
> and hi->addr_mapped[1] should be tagged __iomem.
>
> Signed-off-by: Matei Oprea
> Cc: ROSEdu Kernel Community
> ---
> drivers/staging/cxt1e1/hwprobe.c |4 ++--
le_table = b2105_duty_cycle_table,
> +};
> +
> +static struct of_device_id st_pwm_of_match[] = {
const?
Other than that:
Reviewed-by: Josh Cartwright
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hosted by The Linux Foundation
--
To unsubscribe from this lis
On Mon, Apr 21, 2014 at 12:30:42AM -0500, Andy Gross wrote:
> The GSBI (General Serial Bus Interface) driver controls the overarching
> configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
> earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
> functionalit
On Mon, Apr 21, 2014 at 12:11:18PM -0500, Andy Gross wrote:
> On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
> > > + if (of_property_read_u32(node, "qcom,mode", &mode)) {
> > > + dev_err(gsbi->dev, "missing mode config
On Mon, Mar 31, 2014 at 11:14:24AM -0700, Stephen Boyd wrote:
> If the debounce time is 0 our usage of ilog2() later on in this
> driver will cause undefined behavior. If CONFIG_OF=n this fact is
> evident to the compiler, and it emits a call to ilog2_NaN()
> which doesn't exist. Fix this by se
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
> * Move SoC peripherals into an SoC container node
> * Move serial enabling into board file (qcom-msm8960-cdp.dts)
> * Cleanup cpu node to match binding spec, enable-method and compatible
> should be per cpu, not part of the container
>
On Mon, May 05, 2014 at 04:44:25PM -0500, Suman Anna wrote:
> Hi Rob,
>
> On 04/30/2014 07:34 PM, Suman Anna wrote:
> > The property 'hwlock-reserved-locks' will be used to represent
> > the number of locks to be reserved for clients that would need
> > to request/operate on specific locks. A new
Hey all-
Looking through a bunch of irqdomain implementations (and in some other
places), it appears that the following pattern is distressingly common:
static int foo_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
/*..
es on the SPMI bus. The status register is
read to determine when the command sequence has completed and whether
or not it completed successfully.
Signed-off-by: Kenneth Heitke
Signed-off-by: Josh Cartwright
---
drivers/spmi/Kconfig | 17 ++
drivers/spmi/Makefile| 2 +
drivers
urora.org
[5]: http://lkml.kernel.org/r/cover.1376596224.git.jo...@codeaurora.org
Josh Cartwright (4):
spmi: add generic SPMI controller binding documentation
spmi: pmic_arb: add support for interrupt handling
spmi: document the PMIC arbiter SPMI bindings
regmap: spmi: support base and extende
Write Long') when possible.
Signed-off-by: Josh Cartwright
Acked-by: Mark Brown
---
drivers/base/regmap/regmap-spmi.c | 228 --
include/linux/regmap.h| 12 +-
2 files changed, 205 insertions(+), 35 deletions(-)
diff --git a/drivers/base/reg
handling which allows for these interrupts to be used.
Cc: Thomas Gleixner
Signed-off-by: Josh Cartwright
---
drivers/spmi/Kconfig | 1 +
drivers/spmi/spmi-pmic-arb.c | 377 ++-
2 files changed, 376 insertions(+), 2 deletions(-)
diff --git a
Signed-off-by: Josh Cartwright
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi
Signed-off-by: Josh Cartwright
---
Documentation/devicetree/bindings/spmi/spmi.txt | 41 +
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spmi/spmi.txt
diff --git a/Documentation/devicetree/bindings/spmi/spmi.txt
b/Documentation
to 16 logical slaves.
The framework supports message APIs, multiple busses (1 controller
per bus) and multiple clients/slave devices per controller.
Signed-off-by: Kenneth Heitke
Signed-off-by: Michael Bohan
Signed-off-by: Josh Cartwright
---
drivers/Kconfig | 2 +
drivers
On Tue, Feb 04, 2014 at 09:10:45PM +0100, Thomas Gleixner wrote:
> On Mon, 3 Feb 2014, Josh Cartwright wrote:
> > +static void qpnpint_irq_ack(struct irq_data *d)
> > +{
> > + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
> > + u8 irq = d->h
On Wed, Feb 05, 2014 at 10:07:50AM +, Grant Likely wrote:
> On Tue, 04 Feb 2014 13:09:33 +0100, Marek Szyprowski
> wrote:
> > From: Grant Likely
> > +/reserved-memory node
> > +-
> > +#address-cells, #size-cells (required) - standard definition
> > +- Should use the s
Hey Ivan-
On Wed, Feb 05, 2014 at 03:47:38PM +0200, Ivan Khoronzhuk wrote:
> Add broadcast clock-event device for the Keystone arch.
>
> The timer can be configured as a general-purpose 64-bit timer,
> dual general-purpose 32-bit timers. When configured as dual 32-bit
> timers, each half can oper
Hey Rohit-
On Thu, Oct 17, 2013 at 11:25:10AM -0700, Rohit Vaswani wrote:
> This patch adds basic board support for APQ8074 Dragonboard
> which belongs to the Snapdragon 800 family.
> For now, just support a basic machine with device tree.
>
> Signed-off-by: Rohit Vaswani
> ---
> arch/arm/boot/
On Fri, Feb 07, 2014 at 01:39:52AM -0600, Andy Gross wrote:
> On Thu, Feb 06, 2014 at 06:57:48PM +0200, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov"
> >
> > Qualcomm Universal Peripheral (QUP) core is an AHB slave that
> > provides a common data path (an output FIFO and an input FIFO)
> > for
Hey Mark-
On Fri, Feb 07, 2014 at 05:18:34PM +, Mark Brown wrote:
> On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote:
>
> > config SPI_QUP
> > tristate "Qualcomm SPI Support with QUP interface"
> > depends on
On Fri, Feb 07, 2014 at 05:31:08PM +, Mark Brown wrote:
> On Fri, Feb 07, 2014 at 11:20:51AM -0600, Josh Cartwright wrote:
> > On Fri, Feb 07, 2014 at 05:18:34PM +, Mark Brown wrote:
> > > On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote:
> > &g
On Thu, Oct 02, 2014 at 12:08:38PM -0700, Stephen Boyd wrote:
[..]
> On 10/01/14 11:15, Josh Cartwright wrote:
> > The percpu-ness of the two WDTs makes configuration even more
> > interesting, as it's possible you'd want to independently configure
> > timeo
Select QCOM_WDT to allow for the watchdog driver to be built.
Signed-off-by: Josh Cartwright
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 8c7da33..80bad9a 100644
--- a/arch/arm
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
IPQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Now that the Krait Processor Sub-system (KPSS) Watchdog driver has been pulled
into Wim's tree destined for 3.18, add descriptions of the WDT in the relevant
device trees, and include the driver in qcom_defconfig.
Josh Cartwright (4):
ARM: qcom: add QCOM_WDT driver to qcom_defconfig
ARM:
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
APQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
MSM8960 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Hey Stephen-
Thanks for taking a look.
On Wed, Oct 01, 2014 at 10:28:55AM -0700, Stephen Boyd wrote:
> On 10/01, Josh Cartwright wrote:
> > @@ -96,6 +104,13 @@
> > cpu-offset = <0x8>;
> > };
> >
On Wed, Jul 08, 2015 at 01:54:34PM +0200, Richard Cochran wrote:
> On Mon, Jul 06, 2015 at 03:44:58PM -0500, Josh Cartwright wrote:
> > It's difficult to make too many judgements without seeing how a driver
> > might implement this; is there another patchset that shows how a d
On Mon, Jun 08, 2015 at 11:38:35PM +0530, Punnaiah Choudary Kalluri wrote:
> The following patches add arm pl353 static memory controller driver for
> xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and
> nor/sram memory interfaces. The current implementation supports only a
> s
On Thu, Aug 20, 2015 at 10:48:38AM +0800, Dongsheng Yang wrote:
> On 08/20/2015 04:35 AM, Richard Weinberger wrote:
> >This is a partial revert of commit d7f0b70d30ffb9bbe6b8a3e1035cf0b79965ef53
> >("UBIFS: Add security.* XATTR support for the UBIFS").
>
> Hi Richard,
> What about a full rev
On Thu, Apr 28, 2016 at 09:19:47AM -0500, Nathan Sullivan wrote:
> Since of_mdiobus_register and mdiobus_register will scan automatically,
This is only partially true. of_mdiobus_register() only scans for PHYs
with device tree presence (starting with nodes which specify an address,
then continuin
On Thu, Apr 28, 2016 at 08:59:32PM +0200, Andrew Lunn wrote:
> On Thu, Apr 28, 2016 at 01:55:27PM -0500, Nathan Sullivan wrote:
> > On Thu, Apr 28, 2016 at 08:43:03PM +0200, Andrew Lunn wrote:
> > > > I agree that is a valid fix for AT91, however it won't solve our
> > > > problem, since
> > > > w
On Thu, Apr 28, 2016 at 11:23:15PM +0200, Andrew Lunn wrote:
> On Thu, Apr 28, 2016 at 04:03:57PM -0500, Josh Cartwright wrote:
> > On Thu, Apr 28, 2016 at 08:59:32PM +0200, Andrew Lunn wrote:
> > > On Thu, Apr 28, 2016 at 01:55:27PM -0500, Nathan Sullivan wrote:
> > > &
On Thu, Apr 28, 2016 at 07:34:59PM -0500, Josh Cartwright wrote:
> On Thu, Apr 28, 2016 at 11:23:15PM +0200, Andrew Lunn wrote:
> > On Thu, Apr 28, 2016 at 04:03:57PM -0500, Josh Cartwright wrote:
> > > On Thu, Apr 28, 2016 at 08:59:32PM +0200, Andrew Lunn wrote:
> > > &
On Fri, Apr 29, 2016 at 02:40:53PM +0200, Nicolas Ferre wrote:
[..]
> > static int macb_mii_init(struct macb *bp)
> > {
> > struct macb_platform_data *pdata;
> > struct device_node *np;
> > - int err = -ENXIO, i;
> > + int err = -ENXIO;
> >
> > /* Enable management port */
> >
On Mon, May 02, 2016 at 12:08:50PM -0700, Florian Fainelli wrote:
> On 02/05/16 11:36, Josh Cartwright wrote:
> > On Fri, Apr 29, 2016 at 02:40:53PM +0200, Nicolas Ferre wrote:
> > [..]
> >>> static int macb_mii_init(struct macb *bp)
> >>> {
&
On Mon, Dec 07, 2015 at 11:58:33AM +0100, Neil Armstrong wrote:
> On some platforms, the macb integration does not use the USRIO
> register to configure the (R)MII port and clocks.
> When the register is not implemented and the MACB error signal
> is connected to the bus error, reading or writing t
On Wed, Nov 18, 2015 at 11:05:44PM +0200, Ioan-Adrian Ratiu wrote:
> On Wed, 18 Nov 2015 21:37:42 +0100 (CET)
> Jiri Kosina wrote:
>
> > On Wed, 18 Nov 2015, Ioan-Adrian Ratiu wrote:
> >
> > > The critical section protected by usbhid->lock in hid_ctrl() is too
> > > big and in rare cases causes
On Mon, Oct 26, 2015 at 05:44:22PM -0700, Paul E. McKenney wrote:
> On Mon, Oct 26, 2015 at 02:14:55PM -0500, Josh Cartwright wrote:
> > This reverts commit be3fc413da9eb17cce0991f214ab019d16c88c41.
> >
> > While the use of synchronize_rcu_expedited() might make
> > syn
On Tue, Oct 27, 2015 at 04:15:59PM -0700, Paul E. McKenney wrote:
> On Tue, Oct 27, 2015 at 08:27:53AM -0700, Eric Dumazet wrote:
> > On Tue, 2015-10-27 at 12:02 -0300, Arnaldo Carvalho de Melo wrote:
[..]
> > > The first suggestion, with it disabled by default seems to be the most
> > > flexible t
On Tue, Oct 27, 2015 at 05:09:12PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> The Simple FPGA bus uses the FPGA Manager Framework and the
> FPGA Bridge Framework to provide a manufactorer-agnostic
> interface for reprogramming FPGAs that is Device Tree
> Overlays-based.
Do y
On Wed, Oct 28, 2015 at 08:37:51AM -0700, Moritz Fischer wrote:
> On Wed, Oct 28, 2015 at 3:07 AM, Josh Cartwright wrote:
> > On Tue, Oct 27, 2015 at 05:09:12PM -0500, at...@opensource.altera.com wrote:
> >> From: Alan Tull
> >>
> >> The Simple FPGA bus use
On Wed, Oct 28, 2015 at 12:03:41PM -0500, atull wrote:
> On Wed, 28 Oct 2015, Moritz Fischer wrote:
>
> > On Wed, Oct 28, 2015 at 9:18 AM, Josh Cartwright wrote:
> > > On Wed, Oct 28, 2015 at 08:37:51AM -0700, Moritz Fischer wrote:
> > >> On Wed, Oct 28, 2015 a
On Wed, Oct 28, 2015 at 12:59:16PM -0500, Josh Cartwright wrote:
> On Wed, Oct 28, 2015 at 12:03:41PM -0500, atull wrote:
> > On Wed, 28 Oct 2015, Moritz Fischer wrote:
> >
> > > On Wed, Oct 28, 2015 at 9:18 AM, Josh Cartwright wrote:
> > > > On Wed, Oct
)
(kthread_worker_fn) from (kthread+0xd0/0xe8)
(kthread) from (ret_from_fork+0x14/0x2c)
Reported-by: Sean Nyekjaer
Fixes: 9e6f4ca3e567 ("sc16is7xx: use kthread_worker for tx_work and irq")
Cc: sta...@vger.kernel.org # v4.1+
Signed-off-by: Josh Cartwright
---
drivers/tty/serial/sc16is7xx.c | 2
regulator driver
to support the SMB208.
This patchset is based ontop of v7 of Bjorne Andersson's RPM patchset [1].
1:
http://lkml.kernel.org/r/1411428329-23172-1-git-send-email-bjorn.anders...@sonymobile.com
Josh Cartwright (3):
mfd: devicetree: qcom_rpm: document IPQ8064 resources
The IPQ8064 SoC has several RPM-controlled resources, an NSS fabrick
clock and four regulator resources. Provide definitions for them.
Signed-off-by: Josh Cartwright
---
Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 6 +-
include/dt-bindings/mfd/qcom-rpm.h | 6
The IPQ8064 reference boards make use of SMB208 regulators which are
controlled by RPM. Implement support for these regulators in the RPM
regulator driver.
Signed-off-by: Josh Cartwright
---
drivers/regulator/qcom_rpm-regulator.c | 19 +++
1 file changed, 19 insertions(+)
diff
The IPQ8064 also includes an RPM following the same message structure as
other chips. In addition, it supports a few new resource types to
support the NSS fabric clocks and the SMB208/SMB209 regulators found on
the reference boards.
Signed-off-by: Josh Cartwright
---
drivers/mfd/qcom_rpm.c
On Tue, Oct 07, 2014 at 04:07:43PM -0700, Stephen Boyd wrote:
> On 10/07/2014 03:10 PM, Josh Cartwright wrote:
> >On Thu, Oct 02, 2014 at 12:08:38PM -0700, Stephen Boyd wrote:
[..]
> >>I'm thinking:
> >>
> >> timer@200a000 {
> >&g
On Wed, Oct 08, 2014 at 09:18:44PM +0200, Nicolas Dechesne wrote:
> Georgi,
>
> On Tue, Sep 2, 2014 at 5:40 PM, Georgi Djakov wrote:
> > Enable support for the two SD host controllers on the APQ8084 platform
> > by adding the required nodes to the DT files.
> > On the IFC6540 board, the first con
cc1: some warnings being treated as errors
>
> Looking at the git logs it seems this was added via:
>
> commit cf1fc187628913070c3e418ce0e205732435aa2f
> Author: Josh Cartwright
> Date: Tue Sep 23 15:59:53 2014 -0500
>
> pinctrl: qcom: use restart_notifier mechanism for ps_hold
>
Something tells me that Russell's patch system won't like to accept a
patch with a duplicate ID (although, I could be wrong).
On Tue, May 12, 2015 at 08:22:01AM +0200, Michal Simek wrote:
> From: Thomas Betker
>
> This patch is based on the
> commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit
The configurations are not modified by the driver. Make them 'const' so
that they may be placed in a read-only section.
Signed-off-by: Josh Cartwright
---
drivers/net/ethernet/cadence/macb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ne
On Tue, Mar 10, 2015 at 07:46:23PM +0530, Punnaiah Choudary Kalluri wrote:
> Device-tree binding documentation for Xilinx ZDMA Engine
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
Hey Punnaiah-
Was this intended to be sent out with a driver?
> .../devicetree/bindings/dma/xilinx/zdma.txt
On Fri, Feb 27, 2015 at 09:09:29AM -0600, Josh Cartwright wrote:
> By making use of the restart_handler chain mechanism, the SLCR-based
> reset mechanism can be prioritized amongst other mechanisms available on
> a particular board.
Have either of you had a chance to look at this yet
Hey Michal-
I've got a few comments on this.
On Mon, Feb 23, 2015 at 12:37:26PM +0100, Michal Simek wrote:
> Xilinx Microblaze is placed in programmable logic on Xilinx
> Zynq architecture. Driver requires specific HW setting
> described in DT binding.
>
> Signed-off-by: Michal Simek
[..]
> +++
On Thu, Feb 12, 2015 at 10:26:16AM +, Mark Rutland wrote:
> On Thu, Feb 12, 2015 at 10:22:07AM +, Michal Simek wrote:
> > Add OCM node for all zynq boards. OCM location
> > can changed but for all current boards this
> > is the location where OCM is.`
> >
> > Signed-off-by: Michal Simek
>
On Tue, Feb 17, 2015 at 04:52:45PM -0800, Bryan Wu wrote:
> On Tue, Feb 17, 2015 at 4:32 PM, Ricardo Ribalda Delgado
[..]
> > Then we have TWO gpios chip. Each of them have a led named red. When
> > the second gpio-led is probed we have an error. Everything else
> > (address offset, phandle, device
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright
---
arch/arm/mach-zynq/common.c
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright
---
v1 -> v2: Also d
Hello!
I looked through your driver and have some comments.
On Mon, Mar 02, 2015 at 11:25:11PM +0530, Kedareswara rao Appana wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memory access between m
Hey Gilad-
On Mon, Feb 09, 2015 at 03:51:12PM -0700, Gilad Avidov wrote:
> Qualcomm PMIC Arbiter version-2 changes from version-1 are:
>
> - Some different register offsets.
> - New channel register space, one per PMIC peripheral (ppid).
> All tx traffic uses these channels.
> - New observer re
us
justification.
Therefore,
Acked-by: Josh Cartwright
Josh
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From: Kalle Valo
commit 31b9cc9a873dcab161999622314f98a75d838975 upstream.
Jason noticed that with Yocto GCC 4.8.1 ath6kl crashes with this iperf command:
iperf -c $TARGET_IP -i 5 -t 50 -w 1M
The crash was:
Unable to handle kernel paging request at virtual address 1a48
pgd = 80004000
[1a4
On Tue, Mar 08, 2016 at 06:52:06PM +0100, Sebastian Andrzej Siewior wrote:
> * Daniel Wagner | 2016-03-08 16:59:13 [+0100]:
>
> >Hi,
> Hi,
>
> >As Peter correctly pointed out in [1] a simple conversion from
> >wait to swait in completion.c wont work. I played a bit around and
> >came up with this
Hey Kyle-
On Mon, Mar 14, 2016 at 04:55:08PM -0500, Kyle Roeschley wrote:
> From: Gratian Crisan
From what I understand, this was mostly Aaron's work, so he should get
authorship. I could be wrong, though, but you'll want to check.
> These changes add support for PIEs (physical interface eleme
On Fri, Apr 01, 2016 at 01:13:06AM +0530, punnaiah choudary kalluri wrote:
> Hi,
>
> We are using the pl353 smc controller for interfacing the nand in our zynq
> SOC.
> The driver for this controller is currently under mainline review.
> Recently we are moved to 4.4 kernel and observing issues wi
On Fri, Oct 09, 2015 at 12:45:05AM +0200, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 26
> ++
> 1 file changed, 26 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/fpga/xilinx-zynq
Hey Moritz-
On Fri, Oct 09, 2015 at 12:45:07AM +0200, Moritz Fischer wrote:
> This commit adds FPGA Manager support for the Xilinx Zynq chip.
> The code heavily borrows from the xdevcfg driver in Xilinx'
> vendor tree.
>
> Signed-off-by: Moritz Fischer
[..]
> +++ b/drivers/fpga/zynq-fpga.c
[..]
On Tue, Sep 29, 2015 at 01:00:45PM -0700, Brian Norris wrote:
> On Tue, Sep 29, 2015 at 12:55:39PM -0700, Brian Norris wrote:
>
> ...
>
> Seems Ben Shelton has moved on to other things...
He has, but there are others paying attention who want this feature :).
Josh
signature.asc
Description:
On Tue, Aug 30, 2016 at 03:01:51PM -0700, Andy Lutomirski wrote:
> On Wed, Aug 24, 2016 at 9:51 AM, Josh Cartwright wrote:
[..]
> >> diff --git a/kernel/fork.c b/kernel/fork.c
> >> index 52e725d4a866..05f7ef796fb4 100644
> >> --- a/kernel/fork.c
> >> +++
On Mon, Mar 14, 2016 at 03:05:59PM -0700, Greg KH wrote:
> On Mon, Mar 14, 2016 at 04:54:32PM -0500, Kyle Roeschley wrote:
> > From: Jeff Westfahl
> >
> > This driver introduces support for hardware features of National
> > Instruments real-time controllers. This is an ACPI device that exposes
>
On Tue, Mar 15, 2016 at 10:50:31PM -0400, Paul Gortmaker wrote:
> On Tue, Mar 15, 2016 at 7:25 PM, Paul Gortmaker
> wrote:
> > On Tue, Mar 15, 2016 at 5:45 PM, Paul Gortmaker
> > wrote:
> >> On Mon, Mar 14, 2016 at 11:49 AM, Steven Rostedt
> >> wrote:
> >>>
> >>> Dear RT Folks,
> >>>
> >>> 3.14
Hello Alexandre-
Few comments below.
On Sat, Sep 26, 2015 at 03:54:39PM +0200, Alexandre Belloni wrote:
> This driver supports the following functions:
> - reading and settings time
> - alarms when connected to an IRQ
> - reading and clearing the voltage low flags
> - nvram
>
> Signed-off-by
On Tue, Sep 22, 2015 at 10:21:10AM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> API to support programming FPGA's.
>
> The following functions are exported as GPL:
> * fpga_mgr_buf_load
>Load fpga from image in buffer
>
> * fpga_mgr_firmware_load
>Request firmware and
On Tue, Sep 22, 2015 at 10:21:11AM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add driver to fpga manager framework to allow configuration
> of FPGA in Altera SoCFPGA parts.
>
> Signed-off-by: Alan Tull
> Acked-by: Michal Simek
> Acked-by: Moritz Fischer
[..]
> +++ b/drive
On Wed, Sep 23, 2015 at 12:10:13PM -0500, atull wrote:
> On Tue, 22 Sep 2015, Josh Cartwright wrote:
[..]
> > > +struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
> > > +{
> > > + struct fpga_manager *mgr;
> > > + struct device *dev;
> >
On Thu, Jul 02, 2015 at 06:14:48PM -0700, Christopher Hall wrote:
> * getsynctime64()
Hello Christopher-
A couple comments below.
>
> This takes 2 arguments referring to system and device time
>
> With this callback drivers may provide both system time and device time
> to ensure precise corre
On Fri, Jul 10, 2015 at 03:37:25PM -0400, Chris Metcalf wrote:
> Normally the tilegx networking shim sends irqs to all the cores
> to distribute the load of processing incoming-packet interrupts,
> so that you can get to multiple Gb's of traffic inbound.
>
> However, in nohz_full mode we don't wan
On Fri, Jul 10, 2015 at 07:06:23PM -0400, Chris Metcalf wrote:
> On 7/10/2015 6:45 PM, Josh Cartwright wrote:
> >>+static inline const struct cpumask *housekeeping_cpumask(void)
> >>>+{
> >>>+#ifdef CONFIG_NO_HZ_FULL
> >>>+ if (tick_nohz_full_ena
Hey Alan-
First off, thanks for all of your (and others') work on this.
On Fri, Feb 05, 2016 at 03:29:58PM -0600, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> New bindings document for FPGA Region to support programming
> FPGA's under Device Tree control
>
> Signed-off-by: Alan Tul
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