[PATCH] tools: spi: enable CROSS_COMPILE in Makefile

Signed-off-by: Jorge Ramirez-Ortiz --- tools/spi/Makefile | 4 1 file changed, 4 insertions(+) diff --git a/tools/spi/Makefile b/tools/spi/Makefile index cd0db62..d1845b0 100644 --- a/tools/spi/Makefile +++ b/tools/spi/Makefile @@ -1,4 +1,8 @@ +CC = $(CROSS_COMPILE)gcc + all: spidev_test

[PATCH v2] tools: spi: enable CROSS_COMPILE in Makefile

Signed-off-by: Jorge Ramirez-Ortiz --- tools/spi/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/spi/Makefile b/tools/spi/Makefile index cd0db62..3815b18 100644 --- a/tools/spi/Makefile +++ b/tools/spi/Makefile @@ -1,3 +1,5 @@ +CC = $(CROSS_COMPILE)gcc + all: spidev_test

[PATCH v2] ARM64: dts: meson s905x: accept MAC addr from u-boot environment

ested-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-librete

[PATCH] ARM64: dts: meson: accept MAC addr from u-boot environment

Extend configuring the MAC address from u-boot to all meson boards. I didn't test this changeset but having checked libretech's u-boot tree I believe it should just work. Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi| 1 +

[PATCH 1/2] dt-bindings: Add Qualcomm USB Super-Speed PHY bindings

Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Vinod Koul --- .../devicetree/bindings/usb/qcom,usb-ssphy.txt | 78 +++

[PATCH 2/2] phy: qualcomm: usb: Add Super-Speed PHY driver

From: Shawn Guo Driver to control the Synopsys SS PHY 1.0.0 implemeneted in QCS404 Based on Sriharsha Allenki's original code. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Shawn Guo Reviewed-by: Vinod Koul --- drivers/phy/qualcomm/Kconfig | 11 ++ drivers/phy/qua

[PATCH 0/2] USB SS PHY for Qualcomm's QCS404

This set adds USB SS PHY support to Qualcomm's QCS404 SoC The PHY is implemented using Synopsys SS PHY 1.0.0 IP The code is based on Sriharsha Allenki's original implementation. Jorge Ramirez-Ortiz (1): dt-bindings: Add Qualcomm USB Super-Speed PHY bindings Shawn Guo (1): phy

[PATCH] iio: imu: st_lsm6dsx: irq not handled unless data pushed to buffers

read errors. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c index 4994f92..4959923 100644

Re: [RFC] regmap: allow volatile register writes with cached only read maps

On 05/13/2018 04:22 AM, Mark Brown wrote: On Fri, May 11, 2018 at 12:29:42PM +0200, Jorge Ramirez-Ortiz wrote: On 05/11/2018 04:00 AM, Mark Brown wrote: We don't currently suppress writes except when regmap_update_bits() notices that the modification was a noop. You probably want to be

[PATCH] checkpatch: add Co-Developed-by to signature tags

As per Documentation/process/submitting-patches, Co-developed-by is a valid signature. This commit removes the warning. Signed-off-by: Jorge Ramirez-Ortiz --- scripts/checkpatch.pl | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 93e84c9

[PATCH 2/2] checkpatch: add Co-developed-by to signature tags

As per Documentation/process/submitting-patches, Co-developed-by is a valid signature. This commit removes the warning. Signed-off-by: Jorge Ramirez-Ortiz --- scripts/checkpatch.pl | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 93e84c9

[PATCH 0/2] Fix Co-Developed-by

The following set unifies the terminology for co-developed patches (losing the capital in Developed) and adds the rule to the checkpatch.pl script to stop warnings. Jorge Ramirez-Ortiz (2): docs: fix Co-Developed-by docs checkpatch: add Co-developed-by to signature tags Documentation

[PATCH 1/2] docs: fix Co-Developed-by docs

The accepted terminology will be Co-developed-by therefore losing the capital letter from now on. Signed-off-by: Jorge Ramirez-Ortiz --- Documentation/process/submitting-patches.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/process/submitting

[PATCH 12/13] arm64: dts: qcom: qcs404: Add cpufreq support

Support CPU frequency scaling on qcs404. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot

[PATCH 09/13] arm64: dts: qcom: qcs404: Add OPP table

Add a CPU OPP table to qcs404 Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot

[PATCH 05/13] clk: qcom: apcs-msm8916: get parent clock names from DT

Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/apcs-msm8916.c | 33 - 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index a6c89a3..2453242 100644

[PATCH 13/13] arm64: defconfig: Enable HFPLL

The high frequency pll is required on compatible Qualcomm SoCs to support the CPU frequency scaling feature. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch

[PATCH 02/13] mbox: qcom: add APCS child device for QCS404

There is clock controller functionality in the APCS hardware block of qcs404 devices similar to msm8916. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 21 + 1 file changed, 13

[PATCH 11/13] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider

Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file changed, 3 insertions

[PATCH 10/13] arm64: dts: qcom: qcs404: Add HFPLL node

The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch

[PATCH 04/13] dt-bindings: mailbox: qcom: Add clock-name optional property

clock driver source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 21 + 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox

[PATCH 00/13] Support CPU frequency scaling on QCS404

appreciate the maintainer's input on this topic. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Jorge Ramirez-Ortiz (13): clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency mbox: qcom: add APCS child device for QCS404 mbox: qcom: replac

[PATCH 07/13] clk: qcom: hfpll: register as clock provider

Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/hfpll.c | 10 +- 1 file changed, 9 insertions(+), 1

[PATCH 06/13] clk: qcom: hfpll: get parent clock names from DT

Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/hfpll.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index a6de7101..87b7f46 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c

[PATCH 01/13] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency

Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/gcc-qcs404.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/gcc

[PATCH 03/13] mbox: qcom: replace integer with valid macro

Use the correct macro when registering the platform device. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/qcom-apcs

[PATCH 08/13] clk: qcom: hfpll: CLK_IGNORE_UNUSED

itical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/h

Re: [PATCH 1/2] dt-bindings: Add Qualcomm USB Super-Speed PHY bindings

On 07/12/18 10:55:57, Jorge Ramirez-Ortiz wrote: > Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY > controller embedded in QCS404. > > Based on Sriharsha Allenki's original > definitions. > > Signed-off-by: Jorge Ramirez-Ortiz > Reviewed

[PATCH] arm64: dts: qcom: qcs404: sdcc1: enable HS400

The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a39924e

[PATCH] nvmem: core: fix read_buffer in place

All unused/extra bytes in the cell buffer must be zeroed. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/nvmem/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index f7301bb4ef3b..65e198adebac 100644 --- a/drivers/nvmem

[PATCH] regulator: core: do not report EPROBE_DEFER as error.

Do not log a temporary failure to get a regulator (EPROBE_DEFER) while the driver is requesting retries. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/regulator/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c

[PATCH v2] regulator: core: do not report EPROBE_DEFER as error but as debug

Temporary failures to get a regulator (EPROBE_DEFER) should be logged as debug information instead of errors. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/regulator/core.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/core.c b/drivers/regulator

[PATCH 0/3] qcom: add PMS405 SPMI regulator

The following patchset applies cleanly on linux 5.0-rc2. It adds support for the pms405 spmi regulators and configures s3 as a supply. The dts modifications required to enable voltage scaling will be posted after the currently pending cpufreq patches are merged. Jorge Ramirez-Ortiz (3): dt

[PATCH 1/3] dt-bindings: qcom_spmi: Document pms405 support

The PMS405 supports 5 SMPS and 13 LDO regulators. Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/regulator/qcom,spmi-regulator.txt | 24 ++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b

[PATCH 2/3] drivers: regulator: qcom: add PMS405 SPMI regulator

units of millivolts S3 controls the cpu voltages (s3 is a buck regulator of type HFS430); it is therefore required so we can enable voltage scaling for safely running cpufreq. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/regulator/qcom_spmi-regulator.c | 197 +--- 1

[PATCH 3/3] arm64: dts: qcom: pms405: add spmi regulators

The PMS405 sports 5 SMPS and 13 LDO regulators. Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/pms405.dtsi | 20 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index ad2b62d

[PATCH] drivers: optee: allow op-tee to access devices on the i2c bus

Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to control this type of cryptographic devices it needs coordinated access to the bus, so collisions and RUNTIME_PM dont get in the way. This trampoline driver allow OP-TEE to access them. Signed-off-by: Jorge Ramirez-

[PATCH v2] drivers: optee: allow op-tee to access devices on the i2c bus

Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to control this type of cryptographic devices it needs coordinated access to the bus, so collisions and RUNTIME_PM dont get in the way. This trampoline driver allow OP-TEE to access them. Signed-off-by: Jorge Ramirez-

[PATCHv7] drivers: optee: allow op-tee to access devices on the i2c bus

Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to control this type of cryptographic devices it needs coordinated access to the bus, so collisions and RUNTIME_PM dont get in the way. This trampoline driver allow OP-TEE to access them. Signed-off-by: Jorge Ramirez-

[PATCHv8] drivers: optee: allow op-tee to access devices on the i2c bus

Some secure elements like NXP's SE050 sit on I2C buses. For OP-TEE to control this type of cryptographic devices it needs coordinated access to the bus, so collisions and RUNTIME_PM dont get in the way. This trampoline driver allow OP-TEE to access them. Signed-off-by: Jorge Ramirez-

[PATCHv3 2/2] hwrng: optee: fix wait use case

first read. Worth noticing that since msleep(0) schedules a one jiffy timeout is better to skip such a call. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Sumit Garg --- drivers/char/hw_random/optee-rng.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char

[PATCHv3 2/2] hwrng: optee: fix wait use case

first read. Worth noticing that since msleep(0) schedules a one jiffy timeout is better to skip such a call. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Sumit Garg --- drivers/char/hw_random/optee-rng.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char

[PATCHv3 1/2] hwrng: optee: handle unlimited data rates

Data rates of MAX_UINT32 will schedule an unnecessary one jiffy timeout on the call to msleep. Avoid this scenario by using 0 as the unlimited data rate. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Sumit Garg --- drivers/char/hw_random/optee-rng.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH] usb: gadget: USB3 support to the legacy printer driver

On 11/18/2014 03:47 PM, Felipe Balbi wrote: > Hi, > > On Tue, Nov 18, 2014 at 03:41:43PM -0500, Jorge Ramirez-Ortiz wrote: >>>>> you have no clue what these mean, do you ? How about reading the USB >>>>> specification of even http://www.beyondlogic.org/usbn

[PATCH] usb: gadget: USB3 support to the legacy printer driver

Hi, This patch adds USB3 support to the legacy gadget printer driver. Applies cleanly on fc14f9c Linux 3.18-rc5. Please could it be considered for inclusion? regards, Jorge >From f46d9b0d2160b30f14dee104657de865e9e2bc38 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 25

Re: [PATCH] usb: gadget: USB3 support to the legacy printer driver

On 11/17/2014 07:54 PM, Greg KH wrote: > On Mon, Nov 17, 2014 at 06:30:28PM -0600, Felipe Balbi wrote: >> Hi, >> >> On Mon, Nov 17, 2014 at 06:19:54PM -0500, Jorge Ramirez-Ortiz wrote: >>> Hi, >>> >>> This patch adds USB3 support to the legacy gadge

[PATCH] usb: gadget: USB3 support to the legacy printer driver

g_printer driver. 0) enable the net2280 on the g_printer: -- From 8e306693839a77bfe3411a842d4d20acb9dae9e3 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Mon, 17 Nov 2014 22:31:59 -0500 Subject: [PATCH] use the 338x

Re: [PATCH] usb: gadget: USB3 support to the legacy printer driver

On 11/18/2014 10:17 AM, Felipe Balbi wrote: > Hi, > > On Tue, Nov 18, 2014 at 09:19:36AM -0500, Jorge Ramirez-Ortiz wrote: >> Hi Felipe/Greg >> >> Thanks for your comments on my previous attempt. >> I think I addressed them here. > no you haven't. Read

[PATCH] usb: gadget: add USB3 support to the printer driver

This patch adds USB3 support to the printer driver. Tests used two binaries (host/device) to handle the file transfer [gadget] $ dmesg net2280 :02:00.0: usb_reset_338x: Defect 7374 FsmValue 0xf000 net2280 :02:00.0: usb_reinit_338x: Defect 7374 FsmValue f000 net2280 :02:00.0

[PATCH] usb: gadget: add USB3 support to the printer driver

Add SS descriptors to support the capabilities provided by USB3 controller drivers; unit tests run using a PLX 3380 [max transfer speed measured of 1Gbps] This driver shall fallback to lower operating modes when the higher ones are not available. Signed-off-by: Jorge Ramirez-Ortiz --- drivers

Re: [PATCH] usb: gadget: USB3 support to the legacy printer driver

On 11/18/2014 01:00 PM, Felipe Balbi wrote: > Hi, > > (fix your mailer, lines should be broken at 80-characters. > Documentation/email-clients.txt has tips) > > On Tue, Nov 18, 2014 at 12:52:11PM -0500, Jorge Ramirez-Ortiz wrote: >> On 11/18/2014 10:17 AM, Felipe Balbi w

dw_mmc: HLE errors

Doug/Jaehoon, Were there any follow ups to this thread [1] from March 30, 2015? We are seeing HLE errors on 3.18 and we are trying to determine if a solution was ever delivered. On inspection, I can't find anything specific in recent kernels that address this particular issue (was the actual root

Re: dw_mmc: HLE errors

On 11/23/2015 11:57 AM, Doug Anderson wrote: > Jorge, > > On Mon, Nov 23, 2015 at 6:10 AM, Jorge Ramirez-Ortiz > wrote: >> Doug/Jaehoon, >> >> Were there any follow ups to this thread [1] from March 30, 2015? >> We are seeing HLE errors on 3.18 and we are tryi

Re: dw_mmc: HLE errors

On 11/23/2015 07:11 PM, Jaehoon Chung wrote: > Dear, Jorge. > > On 11/24/2015 02:29 AM, Jorge Ramirez-Ortiz wrote: >> On 11/23/2015 11:57 AM, Doug Anderson wrote: >>> Jorge, >>> >>> On Mon, Nov 23, 2015 at 6:10 AM, Jorge Ramirez-Ortiz >>> wrote:

[PATCH 2/2] watchdog: pm8916_wdt: fix missing include

As per Documentation/process/submit-checklist.rst, when using a facility #include the file that defines/declares that facility. Don't depend on other header files pulling in ones that you use. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/pm8916_wdt.c | 1 + 1 file chang

[PATCH 1/2] watchdog: pm8916_wdt: fix pretimeout registration flow

When an IRQ is present in the dts, the probe function shall fail if the interrupt can not be registered. The probe function shall also be retried if getting the irq is being deferred. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/pm8916_wdt.c | 16 1 file changed, 12

[PATCH 0/2] qcom_wdt bark irq support

remove unecessary variable from the driver's private storage v2: register the pre-timeout notifier. With the second patch in the set, I took the oportunity to do some cleanup in the same code base removing an unnecesary variable from the driver's private storage. Jorge Ramire

[PATCH 2/2] watchdog: qcom: remove unnecessary variable from private storage

there is no need to continue keeping the clock in private storage. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/qcom-wdt.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index 935c78a882a3

[PATCH 1/2] watchdog: qcom: support pre-timeout when the bark irq is available

Use the bark interrupt as the pre-timeout notifier whenever this interrupt is available. By default, the pretimeout notification shall occur one second earlier than the timeout. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/qcom-wdt.c | 70 ++--- 1

[PATCH] clk: qcom: fix QCS404 TuringCC regmap

The max register is 0x23004 as per the manual (the current max_register that this commit is fixing is actually out of bounds). Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/turingcc-qcs404.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/turingcc

[PATCH] mailbox: qcom-apcs: fix max_register value

The mailbox length is 0x1000 hence the max_register value is 0xFFC. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc

[PATCH v2] clk: qcom: fix QCS404 TuringCC regmap

The max register is 0x23004 as per the manual (the current max_register that this commit is fixing is actually out of bounds). Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC") Signed-off-by: Jorge Ramirez-Ortiz --- v2: add Fixes tag drivers/clk/qcom/turingcc-qcs404.c | 2

[PATCH v2] mailbox: qcom-apcs: fix max_register value

The mailbox length is 0x1000 hence the max_register value is 0xFFC. Fixes: c6a8b171ca8e ("mailbox: qcom: Convert APCS IPC driver to use regmap") Signed-off-by: Jorge Ramirez-Ortiz --- v2: added Fixes tag drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +- 1 file changed, 1 inser

[PATCH v2 0/2] mbox changes for QCS404 DVFS

These are the mailbox changes required to enable CPU frequency scaling on Qualcomm's QCS404. v2: sboyd review replace if statement with a of_match_device dont modify platform_set_drvdata Jorge Ramirez-Ortiz (2): mbox: qcom: add APCS child device for QCS404 mbox: qcom: replace in

[PATCH v2 1/2] mbox: qcom: add APCS child device for QCS404

There is clock controller functionality in the APCS hardware block of qcs404 devices similar to msm8916. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++-- 1 file changed, 6 insertions(+), 2

[PATCH v2 2/2] mbox: qcom: replace integer with valid macro

Use the correct macro when registering the platform device. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[PATCH 1/2] arm64: dts: qcom: qcs404: add sleep clk fixed rate oscillator

This fixed rate clock is required for the operation of some devices (ie watchdog). Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi

[PATCH 2/2] arm64: dts: qcom: qcs404: add the watchdog node

Allows QCS404 based designs to enable watchdog support Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 131d8046d3be

[PATCH 2/5] clk: qcom: apcs-msm8916: get parent clock names from DT

Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/apcs-msm8916.c | 23 --- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index

[PATCH 4/5] clk: qcom: hfpll: register as clock provider

Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd --- drivers/clk/qcom/hfpll.c

[PATCH 3/5] clk: qcom: hfpll: get parent clock names from DT

Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/hfpll.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index a6de7101430c..87b7f46d27e0 100644 --- a/drivers/clk/qcom

[PATCH 5/5] clk: qcom: hfpll: CLK_IGNORE_UNUSED

itical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn

[PATCH 1/5] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency

Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd --- drivers/clk/qcom/clk-alpha-pll.c | 8 drivers

[PATCH 2/2] mbox: qcom: replace integer with valid macro

Use the correct macro when registering the platform device. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[PATCH 1/2] mbox: qcom: add APCS child device for QCS404

There is clock controller functionality in the APCS hardware block of qcs404 devices similar to msm8916. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 +--- 1

[PATCH 1/6] dt-bindings: mailbox: qcom: Add clock-name optional property

clock driver source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../mailbox/qcom,apcs-kpss-global.txt | 24 --- 1 file changed, 21 insertions(+), 3

[PATCH 4/6] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider

Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file

[PATCH 2/6] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider

node. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5ea9fb8f2f87..96dc7a12aa94

[PATCH 3/6] arm64: dts: qcom: qcs404: Add HFPLL node

The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 + 1 file changed, 9

[PATCH 5/6] arm64: dts: qcom: qcs404: Add DVFS support

following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz

[PATCH 6/6] arm64: defconfig: Enable HFPLL

The high frequency pll is required on compatible Qualcomm SoCs to support the CPU frequency scaling feature. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1

[PATCH] watchdog: qcom: add support for the bark interrupt

Use the bark interrupt to notify the bark event. Since the bark and bite timeouts are identical, increase the bite timeout by one second so that the bark event can be logged to the console. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/qcom-wdt.c | 42

[no subject]

Use the bark interrupt as the pre-timeout notifier whenever this interrupt is available. By default, the pretimeout notification shall occur one second earlier than the timeout. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/qcom-wdt.c | 63 ++--- 1

[PATCH v2] watchdog: qcom: support pre-timeout when the bark irq is available

Use the bark interrupt as the pre-timeout notifier whenever this interrupt is available. By default, the pretimeout notification shall occur one second earlier than the timeout. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/watchdog/qcom-wdt.c | 63 ++--- 1

[PATCH v3] watchdog: qcom: support pre-timeout when the bark irq is available

Use the bark interrupt as the pre-timeout notifier whenever this interrupt is available. By default, the pretimeout notification shall occur one second earlier than the timeout. Signed-off-by: Jorge Ramirez-Ortiz --- v3: remove unnecesary variable added to private. v2: register the

[PATCH v4] watchdog: qcom: support pre-timeout when the bark irq is available

Use the bark interrupt as the pre-timeout notifier whenever this interrupt is available. By default, the pretimeout notification shall occur one second earlier than the timeout. Signed-off-by: Jorge Ramirez-Ortiz --- v4: address Guenter Roeck comments as follows: remove unnecessary

[PATCH v2 1/5] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency

Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd --- drivers/clk/qcom/clk-alpha-pll.c | 8 drivers

[PATCH v2 5/5] clk: qcom: apcs-msm8916: get parent clock names from DT

Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/apcs-msm8916.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index a6c89a310b18

[PATCH v2 4/5] clk: qcom: hfpll: use clk_parent_data to specify the parent

Extend support to platorms using different parents. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/hfpll.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom

[PATCH v2 3/5] clk: qcom: hfpll: CLK_IGNORE_UNUSED

itical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn

[PATCH v2 0/5] Clock changes to support cpufreq on QCS404

The following clock changes are required to enable cpufreq support on the QCS404 v2: sboyd review of v1 --- missing cover letter reorder the patchset use clk_parent data to speficy the parent clock dong ignore the clock position abi Jorge Ramirez-Ortiz (5

[PATCH v2 2/5] clk: qcom: hfpll: register as clock provider

Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd --- drivers/clk/qcom/hfpll.c

[PATCH 2/5] misc: fastrpc: fix memory leak from miscdev->name

From: Srinivas Kandagatla Fix a memory leak in miscdev->name by using devm_variant Orignally reported by kmemleak: [] kmemleak_alloc+0x50/0x84 [] __kmalloc_track_caller+0xe8/0x168 [] kvasprintf+0x78/0x100 [] kasprintf+0x50/0x74 [] fastrpc_rpmsg_probe+0xd8/0x20c [] rpmsg_d

[PATCH 5/5] misc: fastrpc: revert max init file size back to 2MB

With the integration of the mmap/unmap functionality, it is no longer necessary to allow large memory allocations upfront since they can be handled during runtime. Tested on QCS404 with CDSP Neural Processing test suite. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Srinivas Kandagatla

[PATCH 0/5] misc: fastrpc: fixes and map/unmap support

Hi Greg These patches implement a few fixes identified while working on the QCS404 ML integration plus we now have support for mmap/unmap of buffers (so the process can be created with less initial memory requirements). Jorge Ramirez-Ortiz (4): misc: fastrpc: add mmap/unmap support misc

[PATCH 3/5] misc: fastrpc: do not interrupt kernel calls

necessary, this timeout will need to be revisited. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Srinivas Kandagatla --- drivers/misc/fastrpc.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index bc03500bfe60

[PATCH 4/5] misc: fastrpc: handle interrupted contexts

Buffers owned by a context that has been interrupted either by a signal or a timeout might still be being accessed by the DSP. delegate returning the associated memory to a later time when the device is released. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Srinivas Kandagatla --- drivers

[PATCH 1/5] misc: fastrpc: add mmap/unmap support

Support the allocation/deallocation of buffers mapped to the DSP. When the memory mapped to the DSP at process creation is not enough, the fastrpc library can extend it at runtime. This avoids having to do large preallocations by default. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Srinivas

[PATCH v2 1/5] misc: fastrpc: add mmap/unmap support

Support the allocation/deallocation of buffers mapped to the DSP. When the memory mapped to the DSP at process creation is not enough, the fastrpc library can extend it at runtime. This avoids having to do large preallocations by default. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Srinivas

[PATCH v4 3/4] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings

Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed phy controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/phy/qcom,snps-usb-ssphy.txt | 79 +++ 1 file changed, 79

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