On 09/07/2016 05:06 PM, Daniel Thompson wrote:
On 07/09/16 15:28, Jorge Ramirez-Ortiz wrote:
Signed-off-by: Jorge Ramirez-Ortiz
---
tools/spi/Makefile | 4
1 file changed, 4 insertions(+)
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index cd0db62..d1845b0 100644
--- a/tools/spi
On 12/18/18 00:37, Stephen Boyd wrote:
Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:22)
Allow accessing the parent clock names required for the driver
operation by using the device tree node.
This permits extending the driver to other platforms without having to
modify its source code.
For
patch anyway I wont pursue it further.
Otherwise please let me know I will also update the documentation to
match the commit.
TIA
.
Signed-off-by: Jorge Ramirez-Ortiz
[]
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
[]
@@ -468,6 +468,7 @@ our $logFunctions = qr{(?x:
On 12/14/18 17:13, Greg KH wrote:
On Fri, Dec 14, 2018 at 07:52:15AM -0800, Joe Perches wrote:
On Fri, 2018-12-14 at 14:01 +0100, Jorge Ramirez-Ortiz wrote:
As per Documentation/process/submitting-patches, Co-developed-by is a
valid signature.
This commit removes the warning.
Your commit
On 12/14/18 18:39, Joe Perches wrote:
On Fri, 2018-12-14 at 22:58 +0530, Himanshu Jha wrote:
On Fri, Dec 14, 2018 at 08:27:33AM -0800, Joe Perches wrote:
Is it really important to specify things like 75% / 25%
authorship crediting?
IDK how that ratio came up into this discussion ?
How does on
On 12/20/18 21:25, Stephen Boyd wrote:
Quoting Jorge Ramirez-Ortiz (2018-12-07 01:55:57)
+
+- qcom,vdd-voltage-level:
+Value type:
+Definition: This is a list of three integer values where
+each value corresponding to voltage corner in uV.
As far as I'm aware,
On 12/20/18 18:37, Jack Pham wrote:
Hi Rob, Jorge,
On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
controller embedded in QCS404.
Bas
On 12/20/18 18:07, Rob Herring wrote:
On Thu, Dec 20, 2018 at 10:52:45AM +0100, Jorge Ramirez-Ortiz wrote:
On 07/12/18 10:55:57, Jorge Ramirez-Ortiz wrote:
Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
controller embedded in QCS404.
Based on Sriharsha Allenki's
On 12/21/18 12:19, Taniya Das wrote:
On 12/17/2018 3:16 PM, Jorge Ramirez-Ortiz wrote:
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
specifications.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/clk/qcom
On 12/21/18 20:28, Bjorn Andersson wrote:
On Fri 21 Dec 09:58 PST 2018, Taniya Das wrote:
Hello,
On 12/21/2018 6:06 PM, Jorge Ramirez wrote:
On 12/21/18 12:19, Taniya Das wrote:
On 12/17/2018 3:16 PM, Jorge Ramirez-Ortiz wrote:
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its
On 12/21/18 22:40, Stephen Boyd wrote:
Quoting Jorge Ramirez (2018-12-21 11:45:28)
On 12/21/18 20:28, Bjorn Andersson wrote:
Perhaps there's a better way to define that this particular clock
hardware can change rate, but in this implementation it must not?
the initialization for
On 12/28/18 23:28, Stephen Boyd wrote:
Quoting Jorge Ramirez (2018-12-26 01:20:07)
On 12/18/18 15:35, Niklas Cassel wrote:
On Mon, Dec 17, 2018 at 03:37:43PM -0800, Stephen Boyd wrote:
Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:22)
Allow accessing the parent clock names required for the
On 12/18/18 15:35, Niklas Cassel wrote:
On Mon, Dec 17, 2018 at 03:37:43PM -0800, Stephen Boyd wrote:
Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:22)
Allow accessing the parent clock names required for the driver
operation by using the device tree node.
This permits extending the driver to
On 12/20/18 21:29, Stephen Boyd wrote:
Quoting Jorge Ramirez-Ortiz (2018-12-07 01:55:58)
From: Shawn Guo
Driver to control the Synopsys SS PHY 1.0.0 implemeneted in QCS404
Based on Sriharsha Allenki's original code.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Shawn Guo
On 12/20/18 21:25, Stephen Boyd wrote:
Quoting Jorge Ramirez-Ortiz (2018-12-07 01:55:57)
+
+- qcom,vdd-voltage-level:
+Value type:
+Definition: This is a list of three integer values where
+each value corresponding to voltage corner in uV.
As far as I'm aware,
On 12/20/18 18:37, Jack Pham wrote:
Hi Rob, Jorge,
On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
controller embedded in QCS404.
Bas
On 4/17/19 17:46, Mark Brown wrote:
> On Wed, Apr 17, 2019 at 10:54:11AM +0200, Jorge Ramirez-Ortiz wrote:
>> Do not log a temporary failure to get a regulator (EPROBE_DEFER) while
>> the driver is requesting retries.
>
>> -dev_err(dev, "Fa
On 4/25/19 20:37, Mark Brown wrote:
> On Fri, Apr 19, 2019 at 07:29:48PM +0200, Jorge Ramirez wrote:
>> On 2/4/19 10:03, Mark Brown wrote:
>
>>>> + /* we know we only have one range for this type */
>>>> + if (vreg->logical_type == SPMI_REGULATOR_LOGI
On 4/25/19 23:29, Stephen Boyd wrote:
> Quoting Jorge Ramirez (2019-04-22 04:44:50)
>> On 2/22/19 19:11, Stephen Boyd wrote:
>>> Quoting Jorge Ramirez-Ortiz (2019-01-28 10:32:52)
>>>> @@ -61,6 +65,25 @@ static int qcom_apcs_msm8916_clk_probe(struct
>>>&
On 1/30/19 21:02, Rob Herring wrote:
> On Tue, Jan 29, 2019 at 12:35:14PM +0100, Jorge Ramirez-Ortiz wrote:
>> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
>> controller embedded in QCS404.
>>
>> Based on Sriharsha Allenki's original
>&
On 2/5/19 12:02, Jorge Ramirez wrote:
> On 1/30/19 21:02, Rob Herring wrote:
>> On Tue, Jan 29, 2019 at 12:35:14PM +0100, Jorge Ramirez-Ortiz wrote:
>>> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
>>> controller embedded in QCS404.
>
On 1/17/19 07:44, Bjorn Andersson wrote:
> On Mon 17 Dec 01:46 PST 2018, Jorge Ramirez-Ortiz wrote:
>
>> When the APCS clock is registered (platform dependent), it retrieves
>> its parent names from hardcoded values in the driver.
>>
>> The following commit allo
On 1/28/19 17:57, Jorge Ramirez wrote:
> On 1/17/19 07:44, Bjorn Andersson wrote:
>> On Mon 17 Dec 01:46 PST 2018, Jorge Ramirez-Ortiz wrote:
>>
>>> When the APCS clock is registered (platform dependent), it retrieves
>>> its parent names from hardcoded values in
>>>
static const u32 reg_offset_data_apcs_tmr[] = {
[WDT_RST] = 0x38,
[WDT_EN] = 0x40,
@@ -54,15 +58,38 @@ struct qcom_wdt *to_qcom_wdt(struct watchdog_device
*wdd)
return container_of(wdd, struct qcom_wdt, wdd);
}
+static inline int qcom
On 9/6/19 19:40, Bjorn Andersson wrote:
> On Thu 05 Sep 14:00 PDT 2019, Jorge Ramirez-Ortiz wrote:
>> diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
> [..]
>> +static inline int qcom_get_enable(struct watchdog_device *wdd)
>> +{
>> +
On 9/10/19 11:14, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz, Linaro (2019-09-09 09:54:08)
>> On 09/09/19 09:17:03, Stephen Boyd wrote:
>>> But now the binding is different for the same compatible. I'd prefer we
>>> keep using devm_clk_get() and use a dev
On 9/10/19 11:34, Jorge Ramirez wrote:
> On 9/10/19 11:14, Stephen Boyd wrote:
>> Quoting Jorge Ramirez-Ortiz, Linaro (2019-09-09 09:54:08)
>>> On 09/09/19 09:17:03, Stephen Boyd wrote:
>>>> But now the binding is different for the same compatible. I'd prefer we
On 2/23/19 17:52, Bjorn Andersson wrote:
> On Thu 07 Feb 03:17 PST 2019, Jorge Ramirez-Ortiz wrote:
>
>> Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed phy
>> controller embedded in QCS404.
>>
>> Based on Sriharsha Allenki's original
&g
On 8/29/19 00:31, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2019-08-26 09:46:24)
>> There is clock controller functionality in the APCS hardware block of
>> qcs404 devices similar to msm8916.
>>
>> Co-developed-by: Niklas Cassel
>> Signed-off-by: Nikla
On 8/30/19 20:28, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2019-08-30 09:45:20)
>> On Fri 30 Aug 09:01 PDT 2019, Stephen Boyd wrote:
>>
>>> Quoting Jorge Ramirez (2019-08-29 00:03:48)
>>>> On 2/23/19 17:52, Bjorn Andersson wrote:
>>>>> On T
On 8/27/19 23:45, Srinivas Kandagatla wrote:
>
> On 23/08/2019 16:23, Jorge Ramirez-Ortiz wrote:
>> can you add me as a co-author to this patch please?
>
> No problem I can do that if you feel so!
yes please. thanks!
>
>> since I spent about a day doing the ana
On 8/28/19 10:48, Srinivas Kandagatla wrote:
>
>
> On 28/08/2019 08:50, Jorge Ramirez wrote:
>> On 8/27/19 23:45, Srinivas Kandagatla wrote:
>>> On 23/08/2019 16:23, Jorge Ramirez-Ortiz wrote:
>>>> can you add me as a co-author to this patch please?
>>
On 7/31/19 22:29, Jorge Ramirez-Ortiz wrote:
> The following patchset enables CPU frequency scaling support on the
> QCS404 (with dynamic voltage scaling).
>
> It is important to notice that this functionality will be superseded
> by Core Power Reduction (CPR), a more accurate fo
On 8/26/19 08:54, Jorge Ramirez wrote:
> On 7/31/19 22:29, Jorge Ramirez-Ortiz wrote:
>> The following patchset enables CPU frequency scaling support on the
>> QCS404 (with dynamic voltage scaling).
>>
>> It is important to notice that this functionality will be
On 9/4/19 01:34, Bjorn Andersson wrote:
> On Tue 03 Sep 14:45 PDT 2019, Stephen Boyd wrote:
>
>> Quoting Jack Pham (2019-09-03 10:39:24)
>>> On Mon, Sep 02, 2019 at 08:23:04AM +0200, Jorge Ramirez wrote:
>>>> On 8/30/19 20:28, Stephen Boyd wrote:
>>>>&
On 8/26/19 18:48, Jorge Ramirez-Ortiz wrote:
> When the APCS clock is registered (platform dependent), it retrieves
> its parent names from hardcoded values in the driver.
>
> The following commit allows the DT node to provide such clock names to
> the platform data based clock d
On 8/26/19 18:45, Jorge Ramirez-Ortiz wrote:
> Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
> specifications.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
> Reviewed-by: Bjorn Andersson
>
On 9/5/19 18:39, Bjorn Andersson wrote:
> On Thu 05 Sep 09:21 PDT 2019, Jorge Ramirez-Ortiz wrote:
>
>> Use the bark interrupt to notify the bark event. Since the bark and bite
>> timeouts are identical, increase the bite timeout by one second so
>> that the bark ev
On 9/5/19 20:34, Guenter Roeck wrote:
> On Thu, Sep 05, 2019 at 08:24:19PM +0200, Jorge Ramirez-Ortiz wrote:
>> Use the bark interrupt as the pre-timeout notifier whenever this
>> interrupt is available.
>>
>> By default, the pretimeout notification shall occur one
On 9/5/19 23:19, Guenter Roeck wrote:
> On Thu, Sep 05, 2019 at 11:00:35PM +0200, Jorge Ramirez-Ortiz wrote:
>> Use the bark interrupt as the pre-timeout notifier whenever this
>> interrupt is available.
>>
>> By default, the pretimeout notification shall occur one
On 1/22/19 19:47, Stephen Boyd wrote:
> Quoting Jorge Ramirez (2019-01-17 02:46:21)
>> On 1/17/19 11:08, Viresh Kumar wrote:
>>> On 17-01-19, 09:38, Jorge Ramirez wrote:
>>>> COMMON_CLK_DISABLED_UNUSED relies on the enable_count reference counter
>>>> to d
On 1/26/19 00:29, Bjorn Andersson wrote:
> PMS405 S5 was upstreamed without a voltage and PMS405 L3 is outside the
> acceptable range, causing PCIe to fail. Fix these.
>
> Signed-off-by: Bjorn Andersson
> ---
> arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 6 +++---
> 1 file changed, 3 insertions(+
On 1/30/19 05:41, Vinod Koul wrote:
> On 28-01-19, 19:32, Jorge Ramirez-Ortiz wrote:
>> Add a CPU OPP table to qcs404
>>
>> Co-developed-by: Niklas Cassel
>> Signed-off-by: Niklas Cassel
>> Signed-off-by: Jorge Ramirez-Ortiz
>> ---
>&g
On 1/29/19 21:27, Bjorn Andersson wrote:
> On Tue 29 Jan 03:35 PST 2019, Jorge Ramirez-Ortiz wrote:
>> diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c
>> b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
>> new file mode 100644
>> index 000..e6ae96e
>> --- /dev/n
On 1/30/19 10:53, Jorge Ramirez wrote:
> On 1/29/19 21:27, Bjorn Andersson wrote:
>> On Tue 29 Jan 03:35 PST 2019, Jorge Ramirez-Ortiz wrote:
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c
>>> b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
>>> new file mo
On 1/30/19 10:53, Jorge Ramirez wrote:
>> +priv->vbus = devm_regulator_get_optional(priv->dev, "vbus");
> get_optional means that if vbus-supply is not found, rather than
> returning a dummy regulator object this will fail with -ENODEV.
on this sub
On 1/17/19 07:33, Bjorn Andersson wrote:
> On Mon 17 Dec 01:46 PST 2018, Jorge Ramirez-Ortiz wrote:
>
>> When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
>> to keep the software model of the clock in line with reality, the
>> framework transverses the
On 1/17/19 11:08, Viresh Kumar wrote:
> On 17-01-19, 09:38, Jorge Ramirez wrote:
>> COMMON_CLK_DISABLED_UNUSED relies on the enable_count reference counter
>> to disable the clocks that were enabled by the firwmare and not by the
>> drivers.
>>
>> the cpufreq dri
On 5/6/19 06:38, Mark Brown wrote:
> On Fri, May 03, 2019 at 10:29:42AM +0200, Jorge Ramirez wrote:
>> On 5/3/19 08:26, Mark Brown wrote:
>>> On Thu, May 02, 2019 at 01:30:48PM +0200, Jorge Ramirez wrote:
>
>>> It seems a bit of a jump to add a new driver - it
On 5/20/19 16:56, Jorge Ramirez wrote:
> On 5/20/19 16:51, Stephen Boyd wrote:
>> Quoting Jorge Ramirez-Ortiz (2019-05-20 03:34:35)
>>> When the tty layer requests the uart to throttle, the current code
>>> executing in msm_serial will trigger "Bad mode in Er
On 5/20/19 16:51, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2019-05-20 03:34:35)
>> When the tty layer requests the uart to throttle, the current code
>> executing in msm_serial will trigger "Bad mode in Error Handler" and
>> generate an invalid stack f
On 5/20/19 17:03, Stephen Boyd wrote:
> Quoting Jorge Ramirez (2019-05-20 07:58:54)
>> On 5/20/19 16:56, Jorge Ramirez wrote:
>>>
>>> yeah, semantically confusing msm_reset_dm_count is what really matters:
>>> it tells the hardware to only take n bytes (in t
On 5/20/19 17:12, Bjorn Andersson wrote:
> On Mon 20 May 08:11 PDT 2019, Bjorn Andersson wrote:
>
>> On Mon 20 May 07:58 PDT 2019, Jorge Ramirez wrote:
>>
>>> On 5/20/19 16:56, Jorge Ramirez wrote:
>>>> On 5/20/19 16:51, Stephen Boyd wrote:
>>>>
On 5/20/19 20:50, Bjorn Andersson wrote:
> On Mon 20 May 11:38 PDT 2019, Jorge Ramirez-Ortiz wrote:
>
>> When the tty layer requests the uart to throttle, the current code
>> executing in msm_serial will trigger "Bad mode in Error Handler" and
>> generate an in
On 4/4/19 07:55, Mark Brown wrote:
> On Thu, Apr 04, 2019 at 07:09:22AM +0200, Niklas Cassel wrote:
>> From: Jorge Ramirez-Ortiz
>>
>> Signed-off-by: Jorge Ramirez-Ortiz
>> ---
>> drivers/regulator/qcom_spmi-regulator.c | 7 +++
>> 1 file changed,
On 4/4/19 07:55, Mark Brown wrote:
> On Thu, Apr 04, 2019 at 07:09:22AM +0200, Niklas Cassel wrote:
>> From: Jorge Ramirez-Ortiz
>>
>> Signed-off-by: Jorge Ramirez-Ortiz
>> ---
>> drivers/regulator/qcom_spmi-regulator.c | 7 +++
>> 1 file changed,
On 2/4/19 10:03, Mark Brown wrote:
> On Mon, Jan 28, 2019 at 12:45:03PM +0100, Jorge Ramirez-Ortiz wrote:
>
>> @@ -653,6 +708,10 @@ spmi_regulator_find_range(struct spmi_regulator *vreg)
>> range = vreg->set_points->range;
>> end = range + vreg->set_
On 2/22/19 19:11, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2019-01-28 10:32:52)
>> @@ -61,6 +65,25 @@ static int qcom_apcs_msm8916_clk_probe(struct
>> platform_device *pdev)
>> if (!a53cc)
>> return -ENOMEM;
>>
>> +
t;
> Thanks,
> Mark
>
>>From 317f0111220921e87a168e4e6cec275df4e9be01 Mon Sep 17 00:00:00 2001
> From: Jorge Ramirez-Ortiz
> Date: Wed, 17 Apr 2019 21:24:43 +0200
> Subject: [PATCH] regulator: core: do not report EPROBE_DEFER as error but as
> debug
>
> Te
On 4/27/19 20:21, Mark Brown wrote:
> On Thu, Apr 25, 2019 at 09:44:00PM +0200, Jorge Ramirez wrote:
>
>> the way I see it, if I follow your suggestion and since we are not
>> allowed to extend spmi_regulator_find_range(), the only options are:
>
>> 1) duplicate v
On 5/2/19 04:33, Mark Brown wrote:
> On Mon, Apr 29, 2019 at 02:31:55PM +0200, Jorge Ramirez wrote:
>> On 4/27/19 20:21, Mark Brown wrote:
>
>>> Since the point of this change is AFAICT that this regulator only has a
>>> single linear range it seems like it
On 5/3/19 08:26, Mark Brown wrote:
> On Thu, May 02, 2019 at 01:30:48PM +0200, Jorge Ramirez wrote:
>> On 5/2/19 04:33, Mark Brown wrote:
>
>>> I'm not sure I follow here, sorry - I can see that the driver needs a
>>> custom get/set selector operation
On 7/11/19 16:44, Bjorn Andersson wrote:
> On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
>
>> There is clock controller functionality in the APCS hardware block of
>> qcs404 devices similar to msm8916.
>>
>> Co-developed-by: Niklas Cassel
>> Signed-
On 7/11/19 17:16, Bjorn Andersson wrote:
> On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
>
>> When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
>> to keep the software model of the clock in line with reality, the
>> framework transverses the
On 7/31/19 21:05, Pavel Machek wrote:
> Hi!
hi Pavel,
>
>> [ Upstream commit ba3684f99f1b25d2a30b6956d02d339d7acb9799 ]
>>
>> The function msm_wait_for_xmitr can be taken with interrupts
>> disabled. In order to avoid a potential system lockup - demonstrated
>> under stress testing conditions on
On 6/10/19 19:53, Rob Clark wrote:
> On Mon, Jun 10, 2019 at 10:23 AM Jorge Ramirez-Ortiz
> wrote:
>> The function msm_wait_for_xmitr can be taken with interrupts
>> disabled. In order to avoid a potential system lockup - demonstrated
>> under stress testing conditions on
by cpufreq core) and we skip updating the performance
> state in this case.
>
> Fix this by also updating the performance state when the old_freq ==
> freq.
>
> Fixes: ca1b5d77b1c6 ("OPP: Configure all required OPPs")
> Cc: v5.0 # v5.0
> Reported-by: Niklas Cassel
On 07/06/2016 11:43 PM, Michael Turquette wrote:
Quoting Guodong Xu (2016-06-29 01:45:55)
>From: Jorge Ramirez-Ortiz
>
>Early at boot, during the sys_clk initialization, make sure UART1 uses
>the higher frequency clock, 150MHz.
>
>This enables support for higher baud rate
On 07/07/2016 08:31 AM, Jorge Ramirez wrote:
On 07/06/2016 11:43 PM, Michael Turquette wrote:
Quoting Guodong Xu (2016-06-29 01:45:55)
>From: Jorge Ramirez-Ortiz
>
>Early at boot, during the sys_clk initialization, make sure UART1 uses
>the higher frequency clock, 150MHz.
>
On 07/08/2016 03:48 AM, Michael Turquette wrote:
Quoting Jorge Ramirez (2016-07-07 01:55:05)
On 07/07/2016 08:31 AM, Jorge Ramirez wrote:
On 07/06/2016 11:43 PM, Michael Turquette wrote:
Quoting Guodong Xu (2016-06-29 01:45:55)
From: Jorge Ramirez-Ortiz
Early at boot, during the sys_clk
On 07/08/2016 07:14 PM, Michael Turquette wrote:
Quoting Jorge Ramirez-Ortiz (2016-07-08 01:11:06)
Allow to specify the clock frequency for any given port via the
assigned-clock-rates device tree property.
Signed-off-by: Jorge Ramirez-Ortiz
Tested-by: Jorge Ramirez-Ortiz
---
drivers/tty
On 07/09/2016 02:43 AM, Stephen Boyd wrote:
On 07/08/2016 05:23 PM, Michael Turquette wrote:
Quoting Jorge Ramirez (2016-07-08 14:39:50)
On 07/08/2016 07:14 PM, Michael Turquette wrote:
Quoting Jorge Ramirez-Ortiz (2016-07-08 01:11:06)
Allow to specify the clock frequency for any given port
On 07/11/2016 11:08 PM, Stephen Boyd wrote:
Add the call to of_clk_set_defaults() into the amba probe path so
that devices on the amba bus can use the assigned rates and
parents feature of the common clock framework.
Cc: Michael Turquette
Cc: Jorge Ramirez Ortiz
Signed-off-by: Stephen Boyd
On 07/11/2016 11:08 PM, Stephen Boyd wrote:
Add the call to of_clk_set_defaults() into the amba probe path so
that devices on the amba bus can use the assigned rates and
parents feature of the common clock framework.
Cc: Michael Turquette
Cc: Jorge Ramirez Ortiz
Signed-off-by: Stephen Boyd
On 07/11/2016 11:53 AM, Wei Xu wrote:
Hi Jorge,
On 08/07/2016 09:11, Jorge Ramirez-Ortiz wrote:
Enable support for higher baud rates (up to 3Mbps) in UART1 - required
for bluetooth transfers.
Signed-off-by: Jorge Ramirez-Ortiz
Tested-by: Jorge Ramirez-Ortiz
Fine to me.
Thanks!
Acked-by
On 06/28/2016 12:31 PM, Guodong Xu wrote:
From: Jorge Ramirez-Ortiz
Early at boot, during the sys_clk initialization, make sure UART1 uses
the higher frequency clock.
This enables support for higher baud rates (up to 3Mbps) required to
support faster bluetooth transfers.
Signed-off-by: Jorge
oiding issues with regulator implementations that don't
>> have hardware register support to get the current configured range.
>>
>> Fixes: e92a4047419c ("regulator: Add QCOM SPMI regulator driver")
>> Reported-by: Bjorn Andersson
>> Reported-by: Jorge Ramire
Signed-off-by: Jorge Ramirez-Ortiz
---
tools/spi/Makefile | 4
1 file changed, 4 insertions(+)
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index cd0db62..d1845b0 100644
--- a/tools/spi/Makefile
+++ b/tools/spi/Makefile
@@ -1,4 +1,8 @@
+CC = $(CROSS_COMPILE)gcc
+
all: spidev_test
Signed-off-by: Jorge Ramirez-Ortiz
---
tools/spi/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index cd0db62..3815b18 100644
--- a/tools/spi/Makefile
+++ b/tools/spi/Makefile
@@ -1,3 +1,5 @@
+CC = $(CROSS_COMPILE)gcc
+
all: spidev_test
ested-by: Jorge Ramirez-Ortiz
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-librete
Extend configuring the MAC address from u-boot to all meson boards.
I didn't test this changeset but having checked libretech's u-boot
tree I believe it should just work.
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi| 1 +
Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
controller embedded in QCS404.
Based on Sriharsha Allenki's original
definitions.
Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Vinod Koul
---
.../devicetree/bindings/usb/qcom,usb-ssphy.txt | 78 +++
From: Shawn Guo
Driver to control the Synopsys SS PHY 1.0.0 implemeneted in QCS404
Based on Sriharsha Allenki's original code.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Shawn Guo
Reviewed-by: Vinod Koul
---
drivers/phy/qualcomm/Kconfig | 11 ++
drivers/phy/qua
This set adds USB SS PHY support to Qualcomm's QCS404 SoC
The PHY is implemented using Synopsys SS PHY 1.0.0 IP
The code is based on Sriharsha Allenki's
original implementation.
Jorge Ramirez-Ortiz (1):
dt-bindings: Add Qualcomm USB Super-Speed PHY bindings
Shawn Guo (1):
phy
read errors.
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
index 4994f92..4959923 100644
On 05/13/2018 04:22 AM, Mark Brown wrote:
On Fri, May 11, 2018 at 12:29:42PM +0200, Jorge Ramirez-Ortiz wrote:
On 05/11/2018 04:00 AM, Mark Brown wrote:
We don't currently suppress writes except when regmap_update_bits()
notices that the modification was a noop. You probably want to be
As per Documentation/process/submitting-patches, Co-developed-by is a
valid signature.
This commit removes the warning.
Signed-off-by: Jorge Ramirez-Ortiz
---
scripts/checkpatch.pl | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 93e84c9
As per Documentation/process/submitting-patches, Co-developed-by is a
valid signature.
This commit removes the warning.
Signed-off-by: Jorge Ramirez-Ortiz
---
scripts/checkpatch.pl | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 93e84c9
The following set unifies the terminology for co-developed patches
(losing the capital in Developed) and adds the rule to the
checkpatch.pl script to stop warnings.
Jorge Ramirez-Ortiz (2):
docs: fix Co-Developed-by docs
checkpatch: add Co-developed-by to signature tags
Documentation
The accepted terminology will be Co-developed-by therefore losing the
capital letter from now on.
Signed-off-by: Jorge Ramirez-Ortiz
---
Documentation/process/submitting-patches.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/process/submitting
Support CPU frequency scaling on qcs404.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot
Add a CPU OPP table to qcs404
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/clk/qcom/apcs-msm8916.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
index a6c89a3..2453242 100644
The high frequency pll is required on compatible Qualcomm SoCs to
support the CPU frequency scaling feature.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
There is clock controller functionality in the APCS hardware block of
qcs404 devices similar to msm8916.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 21 +
1 file changed, 13
Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++
1 file changed, 3 insertions
The high frequency pll functionality is required to enable CPU
frequency scaling operation.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch
clock driver source code.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 21 +
1 file changed, 21 insertions(+)
diff --git
a/Documentation/devicetree/bindings/mailbox
appreciate the
maintainer's input on this topic.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
Jorge Ramirez-Ortiz (13):
clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
mbox: qcom: add APCS child device for QCS404
mbox: qcom: replac
Make the output of the high frequency pll a clock provider.
On the QCS404 this PLL controls cpu frequency scaling.
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
Signed-off-by: Jorge Ramirez-Ortiz
---
drivers/clk/qcom/hfpll.c | 10 +-
1 file changed, 9 insertions(+), 1
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