On Tue, Jan 17, 2017 at 12:09 PM, Marc Zyngier wrote:
> On 26/12/16 17:11, Jintack Lim wrote:
>> The ARM architecture defines the EL1 physical timer and the virtual
>> timer, and it is reasonable for an OS to expect to be able to access
>> both. However, the current KVM im
Hi Marc,
On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote:
> On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim
> wrote:
>> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
>> Now VMs are able to use the EL1 physical timer.
>>
>&
On Sun, Jan 29, 2017 at 7:01 AM, Marc Zyngier wrote:
> On Fri, Jan 27 2017 at 01:04:53 AM, Jintack Lim
> wrote:
>> Now that we have a separate structure for timer context, make functions
>> general so that they can work with any timer context, not just the
>
>
Hi Christoffer,
On Mon, Jan 30, 2017 at 9:49 AM, Christoffer Dall
wrote:
> On Thu, Jan 26, 2017 at 08:04:53PM -0500, Jintack Lim wrote:
>> Now that we have a separate structure for timer context, make functions
>> general so that they can work with any timer context, not just
Hi Peter,
On Mon, Jan 30, 2017 at 12:26 PM, Peter Maydell
wrote:
> On 30 January 2017 at 17:08, Jintack Lim wrote:
>> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote:
>>> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I
>>> have at ha
On Mon, Jan 30, 2017 at 9:51 AM, Marc Zyngier wrote:
> On 30/01/17 14:45, Christoffer Dall wrote:
>> On Sun, Jan 29, 2017 at 11:54:05AM +, Marc Zyngier wrote:
>>> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim
>>> wrote:
>>>> Make cntvoff per each tim
On Sun, Jan 29, 2017 at 6:54 AM, Marc Zyngier wrote:
> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim
> wrote:
>> Make cntvoff per each timer context. This is helpful to abstract kvm
>> timer functions to work with timer context without considering timer
>> types
On Mon, Jan 30, 2017 at 1:05 PM, Marc Zyngier wrote:
> On 30/01/17 17:58, Jintack Lim wrote:
>> On Sun, Jan 29, 2017 at 6:54 AM, Marc Zyngier wrote:
>>> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim
>>> wrote:
>>>> Make cntvoff per each timer c
Hi Marc,
On Sun, Jan 29, 2017 at 10:55 AM, Marc Zyngier wrote:
> Hi Jintack,
>
> On Fri, Jan 27 2017 at 01:04:50 AM, Jintack Lim
> wrote:
>> The ARM architecture defines the EL1 physical timer and the virtual timer,
>> and it is reasonable for an OS to expect t
On Wed, Feb 1, 2017 at 3:04 AM, Christoffer Dall
wrote:
> On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote:
>> On Fri, Jan 27 2017 at 01:04:56 AM, Jintack Lim
>> wrote:
>> > Now that we maintain the EL1 physical timer register states of VMs,
>> > up
physical timer
emulation on every entry to the VM and cancel it on exit.
- Change timer_context structure to have cntvoff and restore enable field back
to arch_timer_cpu structure
Jintack Lim (10):
KVM: arm/arm64: Abstract virtual timer context into separate structure
KVM: arm/arm64: Move cntvoff
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.
This is about to become very handy when adding the EL1 physical timer.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
Acked-by
When scheduling a background timer, consider both of the virtual and
physical timer and pick the earliest expiration time.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c| 3 ++-
virt/kvm/arm/arch_timer.c | 53 +++
2 files changed, 42
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c| 37 ++---
include/kvm/arm_arch_timer.h | 2 ++
virt/kvm/arm/arch_timer.c| 2
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c
Add the EL1 physical timer context.
Signed-off-by: Jintack Lim
---
include/kvm/arm_arch_timer.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index f46fa3b..6445a3d 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm
Now that we maintain the EL1 physical timer register states of VMs,
update the physical timer interrupt level along with the virtual one.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/arch_timer.c | 4
1 file changed, 4 insertions(+)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 9 +++--
4 files changed, 25
use the virtual timer since the physical timer is always not
enabled.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/arch_timer.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 89bdb79..1806e5e
make sense.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 3 ---
arch/arm/kvm/arm.c| 1 -
arch/arm64/include/asm/kvm_host.h | 3 ---
include/kvm/arm_arch_timer.h | 9 +++--
virt/kvm/arm/arch_timer.c | 31 +--
virt
Now that we have a separate structure for timer context, make functions
generic so that they can work with any timer context, not just the
virtual timer context. This does not change the virtual timer
functionality.
Signed-off-by: Jintack Lim
Acked-by: Marc Zyngier
---
arch/arm/kvm/arm.c
registers to be able to run the guest hypervisor in
EL1.
Signed-off-by: Jintack Lim
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_host.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64
From: Christoffer Dall
Set up virutal EL2 context to hardware if the guest exception level is
EL2.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a
From: Christoffer Dall
Add a framework to set up the guest's context depending on the guest's
exception level. A chosen context is written to hardware in the lowvisor.
We don't set the virtual EL2 context yet.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
a
traps.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 119 ++
arch/arm64/kvm/sys_regs.h | 7 +++
2 files changed, 126 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 7cef94f..4158f2f 100644
--- a/arch
: Jintack Lim
---
arch/arm64/include/asm/kvm_coproc.h | 2 +-
arch/arm64/kvm/handle_exit.c| 2 +-
arch/arm64/kvm/sys_regs.c | 49 -
arch/arm64/kvm/trace.h | 2 +-
4 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/arch
Forward exceptions due to floating-point register accesses to the guest
hypervisor if it has set CPTR_EL2.TFP bit.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_nested.h | 1 +
arch/arm64/kernel/asm-offsets.c | 1 +
arch/arm64/kvm/handle_exit.c| 3 +++
arch/arm64/kvm
Forward exceptions due to WFI or WFE to the guest hypervisor if the
guest hypervisor has set corresponding virtual HCR_EL2.TWX bits.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_nested.h | 1 +
arch/arm64/kvm/handle_exit.c| 11 ++-
arch/arm64/kvm
Currently, if a vcpu thread tries to change its own active state when
the irq is already in AP list, it'll loop forever. Since the VCPU thread
has already synced back LR state to the struct vgic_irq, let it modify
its own state safely.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/vgic
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
include/kvm/arm_vgic.h | 20
1 file changed, 20 insertions(+)
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 002f092..9a9cb27 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -
scope of the flush operation to only flush shadow
stage 2 page table state of the particular VCPU toggling the caches
instead of the shadow stage 2 state of all possible VCPUs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/mmu.c | 31
Create a mapping from the nested VM's cpu interface to the hardware
virtual cpu interface. This is to allow the nested VM to access virtual
cpu interface directly.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 3 +++
arch/arm/kvm/mmu.c | 5 +
arch/
shadow page table is not valid any more. So ummap it.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 1 +
arch/arm/kvm/arm.c| 1 +
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/kvm_mmu.h | 6
arch/arm64/kvm/mmu-nested.c | 71
Expose physical address of vgic virtual cpu interface.
Signed-off-by: Jintack Lim
---
include/kvm/arm_vgic.h | 1 +
virt/kvm/arm/vgic/vgic-v2.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 5bda20c..05c7811 100644
--- a
remap calls this function with the VM's mmu context.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/mmu.c | 18 +-
arch/arm64/include/asm/kvm_mmu.h | 3 +++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
ind
.
Check if this is the case, and inject a fault if it is.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 7 +++
arch/arm/kvm/mmu.c | 5 +
arch/arm64/include/asm/kvm_mmu.h | 9 +
arch/arm64/kvm/mmu-nested.c
From: Christoffer Dall
Currently, we flush ALL shadow stage-2 page tables on the tlbi
instruction execution. We may be able to do this more efficiently by
considering the vttbr_el2 value of the guest hypervisor, but leave it
for now.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
From: Christoffer Dall
Move this little function to the header files for arm/arm64 so other
code can make use of it directly.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 8
arch/arm/kvm/mmu.c | 8
From: Christoffer Dall
Based on the pseudo-code in the ARM ARM, implement a stage 2 software
page table walker.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 11 ++
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/include/asm/kvm_mmu.h
e sum of offset the host hypervisor initially has for
the VM and virtual offset the guest hypervisor sets for the nested VM.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 6 ++
arch/arm64/include/asm/kvm_emulate.h | 6 ++
virt/kvm/arm/arch_timer.c
Now that everything is ready, we enable nested virtualization by setting
the HCR NV and NV1 bit.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/hyp/switch.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm
From: Christoffer Dall
stage2_flush_xxx functions take a pointer to the kvm struct as the first
parameter but they are never used. Clean this up before modifying mmu
code for nested virtualization support.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/mmu.c | 12
A non-secure EL0 or EL1 read of MPIDR_EL1 should return the value of
VMPIDR_EL2. We emulate this by copying the virtual VMPIDR_EL2 value to
MPIDR_EL1 when entering VM's EL0 or EL1.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 6 ++
1 file changed, 6 insertions(+)
diff --
shadow stage-2 table. Probably we can do smarter with
some sort of rmap structure.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 7
arch/arm/kvm/arm.c | 6 ++-
arch/arm/kvm/mmu.c | 11 +
arch/arm64/include
: Jintack Lim
---
arch/arm64/include/asm/kvm_mmu.h | 3 +++
arch/arm64/kvm/mmu-nested.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index bf94f0c..2ac603d 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch
with the existing
code.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 7
arch/arm/kvm/mmio.c | 12 +++---
arch/arm/kvm/mmu.c | 75
arch/arm64/include/asm
s from the guest
hypervisor's point of view.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 3 ++
arch/arm/kvm/arm.c | 1 +
arch/arm64/include/asm/kvm_emulate.h | 13 -
arch/arm64/include/asm/kvm_host.h| 19 +
arch/arm64/includ
From: Christoffer Dall
Make mmu functions non-static so that we can reuse those functions
to support mmu for the nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/mmu.c | 90 +++-
arch/arm64/include/asm
From: Christoffer Dall
Sometimes when we are invalidating the TLB for a certain S2 MMU
context, this context can also have EL2 context associated with it and
we have to invalidate this too.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c | 6 ++
arch
If we have a pending IRQ for the guest and the guest expects IRQs
to be handled in its virtual EL2 mode (the virtual IMO bit is set)
and it is not already running in virtual EL2 mode, then we have to
emulate an IRQ exception.
Signed-off-by: Jintack Lim
Signed-off-by: Christoffer Dall
---
virt
real hardware irq number if there is a mapping.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 5 ++
arch/arm64/include/asm/kvm_emulate.h | 5 ++
arch/arm64/kvm/context.c | 4 ++
include/kvm/arm_vgic.h | 8 +++
vir
Since vgic state is properly prepared and is pointed by hw_v2_cpu_if,
let's use it to manipulate vgic.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/hyp/vgic-v2-sr.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kv
Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_asm.h | 6 ++--
arch/arm/include/asm/kvm_emulate.h | 4 +++
arch/arm/include/asm/kvm_host.h | 14 ++---
arch/arm/include/asm/kvm_mmu.h | 11 +++
arch/arm/kvm/arm.c
-by: Jintack Lim
---
arch/arm/include/asm/kvm_asm.h| 7 +-
arch/arm/include/asm/kvm_host.h | 26 ---
arch/arm/kvm/arm.c| 34 +
arch/arm/kvm/hyp/switch.c | 5 +-
arch/arm/kvm/hyp/tlb.c| 18 ++---
arch/arm/kvm/mmu.c| 146
From: Christoffer Dall
Now that the vttbr value will be different depending on the VM's
exception level, we set it on each VM entry.
We only have one mmu instance at this point, but there will be
multiple of them when we run nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Ji
Register a device for the virtual interface control block(GICH) access
from the guest hypervisor.
TODO: Get GICH address from DT, which is hardcoded now.
Signed-off-by: Jintack Lim
---
arch/arm64/include/uapi/asm/kvm.h | 6 ++
include/kvm/arm_vgic.h | 5 -
virt/kvm/arm
Emulate GICH interface accesses from the guest hypervisor.
Signed-off-by: Jintack Lim
Signed-off-by: Shih-Wei Li
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/Makefile| 1 +
virt/kvm/arm/vgic/vgic-v2-nested.c | 207 +
2 files changed, 208
From: Christoffer Dall
Inject stage-2 page faults to the guest hypervisor.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/esr.h | 1 +
arch/arm64/kvm/mmu-nested.c | 30 --
2 files changed, 25 insertions(+), 6 deletions
Forward exceptions due to hvc instruction to the guest hypervisor.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_nested.h | 5 +
arch/arm64/kvm/Makefile | 1 +
arch/arm64/kvm/handle_exit.c| 11 +++
arch/arm64/kvm/handle_exit_nested.c | 27
From: Christoffer Dall
If we exit a nested VM with a pending maintenance interrupt from the
GIC, then we need to forward this to the guest hypervisor so that it can
re-sync the appropriate LRs and sample level triggered interrupts again.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack
mc for the psci call. On ARMv8.3, even if EL3 is
not implemented, a smc instruction executed at non-secure EL1 is trapped
to EL2 if HCR_EL2.TSC==1, rather than being treated as UNDEFINED. So,
the host hypervisor can handle this psci call without any confusion.
Signed-off-by: Jintack Lim
---
arch
.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 0f5d21b..19d6a6e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64
Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the guest hypervisor if
it has set the NV1 bit to the virtual HCR_EL2. The guest hypervisor
would set this NV1 bit to run a hypervisor in its VM (i.e. another level
of nested hypervisor).
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm
tware in EL0/EL1 from the guest hypervisor's perspective.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/hyp/switch.c | 10 +++---
arch/arm64/kvm/sys_regs.c | 10 +-
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hy
at it believes to be
a different mode's system register state (for example when preparing to
switch to a VM).
We can leverage the existing sysregs infrastructure to support trapped
accesses to these registers.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/hy
Forward CPACR_EL1 traps to the guest hypervisor if it has configured the
virtual CPTR_EL2 to do so.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 321ecbc..e66f40d
Emulate taking an exception to the guest hypervisor running in the
virtual EL2 as described in ARM ARM AArch64.TakeException().
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 14
arch/arm64/include/asm/kvm_emulate.h | 19 +++
arch/arm64/kvm/Makefile
When HCR.NV bit is set, eret instruction execution in the guest
hypervisor will trap with EC code 0x1A. Let ELR_EL2 and SPSR_EL2 state
from the guest's perspective be restored to the hardware on the next
guest entry.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/esr.h | 1 +
arch/
Forward virtual memory register traps to the guest hypervisor
if it has set corresponding bits to the virtual HCR_EL2.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm
Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 71
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c
index acb4b1e..2e9e386 100644
--- a/arch/arm64/kvm/context.c
+++ b/arch/arm64/kvm
From: Christoffer Dall
When running a nested hypervisor we occasionally have to figure out if
the mode we are switching into is the virtual EL2 mode or a regular
EL0/1 mode.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 6 ++
arch
From: Christoffer Dall
We were not allowing userspace to set a more privileged mode for the VCPU
than EL1, but now that we support nesting with a virtual EL2 mode, do
allow this!
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/guest.c | 2 ++
1 file changed, 2
/arm64: Forward the guest hypervisor's stage 2 permission
faults
KVM: arm64: Emulate TLBI instruction
KVM: arm64: Fixes to toggle_cache for nesting
Jintack Lim (28):
KVM: arm64: Add EL2 execution context for nesting
KVM: arm64: Emulate taking an exception to the guest hypervisor
KV
From: Christoffer Dall
Some bits of the TCR weren't defined and since we're about to use these
in KVM, add these defines.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/pgtable-hwdef.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/
From: Christoffer Dall
Set the initial exception level of the guest to EL2 if nested
virtualization feature is enabled.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/reset.c
From: Christoffer Dall
Add an option that allows nested hypervisor support.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index 6eaf12c..37263ff
registers were happening locally in the shadow array, with no benefit to
software actually running in virtual EL1 at all.
To fix this, simply synchronize the shadow and real EL1 state for these
registers on entry/exit to/from virtual EL2 state.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack
On Mon, Jan 9, 2017 at 10:05 AM, David Hildenbrand wrote:
>
>> Even though this work is not complete (see limitations below), I'd
>> appreciate
>> early feedback on this RFC. Specifically, I'm interested in:
>> - Is it better to have a kernel config or to make it configurable at
>> runtime?
>
>
>
On Mon, Jan 9, 2017 at 7:02 AM, Christoffer Dall
wrote:
> On Mon, Dec 26, 2016 at 12:12:02PM -0500, Jintack Lim wrote:
>> Initialize the emulated EL1 physical timer with the default irq number.
>>
>> Signed-off-by: Jintack Lim
>> ---
>> arch/arm/kvm/reset.c
On Mon, Jan 9, 2017 at 7:14 AM, Christoffer Dall
wrote:
> On Mon, Dec 26, 2016 at 12:12:04PM -0500, Jintack Lim wrote:
>> Now that we maintain the EL1 physical timer register states of the VM,
>> update the physical timer interrupt level along with the virtual one.
>>
>
On Mon, Jan 9, 2017 at 7:16 AM, Christoffer Dall
wrote:
> On Mon, Dec 26, 2016 at 12:12:06PM -0500, Jintack Lim wrote:
>> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
>> Now the VM is able to use the EL1 physical timer.
>>
>> Signed-off-by: J
Hi Christoffer,
thanks for the review!
On Mon, Jan 9, 2017 at 7:13 AM, Christoffer Dall
wrote:
> On Mon, Dec 26, 2016 at 12:12:05PM -0500, Jintack Lim wrote:
>> Set a background timer for the EL1 physical timer emulation while VMs are
>> running, so that VMs get interrupts f
imer_cpu structure
Jintack Lim (10):
KVM: arm/arm64: Abstract virtual timer context into separate structure
KVM: arm/arm64: Move cntvoff to each timer context
KVM: arm/arm64: Decouple kvm timer functions from virtual timer
KVM: arm/arm64: Add the EL1 physical timer context
KVM: arm/arm64: In
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c| 32 +---
include/kvm/arm_arch_timer.h | 2 ++
virt/kvm/arm/arch_timer.c| 2
use the virtual timer since the physical timer is always not
enabled.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/arch_timer.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index d3925e2
Add the EL1 physical timer context.
Signed-off-by: Jintack Lim
---
include/kvm/arm_arch_timer.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index d921d20..69f648b 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm
Now that we have a separate structure for timer context, make functions
general so that they can work with any timer context, not just the
virtual timer context. This does not change the virtual timer
functionality.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c | 2 +-
include
make sense.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 6 +++---
arch/arm64/include/asm/kvm_host.h | 4 ++--
include/kvm/arm_arch_timer.h | 8 +++-
virt/kvm/arm/arch_timer.c | 26 --
virt/kvm/arm/hyp/timer-sr.c | 3 +--
5
Now that we maintain the EL1 physical timer register states of VMs,
update the physical timer interrupt level along with the virtual one.
Note that the emulated EL1 physical timer is not mapped to any hardware
timer, so we call a proper vgic function.
Signed-off-by: Jintack Lim
---
virt/kvm
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c
When scheduling a background timer, consider both of the virtual and
physical timer and pick the earliest expiration time.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c| 3 ++-
virt/kvm/arm/arch_timer.c | 55 ---
2 files changed, 44
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.
This is about to become very handy when adding the EL1 physical timer.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 9 +++--
4 files changed, 25
Add the EL1 physical timer context.
Signed-off-by: Jintack Lim
---
include/kvm/arm_arch_timer.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index cf84145..d21652a 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm
timer interrupts
while they are runnable. But they won't get interrupts once vcpus go to
sleep since we don't have code to wake vcpus up on the emulated physical
timer expiration yet.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c| 3 +-
virt/kvm/arm/arch_ti
-off-by: Jintack Lim
---
virt/kvm/arm/arch_timer.c | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index aa7e243..be8d953 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 12 ++--
4 files changed
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now the VM is able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c| 35 ---
include/kvm/arm_arch_timer.h | 3 +++
virt/kvm/arm/arch_timer.c
p-and-emulate.
Jintack Lim (8):
KVM: arm/arm64: Abstract virtual timer context into separate structure
KVM: arm/arm64: Decouple kvm timer functions from virtual timer
KVM: arm/arm64: Add the EL1 physical timer context
KVM: arm/arm64: Initialize the emulated EL1 physical timer
KVM: arm64: Add th
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