On Tue, Oct 17, 2017 at 4:14 AM, Christoph Hellwig wrote:
> Just took a quick look over this and I basically agree with the comments
> from Robin.
>
> What I don't understand is why you're even trying to do all these
> hacky things.
>
> It seems like the controller should simply set dma_pfn_offset
On Tue, Oct 17, 2017 at 4:24 PM, Rob Herring wrote:
> On Wed, Oct 11, 2017 at 06:34:22PM -0400, Jim Quinlan wrote:
>> The DT bindings description of the Brcmstb PCIe device is described. This
>> node can be used by almost all Broadcom settop box chips, using
>> AR
On Mon, Oct 23, 2017 at 5:06 AM, David Laight wrote:
> From: Jim Quinlan
>> Sent: 20 October 2017 16:28
>> On Fri, Oct 20, 2017 at 10:57 AM, Christoph Hellwig wrote:
>> > On Fri, Oct 20, 2017 at 10:41:56AM -0400, Jim Quinlan wrote:
>> >> I am not sure I unders
The DT bindings description of the Brcmstb PCIe device is described. This
node can be used by almost all Broadcom settop box chips, using
ARM, ARM64, or MIPS CPU architectures.
Signed-off-by: Jim Quinlan
---
.../devicetree/bindings/pci/brcmstb-pci.txt| 63 ++
1 file
This patch series adds support for the Broadcom Settopbox PCIe host
controller. It is targeted to Broadcom Settopbox chips running on
ARM, ARM64, and MIPS platforms.
Changes from V1:
* Patch brcmstb-add-memory-API:
- fix DT_PROP_DATA_TO_U32 macro.
- dropped one EXPORT_SYMBOL, changed the oth
Adds the Kconfig hooks to enable the Broadcom STB PCIe root complex
driver for Broadcom MIPS systems.
Signed-off-by: Jim Quinlan
---
arch/mips/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cb7fcc4..83ba54d 100644
--- a/arch/mips
ma_ops. The
wrappers translate the dma addresses before/after invoking
the arch_dma_ops, as appropriate.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/Makefile | 3 +-
drivers/pci/host/pci-brcmstb-dma.c | 317 +
drivers/pci/host/pci-brcmstb.c
Adds the PCIe nodes for the Broadcom STB PCIe root complex.
Signed-off-by: Jim Quinlan
---
arch/mips/boot/dts/brcm/bcm7425.dtsi | 25 +
arch/mips/boot/dts/brcm/bcm7435.dtsi | 26 ++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 4
arch
internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/Kconfig | 12 ++
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci
Add MIPS as an arch that supports PCI_MSI_IRQ_DOMAIN and add
generation of msi.h in the MIPS arch.
Signed-off-by: Jim Quinlan
---
arch/mips/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/Kbuild b
regions.
We cannot use memblock here or anything like what Linux provides
because it collapses adjacent regions within a larger block, and here
we actually need per-memory controller addresses and sizes, which is
why we resort to manual DT parsing.
Signed-off-by: Jim Quinlan
---
drivers/soc/bcm
by the PCIe controller. It cannot be used or shared
by any other HW. As such, the small amount of code for this
controller is included in this driver as there is little upside to put
it elsewhere.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/Kconfig |8 +
drivers/pci/host/Makefile
On Tue, Oct 24, 2017 at 8:23 PM, Florian Fainelli wrote:
> Hi Jim,
>
> On 10/24/2017 11:15 AM, Jim Quinlan wrote:
>> +#elif defined(CONFIG_MIPS)
>> +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
>> +{
>> + /* The logic here is fairly simple an
On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli wrote:
> Hi Jim,
>
> On 10/24/2017 11:15 AM, Jim Quinlan wrote:
>> This commit adds MSI to the Broadcom STB PCIe host controller. It does
>> not add MSIX since that functionality is not in the HW. The MSI
>> contr
On Wed, Oct 25, 2017 at 9:22 AM, Bjorn Helgaas wrote:
> On Tue, Oct 24, 2017 at 02:15:47PM -0400, Jim Quinlan wrote:
>> This commit adds MSI to the Broadcom STB PCIe host controller. It does
>> not add MSIX since that functiostbsrvnality is not in the HW. The MSI
>> con
On Wed, Oct 25, 2017 at 5:46 AM, David Laight wrote:
> From: Jim QuinlanPCIE_IPROC_MSI
>> Sent: 24 October 2017 19:16
>> The Broadcom STB PCIe host controller is intimately related to the
>> memory subsystem. This close relationship adds complexity to how cpu
>> system memory is mapped to PCIe me
rface. This is a local interface
>> only accessible by the PCIe controller. It cannot be used or shared
>> by any other HW. As such, the small amount of code for this
>> controller is included in this driver as there is little upside to put
>> it elsewhere.
>>
>>
On Wed, Oct 25, 2017 at 4:16 PM, Bjorn Helgaas wrote:
> On Wed, Oct 25, 2017 at 11:40:47AM -0700, Scott Branden wrote:
>> Hi Bjorn,
>>
>>
>> On 17-10-25 10:23 AM, Bjorn Helgaas wrote:
>> >[+cc Ray, Scott, Jon]
>> >
>> >On Wed, Oct 25, 2017 at
r(), but added code in brcm_dma_supported()
- put all of the notifier code in one compilation unit.
Florian Fainelli (1):
SOC: brcmstb: add memory API
Jim Quinlan (7):
dt-bindings: pci: Add DT docs for Brcmstb PCIe device
PCI: brcmstb: Add Broadcom STB PCIe host controller driver
PCI:
regions.
We cannot use memblock here or anything like what Linux provides
because it collapses adjacent regions within a larger block, and here
we actually need per-memory controller addresses and sizes, which is
why we resort to manual DT parsing.
Signed-off-by: Jim Quinlan
---
drivers/soc/bcm
The DT bindings description of the Brcmstb PCIe device is described. This
node can be used by almost all Broadcom settop box chips, using
ARM, ARM64, or MIPS CPU architectures.
Signed-off-by: Jim Quinlan
---
.../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++
1 file
Adds the Kconfig hooks to enable the Broadcom STB PCIe root complex
driver for Broadcom MIPS systems.
Signed-off-by: Jim Quinlan
---
arch/mips/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cb7fcc4..83ba54d 100644
--- a/arch/mips
Adds the PCIe nodes for the Broadcom STB PCIe root complex.
Signed-off-by: Jim Quinlan
---
arch/mips/boot/dts/brcm/bcm7425.dtsi | 26 ++
arch/mips/boot/dts/brcm/bcm7435.dtsi | 27 +++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 4
internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/pcie-brcmstb.c | 372 ++--
1 file changed, 359 insertions
ma_ops. The
wrappers translate the dma addresses before/after invoking
the arch_dma_ops, as appropriate.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/Makefile | 4 +-
drivers/pci/host/pcie-brcmstb-dma.c | 319
drivers/pci/host/pcie-brcmstb.c |
Add MIPS as an arch that supports PCI_MSI_IRQ_DOMAIN and add
generation of msi.h in the MIPS arch.
Signed-off-by: Jim Quinlan
---
arch/mips/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/Kbuild b
by the PCIe controller. It cannot be used or shared
by any other HW. As such, the small amount of code for this
controller is included in this driver as there is little upside to put
it elsewhere.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/Kconfig|9 +
drivers/pci/host
On Wed, Oct 18, 2017 at 2:53 AM, Christoph Hellwig wrote:
> On Tue, Oct 17, 2017 at 12:11:55PM -0400, Jim Quinlan wrote:
>> My understanding is that dma_pfn_offset is that it is a single
>> constant offset from RAM, in our case, to map to PCIe space.
>
> Yes.
>
>>
On Thu, Oct 19, 2017 at 5:16 AM, Christoph Hellwig wrote:
> On Wed, Oct 18, 2017 at 10:41:17AM -0400, Jim Quinlan wrote:
>> That's what brcm_to_{pci,cpu} are for -- they keep a list of the
>> dma-ranges given in the PCIe DT node, and translate from system memory
>&
On Thu, Oct 19, 2017 at 5:49 PM, Rob Herring wrote:
> On Tue, Oct 17, 2017 at 5:42 PM, Jim Quinlan wrote:
>> On Tue, Oct 17, 2017 at 4:24 PM, Rob Herring wrote:
>>> On Wed, Oct 11, 2017 at 06:34:22PM -0400, Jim Quinlan wrote:
>>>> The DT bindings description
On Fri, Jan 26, 2018 at 2:53 AM, Christoph Hellwig wrote:
> On Wed, Jan 24, 2018 at 12:04:58PM -0800, Florian Fainelli wrote:
>> This looks nicer than the current shape, but this still requires to
>> register a PCI fixup to override phys_to_dma() and dma_to_phys(), and it
>> would appear that you
ot;, "supply-names" to "xyz-supply"
* Patch removed: export-symbol-arch_setup_dma_ops [4/9]
* Patch brcmstb-add-dma-ranges:
- use get_dma_ops(); also use a const dma_map_ops structure.
- rewrite map_sg(), unmap_sg(), other calls like syng_sg_*()
- omit brcm_mapping_error(), but
regions.
We cannot use memblock here or anything like what Linux provides
because it collapses adjacent regions within a larger block, and here
we actually need per-memory controller addresses and sizes, which is
why we resort to manual DT parsing.
Signed-off-by: Jim Quinlan
Conflicts
Add MIPS as an arch that supports PCI_MSI_IRQ_DOMAIN and add
generation of msi.h in the MIPS arch.
Signed-off-by: Jim Quinlan
---
arch/mips/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/Kbuild b
Adds the Kconfig hooks to enable the Broadcom STB PCIe root complex
driver for Broadcom MIPS systems.
Signed-off-by: Jim Quinlan
---
arch/mips/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 350a990..fe17361 100644
--- a/arch/mips
Adds the PCIe nodes for the Broadcom STB PCIe root complex.
Signed-off-by: Jim Quinlan
---
arch/mips/boot/dts/brcm/bcm7425.dtsi | 26 ++
arch/mips/boot/dts/brcm/bcm7435.dtsi | 27 +++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 4
internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/pcie-brcmstb.c | 374 +---
1 file changed, 353 insertions
by the PCIe controller. It cannot be used or shared
by any other HW. As such, the small amount of code for this
controller is included in this driver as there is little upside to put
it elsewhere.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/Kconfig|9 +
drivers/pci/host
ma_ops. The
wrappers translate the dma addresses before/after invoking
the arch_dma_ops, as appropriate.
Signed-off-by: Jim Quinlan
---
drivers/pci/host/pcie-brcmstb.c | 420 +++-
1 file changed, 411 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/host/
The DT bindings description of the Brcmstb PCIe device is described. This
node can be used by almost all Broadcom settop box chips, using
ARM, ARM64, or MIPS CPU architectures.
Signed-off-by: Jim Quinlan
---
.../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++
1 file
On Wed, Sep 26, 2018 at 6:07 PM Paul Burton wrote:
>
> Hi Jim,
>
> On Wed, Sep 19, 2018 at 10:32:01AM -0400, Jim Quinlan wrote:
> > The design of the Broadcom PCIe RC controller requires us to remap its
> > DMA addresses for inbound traffic. We do this by modifyin
On Thu, Apr 8, 2021 at 12:20 PM Rob Herring wrote:
>
> On Tue, Apr 06, 2021 at 02:25:49PM -0400, Jim Quinlan wrote:
> > On Tue, Apr 6, 2021 at 1:32 PM Mark Brown wrote:
> > >
> > > On Tue, Apr 06, 2021 at 01:26:51PM -0400, Jim Quinlan wrote:
> > > >
Just like dma_pfn_offset, another offset is added to
the dma/phys translation if there happen to be multiple
regions that have different mapping offsets.
Signed-off-by: Jim Quinlan
---
include/linux/dma-direct.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/linux
From: Jim Quinlan
Some STB chips have a special purpose reset controller named
RESCAL (reset calibration). This commit adds the control
of RESCAL as well as the ability to start and stop its
operation for PCIe HW.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 81
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips:
7278, 7216, 7211 (STB version of RPi4).
- add new property 'brcm,scb-sizes'
- add new property 'resets'
- add new property 'reset-names'
- allow 'ranges' and 'dma-ranges
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI
interrupts; the MSIs are in a register that also contains
unrelated interrupts. In addition, the interrupts lie in
bits [31..24] for these legacy chips. This commit provides
commont code for both legacy and non
n the amount of memory each controller supports.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/Kconfig| 1 +
drivers/pci/controller/pcie-brcmstb.c | 67 ---
2 files changed, 50 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/Kconfi
Currently there is only one caller of of_dma_get_range().
A struct device *dev param is needed For implementing
multiple dma offsets. This function will still work
if dev == NULL.
Signed-off-by: Jim Quinlan
---
drivers/of/address.c| 4 +++-
drivers/of/device.c | 2 +-
drivers/of
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the
default value to ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller
The device variable 'dma_pfn_offset' is used to do a single
linear map between cpu addrs and dma addrs. The variable
'dma_map' is added to struct device to point to an array
of multiple offsets which is required for some devices.
Signed-off-by: Jim Quinlan
---
drivers/of/a
From: Jim Quinlan
The PERST bit was moved to a different register in 7278-type
STB chips. In addition, the polarity of the bit was also
changed; for other chips writing a 1 specified assert; for
7278-type chips, writing a 0 specifies assert.
Signal-wise, PERST is an asserted-low signal
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies
per chip. The 2711 family requires 128B whereas other devices
can employ 512. The assignment is complicated by the fact
that the values for this two-bit field have different meanings;
Value Type_Generic
Just like dma_pfn_offset, another offset is added to
the dma/phys translation if there happen to be multiple
regions that have different mapping offsets.
Signed-off-by: Jim Quinlan
---
arch/arm/include/asm/dma-mapping.h | 17 ++---
1 file changed, 14 insertions(+), 3 deletions
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3,
and S5 suspend and resume. This commit enables the PCIe
driver to do so.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 49 +++
1 file changed, 49 insertions(+)
diff
-46522-5-git-send-email-jim2101...@gmail.com/
Jim Quinlan (15):
PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB
ahci_brcm: fix use of BCM7216 reset controller
dt-bindings: PCI: Add bindings for more Brcmstb chips
PCI: brcmstb: Add compatibily of other chips
PCI: brcmstb: Add suspend and resum
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips.
Some of the register locations, shifts, and masks are different
for certain chips, requiring the use of different constants based
on of_id.
We would like to add the following at this time to the match list
but
From: Jim Quinlan
A reset controller "rescal" is shared between the AHCI driver
and the PCIe driver for the BrcmSTB 7216 chip. The code is
modified to allow this sharing and to deassert() properly.
Signed-off-by: Jim Quinlan
---
drivers/ata/ahci_brcm.c | 14 +-
1 file
On Wed, May 20, 2020 at 1:43 AM Greg Kroah-Hartman
wrote:
>
> On Tue, May 19, 2020 at 04:34:07PM -0400, Jim Quinlan wrote:
> > diff --git a/include/linux/device.h b/include/linux/device.h
> > index ac8e37cd716a..6cd916860b5f 100644
> > --- a/include/linux/device.h
> >
On Wed, May 20, 2020 at 9:44 AM Nicolas Saenz Julienne
wrote:
>
> On Tue, 2020-05-19 at 16:34 -0400, Jim Quinlan wrote:
> > From: Jim Quinlan
> >
> > The proper value of the parameter SCB_MAX_BURST_SIZE varies
> > per chip. The 2711 family requires 128B whereas ot
On Wed, May 20, 2020 at 7:51 AM Nicolas Saenz Julienne
wrote:
>
> Hi Jim,
>
> On Tue, 2020-05-19 at 16:34 -0400, Jim Quinlan wrote:
> > From: Jim Quinlan
> >
> > Add in compatibility strings and code for three Broadcom STB chips.
> > Some of the regis
Sorry, I meant to put you on the to-list for all patches. The last
time I sent out this many patches using a collective cc-list for all
patches I was told to reduce my cc-list.
Jim
On Wed, May 20, 2020 at 1:42 PM Christoph Hellwig wrote:
>
> If you don't Cc me on the whole series I have absolut
On Wed, May 20, 2020 at 7:51 AM Nicolas Saenz Julienne
wrote:
>
> Hi Jim,
>
> On Tue, 2020-05-19 at 16:34 -0400, Jim Quinlan wrote:
> > From: Jim Quinlan
> >
> > Add in compatibility strings and code for three Broadcom STB chips.
> > Some of the regis
On Wed, May 20, 2020 at 3:27 AM Philipp Zabel wrote:
>
> Hi Jim,
>
> On Tue, May 19, 2020 at 04:34:05PM -0400, Jim Quinlan wrote:
> > From: Jim Quinlan
> >
> > Some STB chips have a special purpose reset controller named
> > RESCAL (reset calibration). This c
fls64
On Sat, Aug 1, 2020 at 1:39 PM Nicolas Saenz Julienne
wrote:
>
> Hi Jim,
>
> On Fri, 2020-07-24 at 16:33 -0400, Jim Quinlan wrote:
> > The Raspberry Pi (RPI) is currently the only chip using this driver
> > (pcie-brcmstb.c). There, only one memory contro
convert it to a
proper 16 bit unsigned integer.
Signed-off-by: Jim Quinlan
---
arch/mips/include/asm/uasm.h | 2 +-
arch/mips/mm/uasm-micromips.c | 2 +-
arch/mips/mm/uasm-mips.c | 2 +-
arch/mips/mm/uasm.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/
ommit message, s/msg/message/, and remove extra WS on
"dt-bindings" commit (Sudeep)
-- Change interrupt name to "message-serviced", move irq assignent to end
of function. (Sudeep)
v1 -- original.
Jim Quinlan (2):
dt-bindings: arm: Add optional interrupt to smc
In normal use of smc/hvc transport in SCMI the message completion is
indicated by the return of the SMC call. This commit provides for an
optional interrupt named "a2p" which is used instead to
indicate the completion of a message.
Signed-off-by: Jim Quinlan
---
Documentation/
Signed-off-by: Jim Quinlan
---
drivers/firmware/arm_scmi/smc.c | 38 -
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c
index 82a82a5dc86a..fd41d436e34b 100644
--- a/drivers/firmware/arm_
On Mon, Dec 7, 2020 at 2:01 PM Rob Herring wrote:
>
> On Thu, Nov 12, 2020 at 12:56:26PM -0500, Jim Quinlan wrote:
> > In normal use of smc/hvc transport in SCMI the message completion is
> > indicated by the return of the SMC call. This commit provides for an
> >
On Tue, Mar 30, 2021 at 11:30 AM Mark Brown wrote:
>10.22.8.121
> On Tue, Mar 30, 2021 at 10:08:16AM -0500, Rob Herring wrote:
> > On Fri, Mar 26, 2021 at 03:18:59PM -0400, Jim Quinlan wrote:
>
> > > +pcie-ep@0,0 {
> > > +
On Mon, Mar 29, 2021 at 12:25 PM Mark Brown
w./lib/python3.6/site-packages/dtschema/schemasrote:
>
> On Fri, Mar 26, 2021 at 03:19:00PM -0400, Jim Quinlan wrote:
>
> > + /* Now look for regulator supply properties */
> > + for_each_prope
/* Pmap_idx to avs pmap number */
const uint8_t pmap_idx_to_avs_id[20];
On Mon, Mar 29, 2021 at 1:16 PM Mark Brown wrote:
>
> On Mon, Mar 29, 2021 at 12:39:50PM -0400, Jim Quinlan wrote:
> > On Mon, Mar 29, 2021 at 12:25 PM Mark Brown
>
> > > Here you are fig
g probe, suspend, and resume.
-- 7216 type SOCs have additional error reporting HW and a
panic handler is added to dump its info.
-- A missing return value check is added.
Jim Quinlan (6):
dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
PCI: brcmstb: Add control of
r property in the pcie EP subnode such as
"vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
file at
https://github.com/devicetree-org/dt-schema/pull/54
Signed-off-by: Jim Quinlan
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 6 ++
1 file changed, 6
Control of EP regulators by the RC is needed because of the chicken-and-egg
situation: although the regulator is "owned" by the EP and would be best
handled on its driver, the EP cannot be discovered and probed unless its
regulator is already turned on.
Signed-off-by: Jim Quinlan
--
.pcie: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 122 ++
1 file changed, 122 insertions(+)
diff --
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 58 +++
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/pci
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie
The check was missing on PCIe resume.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Fixes: 8195b7417018 ("PCI: brcmstb: Add suspend and resume pm_ops")
---
drivers/pci/controller/pcie-brcmstb.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/d
On Fri, Mar 26, 2021 at 4:11 PM Bjorn Helgaas wrote:
>
> On Fri, Mar 26, 2021 at 03:19:00PM -0400, Jim Quinlan wrote:
> > Control of EP regulators by the RC is needed because of the chicken-and-egg
>
> Can you expand "EP"? Not sure if this refers to "endpoint&
On Tue, Apr 6, 2021 at 12:34 PM Mark Brown wrote:
>
> On Thu, Apr 01, 2021 at 05:21:43PM -0400, Jim Quinlan wrote:
>
> > + /* Look for specific pcie regulators in the RC DT node. */
> > + for_each_property_of_node(np, pp) {
> > +
On Tue, Apr 6, 2021 at 12:47 PM Mark Brown wrote:
>
> On Thu, Apr 01, 2021 at 05:21:42PM -0400, Jim Quinlan wrote:
> > Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> > allows optional regulators to be attached and controlled by the PCIe RC
On Tue, Apr 6, 2021 at 1:23 PM Mark Brown wrote:
>
> On Tue, Apr 06, 2021 at 12:59:16PM -0400, Jim Quinlan wrote:
> > On Tue, Apr 6, 2021 at 12:34 PM Mark Brown wrote:
> > > On Thu, Apr 01, 2021 at 05:21:43PM -0400, Jim Quinlan wrote:
>
> > > This is broken, th
On Tue, Apr 6, 2021 at 1:32 PM Mark Brown wrote:
>
> On Tue, Apr 06, 2021 at 01:26:51PM -0400, Jim Quinlan wrote:
> > On Tue, Apr 6, 2021 at 12:47 PM Mark Brown wrote:
>
> > > No great problem with having these in the controller node (assming it
> > > accurately
r property in the pcie EP subnode such as
"vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
file at
https://github.com/devicetree-org/dt-schema/pull/54
Signed-off-by: Jim Quinlan
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4
1 file changed, 4
Check for failure of clk_prepare_enable() on device resume.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Fixes: 8195b7417018 ("PCI: brcmstb: Add suspend and resume pm_ops")
---
drivers/pci/controller/pcie-brcmstb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
di
for fixed regulators that may power the EP device.
-- The brcmstb RC driver is modified to control these regulators
during probe, suspend, and resume.
-- 7216 type SOCs have additional error reporting HW and a
panic handler is added to dump its info.
-- A missing return value check i
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 58 +++
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/pci
and would be best handled by its driver, the device cannot be discovered
and probed unless its regulator is already turned on.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 83 +--
1 file changed, 78 insertions(+), 5 deletions(-)
diff --git a/d
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie
.pcie: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 122 ++
1 file changed, 122 insertions(+)
diff --
On Fri, Nov 13, 2020 at 10:12 AM Jim Quinlan wrote:
>
> On Fri, Nov 13, 2020 at 9:36 AM Sudeep Holla wrote:
> >
> > On Fri, Nov 13, 2020 at 09:26:43AM -0500, Jim Quinlan wrote:
> > > Hi, these are fast calls. Regards, Jim
> > >
> > >
> > &g
On Fri, Nov 20, 2020 at 6:14 AM Sudeep Holla wrote:
>
> On Thu, Nov 19, 2020 at 01:34:18PM -0500, Jim Quinlan wrote:
> > On Fri, Nov 13, 2020 at 10:12 AM Jim Quinlan
> > wrote:
> > >
> > > On Fri, Nov 13, 2020 at 9:36 AM Sudeep Holla wrote:
> > >
Quite similar to the regulator bindings found in "rockchip-pcie-host.txt",
this allows optional regulators to be attached and controlled by the
PCIe RC driver.
Signed-off-by: Jim Quinlan
---
.../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12
1 file changed, 12
reporting HW and a
panic handler is added to dump its info.
-- A missing return value check is added.
Jim Quinlan (6):
dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
PCI: brcmstb: Add control of EP voltage regulator(s)
PCI: brcmstb: Do not turn off regulators if EP can
This distinction is required for an imminent commit.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index cbdb315d4b2f
The check was missing on PCIe resume.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c
b/drivers/pci/controller/pcie-brcmstb.c
index 3983d6c80769..64cf534e44d0
If any downstream device may wake up during S2/S3 suspend, we do not want
to turn off its power when suspending.
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 58 +++
1 file changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/pci
.pcie: Error: Mem Acc: 32bit, Read, @0x3800
brcm-pcie 8b2.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0
Signed-off-by: Jim Quinlan
---
drivers/pci/controller/pcie-brcmstb.c | 124 ++
1 file changed, 124 insertions(+)
diff --git a/drivers/pci/controller
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