On Sat, Oct 20, 2018 at 3:22 PM, KarimAllah Ahmed wrote:
> Read the data directly from guest memory instead of the map->read->unmap
> sequence. This also avoids using kvm_vcpu_gpa_to_page() and kmap() which
> assumes that there is a "struct page" for guest memory.
>
On Sat, Oct 20, 2018 at 3:22 PM, KarimAllah Ahmed wrote:
> Copy the VMCS12 directly from guest memory instead of the map->copy->unmap
> sequence. This also avoids using kvm_vcpu_gpa_to_page() and kmap() which
> assumes that there is a "struct page" for guest memory.
>
> Signed-off-by: KarimAllah A
On Sat, Oct 20, 2018 at 3:22 PM, KarimAllah Ahmed wrote:
> Use kvm_vcpu_map when mapping the L1 MSR bitmap since using
> kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
> a "struct page".
>
> Signed-off-by: KarimAllah Ahmed
> ---
> v1 -> v2:
> - Do not change the lifecy
On Wed, Jul 18, 2018 at 10:55 AM, Radim Krčmář wrote:
>> + vmx->nested.nested_run_pending = 1;
>
> This is not necessary. We're only copying state and do not add anything
> that would be lost on a nested VM exit without prior VM entry.
If nested_run_pending is blindly set on restore, then p
No complaints here!
On Thu, Mar 1, 2018 at 7:24 AM, Raslan, KarimAllah wrote:
> Jim/Paolo/Radim,
>
> Any complains about the current API? (introduced in 4/10)
>
> I have more patches on top and I would like to ensure that this is
> agreed upon at least before sending more revisions/patches.
>
> A
or treatment of SMIs and SMM is
active, but it's not clear what happens with the default treatment of
SMIs and SMM.
On Mon, Apr 16, 2018 at 10:15 AM, Raslan, KarimAllah wrote:
> On Mon, 2018-04-16 at 09:22 -0700, Jim Mattson wrote:
>> On Thu, Apr 12, 2018 at 8:12 AM, KarimAllah Ahmed
On Fri, Apr 27, 2018 at 3:03 AM, Paolo Bonzini wrote:
> On 27/04/2018 00:28, Jim Mattson wrote:
>> The other thing that comes to mind is that there are some new fields
>> in the VMCS12 since I first implemented this. One potentially
>> troublesome field is the VMX preemption
Since these pages are typically not used, can we allocate them conditionally?
On Fri, May 11, 2018 at 8:39 AM, Konrad Rzeszutek Wilk
wrote:
>> /*
>> - * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
>> - * for I/O port accesses.
>> + * Merging of IO bitm
I'd prefer to let the kvm module have the final say as to whether or
not to allow userspace to do this.
On Fri, May 11, 2018 at 8:43 AM, Konrad Rzeszutek Wilk
wrote:
> On Fri, May 11, 2018 at 11:42:46AM -0400, Konrad Rzeszutek Wilk wrote:
>> On Mon, Apr 16, 2018 at 10:46:01PM -0700, Wanpeng Li wr
This does seem to allow a DoS from userspace if userspace prefers it.
That doesn't seem wise.
On Fri, May 11, 2018 at 8:44 AM, Konrad Rzeszutek Wilk
wrote:
> On Mon, Apr 16, 2018 at 10:46:02PM -0700, Wanpeng Li wrote:
>> From: Wanpeng Li
>>
>> Tim Shearer reported that "There is a guest which is
On Thu, Aug 17, 2017 at 9:37 AM Paolo Bonzini wrote:
>
> There is currently some confusion between nested and L1 GPAs. The
> assignment to "direct" in kvm_mmu_page_fault tries to fix that, but
> it is not enough. What this patch does is fence off the MMIO cache
> completely when using shadow nes
On Fri, Jan 25, 2019 at 9:52 AM Paolo Bonzini wrote:
>
> On 21/01/19 13:48, Alexander Popov wrote:
> > The single-step debugging of KVM guests on x86 is broken: if we run
> > gdb 'stepi' command at the breakpoint when the guest interrupts are
> > enabled, RIP always jumps to native_apic_mem_write(
HOST_RSP= 0x00006c14,
> HOST_RIP= 0x6c16,
> + HOST_IA32_S_CET = 0x6c18,
> + HOST_SSP= 0x6c1a,
> + HOST_INTR_SSP_TABL_ADDR = 0x6c1c
> };
>
> /*
> --
> 2.17.1
Reviewed-by: Jim Mattson
On Mon, Feb 25, 2019 at 10:32 PM Yang Weijiang wrote:
>
> Guest queries CET SHSTK and IBT support by CPUID.(EAX=0x7,ECX=0),
> in return, ECX[bit 7] corresponds to SHSTK feature, and EDX[bit 20]
> corresponds to IBT feature.
> CR4.CET[bit 23] is CET master enable bit, it controls CET feature
> avai
o limiting the
> number of ASIDs consumed by the guest.
>
> Signed-off-by: Sean Christopherson
I always thought this was a bizarre one-off restriction.
Reviewed-by: Jim Mattson
Babu Moger
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
if/when it showed up in the kernel on AMD hardware.
>
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
On Tue, Feb 23, 2021 at 2:51 PM Sean Christopherson wrote:
>
> On Fri, Feb 19, 2021, David Edmondson wrote:
> > If the VM entry/exit controls for loading/saving MSR_EFER are either
> > not available (an older processor or explicitly disabled) or not
> > used (host and guest values are the same), r
On Fri, Feb 19, 2021 at 6:46 AM David Edmondson
wrote:
>
> If the VM entry/exit controls for loading/saving MSR_EFER are either
> not available (an older processor or explicitly disabled) or not
> used (host and guest values are the same), reading GUEST_IA32_EFER
> from the VMCS returns an inaccur
1/20/21 3:45 PM, Babu Moger wrote:
> >>>
> >>>
> >>> On 1/20/21 3:14 PM, Jim Mattson wrote:
> >>>> On Tue, Jan 19, 2021 at 3:45 PM Babu Moger wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>
On Thu, Feb 18, 2021 at 8:35 AM Sean Christopherson wrote:
>
> On Thu, Feb 18, 2021, Paolo Bonzini wrote:
> > On 18/02/21 13:56, David Edmondson wrote:
> > > On Thursday, 2021-02-18 at 12:54:52 +01, Paolo Bonzini wrote:
> > >
> > > > On 18/02/21 11:04, David Edmondson wrote:
> > > > > When dumping
isolation_ucodes[] table so that these parts benefit from Andi's
optimization in commit 9b545c04abd4f ("perf/x86/kvm: Avoid unnecessary
work in guest filtering").
Signed-off-by: Jim Mattson
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Cc: M
On a host that suffers from pebs_no_isolation, perf_guest_get_msrs()
adds an entry to cpuc->guest_switch_msrs for
MSR_IA32_PEBS_ENABLE. Kvm's atomic_switch_perf_msrs() is the only
caller of perf_guest_get_msrs(). If atomic_switch_perf_msrs() finds an
entry for MSR_IA32_PEBS_ENABLE in cpuc->guest_sw
On Wed, Jul 29, 2020 at 2:06 AM Alexander Graf wrote:
>
>
>
> On 28.07.20 19:13, Jim Mattson wrote:
> > This sounds similar to Peter Hornyack's RFC from 5 years ago:
> > https://www.mail-archive.com/kvm@vger.kernel.org/msg124448.html.
>
> Yeah, looks very simi
On Tue, Jul 28, 2020 at 11:24 PM Haiwei Li wrote:
>
> From: Haiwei Li
>
> The reason output of 'perf kvm stat report --event=vmexit' is uppercase
> on VMX and lowercase on SVM.
>
> To be consistent with VMX, convert lowercase to uppercase.
>
> Signed-off-by: Haiwei Li
Please don't do this. It b
On Wed, Jul 29, 2020 at 1:29 PM Alexander Graf wrote:
> Meanwhile, I have cleaned up Karim's old patch to add allow listing to
> KVM and would post it if Aaron doesn't beat me to it :).
Ideally, this becomes a collaboration rather than a race to the
finish. I'd like to see both proposals, so tha
g a lot of the reader to know where there are and
are not gaps in the allocated hardware exception vectors. Perhaps all
of the above enumeration definitions could have initializers? Either
way...
Reviewed-by: Jim Mattson
On Wed, Jul 29, 2020 at 1:46 PM Alexander Graf wrote:
> Do you have a rough ETA for Aaron's patch set yet? :)
Rough ETA: Friday (31 July 2020).
2 reserved_1[15 - MAX_VECTORS];'
> u16 pause_filter_thresh;
> u16 pause_filter_count;
> u64 iopm_base_pa;
Reviewed-by: Jim Mattson
intercepts[INTERCEPT_VECTOR_5] doesn't seem in any way
"better" than just vmcb->control.intercepts[5].
Reviewed-by: Jim Mattson
On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
>
> Remove set_exception_intercept and clr_exception_intercept.
> Replace with generic set_intercept and clr_intercept for these calls.
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
>
> INVPCID instruction handling is mostly same across both VMX and
> SVM. So, move the code to common x86.c.
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
On Tue, Jul 28, 2020 at 4:39 PM Babu Moger wrote:
>
> The following intercept bit has been added to support VMEXIT
> for INVPCID instruction:
> CodeNameCause
> A2h VMEXIT_INVPCID INVPCID instruction
>
> The following bit has been added to the VMCB layout control area
> to cont
On Wed, Jul 29, 2020 at 4:59 PM Alexander Graf wrote:
>
> MSRs are weird. Some of them are normal control registers, such as EFER.
> Some however are registers that really are model specific, not very
> interesting to virtualization workloads, and not performance critical.
> Others again are reall
On Thu, Jul 30, 2020 at 4:08 PM Alexander Graf wrote:
>
>
>
> On 31.07.20 00:42, Jim Mattson wrote:
> >
> > On Wed, Jul 29, 2020 at 4:59 PM Alexander Graf wrote:
> >>
> >> MSRs are weird. Some of them are normal control registers, such as EFER.
>
On Thu, Jul 30, 2020 at 4:53 PM Jim Mattson wrote:
>
> On Thu, Jul 30, 2020 at 4:08 PM Alexander Graf wrote:
> > Do you have a particular situation in mind where that would not be the
> > case and where we would still want to actually complete an MSR operation
> > after
Manual Volume 2: System Programming,
> Pub. 24593 Rev. 3.34(or later)"
>
> The documentation can be obtained at the links below:
> Link: https://www.amd.com/system/files/TechDocs/24593.pdf
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>
> Signed-off-by: Babu Moger
Reviewed-by: Jim Mattson
2_PKRS = 1, VM exit loads PKRS from the host-state
> area.
> If VM_ENTRY_LOAD_IA32_PKRS = 1, VM entry loads PKRS from the guest-state
> area.
>
> Signed-off-by: Chenyi Qiang
Reviewed-by: Jim Mattson
On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote:
>
> PKS MSR passes through guest directly. Configure the MSR to match the
> L0/L1 settings so that nested VM runs PKS properly.
>
> Signed-off-by: Chenyi Qiang
> ---
> arch/x86/kvm/vmx/nested.c | 32
> arch/x86/k
On Wed, Aug 12, 2020 at 8:00 AM Sean Christopherson
wrote:
>
> On Mon, Aug 10, 2020 at 05:05:36PM -0700, Jim Mattson wrote:
> > On Fri, Aug 7, 2020 at 1:47 AM Chenyi Qiang wrote:
> > >
> > > PKS MSR passes through guest directly. Configure the MSR to match the
>
On Fri, Aug 7, 2020 at 1:46 AM Chenyi Qiang wrote:
>
> Protection Keys for Supervisor Pages (PKS) uses IA32_PKRS MSR (PKRS) at
> index 0x6E1 to allow software to manage supervisor protection key
> rights. For performance consideration, PKRS intercept will be disabled
> so that the guest can access
n bool rather than int?
> +{
> + if (!vcpu->kvm->arch.user_space_msr_enabled)
> + return 0;
> +
> + vcpu->run->exit_reason = KVM_EXIT_X86_WRMSR;
> + vcpu->run->msr.error = 0;
Same question about 'pad' as above.
> + vcpu->run->msr.index = index;
> + vcpu->run->msr.data = data;
> + vcpu->arch.pending_user_msr = true;
> + vcpu->arch.complete_userspace_io = complete_emulated_wrmsr;
> +
> + return 1;
> +}
> +
Reviewed-by: Jim Mattson
On Mon, Aug 3, 2020 at 2:14 PM Alexander Graf wrote:
>
> While tying to add support for the MSR_CORE_THREAD_COUNT MSR in KVM,
> I realized that we were still in a world where user space has no control
> over what happens with MSR emulation in KVM.
>
> That is bad for multiple reasons. In my case,
On Wed, Aug 19, 2020 at 2:46 PM Graf (AWS), Alexander wrote:
> Special MSRs like EFER also irritate me a bit. We can't really trap on them -
> most code paths just know they're handled in kernel. Maybe I'll add some
> sanity checks as well...
Why can't we intercept EFER?
On Mon, Aug 3, 2020 at 2:14 PM Alexander Graf wrote:
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -901,6 +901,13 @@ struct kvm_hv {
> struct kvm_hv_syndbg hv_syndbg;
> };
>
> +struct msr_bitmap_range {
> + u32 flags;
> + u32 nmsrs;
> +
On Wed, Aug 19, 2020 at 3:09 PM Jim Mattson wrote:
>
> On Wed, Aug 19, 2020 at 2:46 PM Graf (AWS), Alexander wrote:
>
> > Special MSRs like EFER also irritate me a bit. We can't really trap on them
> > - most code paths just know they're handled in kernel. Maybe I
On Thu, Aug 20, 2020 at 11:34 AM Tom Lendacky wrote:
>
> On 8/20/20 11:30 AM, Tom Lendacky wrote:
> > On 8/20/20 11:17 AM, Tom Lendacky wrote:
> >> On 8/20/20 10:55 AM, Andy Lutomirski wrote:
> >>> On Thu, Aug 20, 2020 at 8:21 AM Tom Lendacky
> >>> wrote:
>
> On 8/20/20 10:10 AM, Sean C
On Thu, Aug 20, 2020 at 11:38 AM Jim Mattson wrote:
>
> On Thu, Aug 20, 2020 at 11:34 AM Tom Lendacky wrote:
> >
> > On 8/20/20 11:30 AM, Tom Lendacky wrote:
> > > On 8/20/20 11:17 AM, Tom Lendacky wrote:
> > >> On 8/20/20 10:55 AM, Andy Lutomirski wrote:
On Wed, Apr 1, 2020 at 1:13 AM Vitaly Kuznetsov wrote:
>
> If KVM wasn't used at all before we crash the cleanup procedure fails with
> BUG: unable to handle page fault for address: ffc8
> #PF: supervisor read access in kernel mode
> #PF: error_code(0x) - not-present page
> PGD
On Thu, Aug 20, 2020 at 6:33 AM Maxim Levitsky wrote:
>
> The 'page' is to hold the vcpu's vmcb so name it as such to
> avoid confusion.
>
> Signed-off-by: Maxim Levitsky
Reviewed-by: Jim Mattson
- svm->nested.vmcb = 0;
> + svm->nested.vmcb12_gpa = 0;
Here, too, perhaps this could be changed from 0 to an illegal value in
a follow-up change.
Reviewed-by: Jim Mattson
On Thu, Aug 20, 2020 at 6:34 AM Maxim Levitsky wrote:
>
> Replace svm_vcpu_init_msrpm with svm_vcpu_alloc_msrpm, that also allocates
> the msr bitmap and add svm_vcpu_free_msrpm to free it.
>
> This will be used later to move the nested msr permission bitmap allocation
> to nested.c
>
> No functio
On Thu, Aug 20, 2020 at 6:34 AM Maxim Levitsky wrote:
>
> This will be used later to return an error when setting this msr fails.
>
> For VMX, it already has an error condition when EFER is
> not in the shared MSR list, so return an error in this case.
>
> Signed-off-by: Maxim Levitsky
> ---
> -
On Tue, Jul 28, 2020 at 7:38 AM Vitaly Kuznetsov wrote:
>
> PCIe config space can (depending on the configuration) be quite big but
> usually is sparsely populated. Guest may scan it by accessing individual
> device's page which, when device is missing, is supposed to have 'pci
> hole' semantics:
On Wed, Aug 5, 2020 at 5:18 PM Michael S. Tsirkin wrote:
>
> On Wed, Aug 05, 2020 at 10:05:40AM -0700, Jim Mattson wrote:
> > On Tue, Jul 28, 2020 at 7:38 AM Vitaly Kuznetsov
> > wrote:
> > >
> > > PCIe config space can (depending on the configuration) be qui
t; > "else if" case is a mess.
> >
> > Fixes: d42e3fae6faed ("kvm: x86: Read PDPTEs on CR0.CD and CR0.NW changes")
> > Cc: Jim Mattson
> > Cc: Oliver Upton
> > Cc: Peter Shier
> > Signed-off-by: Sean Christopherson
> > ---
> &
On Tue, Aug 18, 2020 at 12:28 AM Chenyi Qiang wrote:
>
>
>
> On 8/14/2020 1:31 AM, Jim Mattson wrote:
> > On Wed, Aug 12, 2020 at 10:42 PM Chenyi Qiang
> > wrote:
> >>
> >>
> >>
> >> On 8/13/2020 5:21 AM, Jim Mattson wrote:
>
It looks like userspace can possibly induce this by providing guest
CPUID information with a "physical address width" of 64 in leaf
0x8008.
Perhaps cpuid_query_maxphyaddr() should just look at the low 5 bits of
CPUID.8008H:EAX? Better would be to return an error for
out-of-range values, bu
On Thu, Dec 10, 2020 at 1:26 PM Babu Moger wrote:
>
> Hi Jim,
>
> > -Original Message-----
> > From: Jim Mattson
> > Sent: Monday, December 7, 2020 5:06 PM
> > To: Moger, Babu
> > Cc: Paolo Bonzini ; Thomas Gleixner
> > ; Ingo Molnar ;
On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote:
>
> Newer AMD processors have a feature to virtualize the use of the
> SPEC_CTRL MSR. When supported, the SPEC_CTRL MSR is automatically
> virtualized and no longer requires hypervisor intervention.
>
> This feature is detected via CPUID function 0x
On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote:
>
> Newer AMD processors have a feature to virtualize the use of the SPEC_CTRL
> MSR. This feature is identified via CPUID 0x800A_EDX[20]. When present,
> the SPEC_CTRL MSR is automatically virtualized and no longer requires
> hypervisor interve
On Mon, Dec 7, 2020 at 3:47 AM stsp wrote:
>
> 07.12.2020 14:29, Paolo Bonzini пишет:
> > On 07/12/20 12:24, stsp wrote:
> >> It tries to enable VME among other things.
> >> qemu appears to disable VME by default,
> >> unless you do "-cpu host". So we have a situation where
> >> the host (which is
On Wed, Apr 4, 2018 at 10:44 PM Paolo Bonzini wrote:
>
> On 04/04/2018 19:35, Stefan Fritsch wrote:
> > On Wednesday, 4 April 2018 19:24:20 CEST Paolo Bonzini wrote:
> >> On 04/04/2018 19:10, Konrad Rzeszutek Wilk wrote:
> >>> Should there be a corresponding test-case?
> >>
> >> Good point! Stefa
On Mon, Sep 14, 2020 at 11:33 AM Babu Moger wrote:
> Thanks Paolo. Tested Guest/nested guest/kvm units tests. Everything works
> as expected.
Debian 9 does not like this patch set. As a kvm guest, it panics on a
Milan CPU unless booted with 'nopcid'. Gmail mangles long lines, so
please see the a
> >
> > Babu, Jim, I'd appreciate it if you ran this to confirm.
Tested-by: Jim Mattson
On Mon, Mar 22, 2021 at 7:37 PM wrote:
>
> From: Haiwei Li
>
> According to IA-32 SDM Vol.3D "A.1 BASIC VMX INFORMATION", two inspections
> are missing.
> * Bit 31 is always 0. Earlier versions of this manual specified that the
> VMCS revision identifier was a 32-bit field in bits 31:0 of this MS
> could lead to use-after-free since readers expect the devices on their
> reference of the bus to remain valid.
>
> Fixes: f65886606c2d ("KVM: fix memory leak in kvm_io_bus_unregister_dev()")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
;dev_count; i++)
> + for (i = 0; i < bus->dev_count; i++) {
> if (bus->range[i].dev == dev) {
> break;
> }
> + }
Per coding-style.rst, neither the for loop nor the if-block should have braces.
"Do not unnecessarily use braces where a single statement will do."
Stylistic nits aside,
Reviewed-by: Jim Mattson
: fix memory leak in kvm_io_bus_unregister_dev()")
> Cc: sta...@vger.kernel.org
> Reported-by: Hao Sun
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
On Mon, Apr 12, 2021 at 6:09 AM David Edmondson
wrote:
>
> Instruction emulation happens for a variety of reasons, yet on error
> we have no idea exactly what triggered it. Add a cause of emulation to
> the various originators and pass it upstream when emulation fails.
What is userspace going to
On Wed, Dec 9, 2020 at 2:39 PM Babu Moger wrote:
>
>
>
> On 12/7/20 5:22 PM, Jim Mattson wrote:
> > On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote:
> >>
> >> Newer AMD processors have a feature to virtualize the use of the SPEC_CTRL
> >> MSR. This f
On Thu, Mar 11, 2021 at 12:32 PM Borislav Petkov wrote:
>
> On Thu, Mar 11, 2021 at 09:07:55PM +0100, Borislav Petkov wrote:
> > On Wed, Mar 10, 2021 at 07:21:23PM -0600, Babu Moger wrote:
> > > # git bisect good
> > > 59094faf3f618b2d2b2a45acb916437d611cede6 is the first bad commit
> > > commit 5
On Tue, Jan 19, 2021 at 3:45 PM Babu Moger wrote:
>
>
>
> On 1/19/21 5:01 PM, Jim Mattson wrote:
> > On Mon, Sep 14, 2020 at 11:33 AM Babu Moger wrote:
> >
> >> Thanks Paolo. Tested Guest/nested guest/kvm units tests. Everything works
> >> as expected.
On Fri, Jan 15, 2021 at 11:35 AM Jim Mattson wrote:
>
> On Fri, Oct 23, 2020 at 10:43 AM Paolo Bonzini wrote:
> >
> > On 23/10/20 19:23, Jim Mattson wrote:
> > >> The information that we need is _not_ that provided by the advanced
> > >> VM-exit info
On Wed, Mar 10, 2021 at 7:24 AM Andi Kleen wrote:
>
> The pebs_no_isolation optimization check is inverted. We want to disable
> PEBS isolation when the microcode is at least the revision in the table,
> not for older microcode. So remove the extra !.
The original code was correct because of the d
non-NULL.
>
> Fixes: abd562df94d1 ("x86/perf: Use static_call for x86_pmu.guest_get_msrs")
> Cc: Like Xu
> Cc: Paolo Bonzini
> Cc: Jim Mattson
> Reported-by: Dmitry Vyukov
> Reported-by: syzbot+cce9ef2dd25246f81...@syzkaller.appspotmail.com
> Suggested-by: Pe
On Fri, Oct 23, 2020 at 10:43 AM Paolo Bonzini wrote:
>
> On 23/10/20 19:23, Jim Mattson wrote:
> >> The information that we need is _not_ that provided by the advanced
> >> VM-exit information (or by a page walk). If a page is neither writable
> >> nor exe
On Thu, Sep 3, 2020 at 7:12 AM Mohammed Gamal wrote:
>
> This patch exposes allow_smaller_maxphyaddr to the user as a module parameter.
>
> Since smaller physical address spaces are only supported on VMX, the parameter
> is only exposed in the kvm_intel module.
> Modifications to VMX page fault an
isolation_ucodes[] table so that these parts benefit from Andi's
optimization in commit 9b545c04abd4f ("perf/x86/kvm: Avoid unnecessary
work in guest filtering").
Signed-off-by: Jim Mattson
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Cc: M
On Wed, Jan 20, 2021 at 1:16 PM Jim Mattson wrote:
>
> On Fri, Jan 15, 2021 at 11:35 AM Jim Mattson wrote:
> >
> > On Fri, Oct 23, 2020 at 10:43 AM Paolo Bonzini wrote:
> > >
> > > On 23/10/20 19:23, Jim Mattson wrote:
> > > >> The information
On Wed, Aug 28, 2019 at 10:38 PM Luwei Kang wrote:
>
> PEBS output Inte PT introduces some new MSRs (MSR_RELOAD_FIXED_CTRx)
> for fixed function counters that use for autoload the preset value
> after writing out a PEBS event.
>
> Introduce base MSRs address parameter to make this function can get
SSBD, STIBP and AMD_SSB_NO bit were not set, and
> VIRT_SSBD does not have to be added manually because it is a
> cpufeature that comes directly from the host's CPUID bit.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Jim Mattson
ek Wilk
> Reported-by: Eduardo Habkost
> Signed-off-by: Paolo Bonzini
Reviewed-by: Jim Mattson
On Wed, Aug 21, 2019 at 1:27 AM Paolo Bonzini wrote:
>
> Similar to AMD bits, set the Intel bits from the vendor-independent
> feature and bug flags, because KVM_GET_SUPPORTED_CPUID does not care
> about the vendor and they should be set on AMD processors as well.
>
> Suggest
PU) but not for KVM_GET/SET_XCRS.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Jim Mattson
On Thu, Aug 15, 2019 at 6:41 AM Yang Weijiang wrote:
> Hi, Vitaly,
> After looked into the issue and others, I feel to make SPP co-existing
> with nested VM is not good, the major reason is, L1 pages protected by
> SPP are transparent to L1 VM, if it launches L2 VM, probably the
> pages would be
On Fri, Aug 16, 2019 at 6:29 AM Yang Weijiang wrote:
> Thanks Jim and Sean! Could we add a new flag in kvm to identify if nested VM
> is on
> or off? That would make things easier. When VMLAUNCH is trapped,
> set the flag, if VMXOFF is trapped, clear the flag.
KVM_GET_NESTED_STATE has the reque
e vmx_vcpu pointer is
> needed, its consumption via 'call vmx_update_host_rsp' is rather subtle.
>
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
t; will instead overlap random chunks of the vendor specific struct.
> E.g. padding a large number of bytes before struct kvm_vcpu triggers
> a usercopy warn when running with CONFIG_HARDENED_USERCOPY=y.
>
> Signed-off-by: Sean Christopherson
X86 parts:
Reviewed-by: Jim Mattson
' for both types
> (X86EMUL_CONTINUE and EMULATION_OK).
>
> Fixes: 285ca9e948fa ("KVM: emulate: speed up do_insn_fetch")
> Signed-off-by: Sean Christopherson
Reviewed-by: Jim Mattson
On Thu, Aug 15, 2019 at 12:41 AM Paolo Bonzini wrote:
>
> The AMD_* bits have to be set from the vendor-independent
> feature and bug flags, because KVM_GET_SUPPORTED_CPUID does not care
> about the vendor and they should be set on Intel processors as well.
> On top of this, SSBD, STIBP and AMD_SS
On Tue, Aug 27, 2019 at 9:04 AM Vitaly Kuznetsov wrote:
>
> It was discovered that after commit 65efa61dc0d5 ("selftests: kvm: provide
> common function to enable eVMCS") hyperv_cpuid selftest is failing on AMD.
> The reason is that the commit changed _vcpu_ioctl() to vcpu_ioctl() in the
> test an
Remove the
> unneeded stub from SVM code.
>
> Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Jim Mattson
mcs_version()
> helper")
> Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Jim Mattson
On Fri, Aug 23, 2019 at 1:55 PM Sean Christopherson
wrote:
>
> Don't advance RIP or inject a single-step #DB if emulation signals a
> fault. This logic applies to all state updates that are conditional on
> clean retirement of the emulation instruction, e.g. updating RFLAGS was
> previously handl
_ioctl() in the
> test and this one can't fail.
>
> Instead of fixing the test is seems to make more sense to not announce
> KVM_CAP_HYPERV_ENLIGHTENED_VMCS support if it is definitely missing
> (on svm and in case kvm_intel.nested=0).
>
> Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Jim Mattson
On Thu, Sep 12, 2019 at 1:51 AM Vitaly Kuznetsov wrote:
>
> Fuqian Huang writes:
>
> > Emulation of VMPTRST can incorrectly inject a page fault
> > when passed an operand that points to an MMIO address.
> > The page fault will use uninitialized kernel stack memory
> > as the CR2 and error code.
>
On Wed, Sep 11, 2019 at 9:18 PM Fuqian Huang wrote:
>
> Emulation of VMPTRST can incorrectly inject a page fault
> when passed an operand that points to an MMIO address.
> The page fault will use uninitialized kernel stack memory
> as the CR2 and error code.
>
> The right behavior would be to abor
On Mon, Sep 16, 2019 at 9:23 AM Vitaly Kuznetsov wrote:
>
> Hyper-V 2019 doesn't expose MD_CLEAR CPUID bit to guests when it cannot
> guarantee that two virtual processors won't end up running on sibling SMT
> threads without knowing about it. This is done as an optimization as in
> this case ther
On Mon, Sep 16, 2019 at 9:23 AM Vitaly Kuznetsov wrote:
>
> KVM needs to know if SMT is theoretically possible, this means it is
> supported and not forcefully disabled ('nosmt=force'). Create and
> export cpu_smt_possible() answering this question.
It seems to me that KVM really just wants to kn
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