Hi Alison,
On 25/08/2020 03:31, Alison Wang wrote:
>> On 09/07/2020 09:22, Alison Wang wrote:
>>> Add error detection for A53 and A72 cores. Hardware error injection is
>>> supported on A53. Software error injection is supported on both.
>>
>
>>
>> As we can't safely write to these registers from
Hi Zhang,
On 12/08/2020 12:09, Liguang Zhang wrote:
> Function arm64_is_fatal_ras_serror() is always called after
> arm64_is_ras_serror(), so we should remove some needless
> arm64_is_ras_serror() call in function arm64_ras_serror_get_severity().
> diff --git a/arch/arm64/include/asm/traps.h b/ar
Hi Andre,
On 06/10/2020 21:18, Andre Przywara wrote:
> The ARM architected TRNG firmware interface, described in ARM spec
> DEN0098[1], defines an ARM SMCCC based interface to a true random number
> generator, provided by firmware.
> This can be discovered via the SMCCC >=v1.1 interface, and provi
Hi Shiju,
On 06/10/2020 17:13, Shiju Jose wrote:
[...]
> Please find following pseudo code we added for the kernel side to make sure
> we correctly understand your suggestions.
>
> 1. Create edac device and edac device sysfs entries for the online CPU caches.
> /drivers/edac/edac_device.c
> str
Hi guys,
On 26/05/2020 22:18, Rob Herring wrote:
> On Fri, May 22, 2020 at 11:24:11AM +0800, chenzhou wrote:
>> On 2020/5/21 21:29, Rob Herring wrote:
>>> On Thu, May 21, 2020 at 3:35 AM Chen Zhou wrote:
Add documentation for DT property used by arm64 kdump:
linux,low-memory-range.
mbm_handle_overflow() and cqm_handle_limbo() are both provided with
the domain's work_struct when called, but use get_domain_from_cpu()
to find the domain, along with the appropriate error handling.
container_of() saves some list walking and bitmap testing, use that
instead.
Signed-off-by:
mains"
error message for affected platforms.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
Reviewed-by: Babu Moger
---
An alternative to this is for Intel non-linear MBA resources to
clear alloc_capable as they can't be configured anyway.
---
arch/x86/kernel/cpu/resctrl/co
Nothing reads struct mbm_states's chunks_bw value, its a copy of
chunks. Remove it.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/internal.h | 2 --
arch/x86/kernel/cpu/resctrl/monitor.c | 3 +--
2 files changed, 1 insertion(+), 4 deletions(-)
The comment in rdtgroup_init() refers to the non existent function
rdt_mount(), which has now been renamed rdt_get_tree(). Fix the
comment.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
est
needed for Haswell, but as it always sets this value to 1, it will
never match.
CC: Reinette Chatre
Signed-off-by: James Morse
Reviewed-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl/core.c| 14
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 39 ++-
arch/x86/
max_delay is used by x86's __get_mem_config_intel() as a local variable.
Remove it, replacing it with a local variable.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/core.c | 8
arch/x86/kernel/cpu/resctrl/internal.h | 3 ---
2
is harmless
as rdtgroup_mkdir() tests these capable flags before allowing the config
directories to be created.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 30 --
1 file changed, 14 insertions(+), 16 deletions
intel_cacheinfo.c,
name it get_cpu_cacheinfo_id() to show its relation with
get_cpu_cacheinfo().
Now this is visible on other architectures, check the id attribute
has actually been set.
Signed-off-by: James Morse
Reviewed-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl/core.c | 17
ml/20200430170400.21501-1-james.mo...@arm.com/
[v1] https://lore.kernel.org/lkml/20200214182401.39008-1-james.mo...@arm.com/
James Morse (10):
x86/resctrl: Nothing uses struct mbm_state chunks_bw
x86/resctrl: Remove max_delay
x86/resctrl: Fix stale comment
x86/resctrl: use container_of() in de
Removing this duplication means user-space visible behaviour and
error messages are not validated or generated in different places.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
Reviewed-by : Babu Moger
---
arch/x86/kernel/cpu/resctrl/core.c| 3 +-
arch/x86/kernel/cpu/resctrl/ctr
We are about to disturb the header soup. This header uses struct pid
and struct pid_namespace. Include their header.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
include/linux/resctrl.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/resctrl.h b/include/linux
e platform device and flag warning if we fail.
Reviewed-by: James Morse
Will/Catalin, any chance you could pick this up for v5.8?
Original message:
https://lore.kernel.org/linux-arm-kernel/20200422122823.1390-1-sudeep.ho...@arm.com/
Thanks!
James
Hi guys,
On 13/05/2020 21:03, Babu Moger wrote:
>> From: Reinette Chatre
>> On 4/30/2020 10:03 AM, James Morse wrote:
>>> Intel expects the cache bitmap provided by user-space to have on a
>>> single span of 1s, whereas AMD can support bitmaps like 0xf00f.
>
ing. Can you try
>> that first?
> My patches will fix this issue. This is an ARM64 specific problem and
> I did not see this to be performance problem on x86 during kexec
> relocation. This happens because on ARM64 relocation is performed with
> MMU disabled, and when MMU is disabl
Hi Neeraj,
On 21/10/2020 18:31, Neeraj Upadhyay wrote:
> On 10/16/2020 9:57 PM, James Morse wrote:
>> On 15/10/2020 07:07, Neeraj Upadhyay wrote:
>>> 1. Looks like interrupt bind interface (SDEI_1_0_FN_SDEI_INTERRUPT_BIND) is
>>> not available
>>> for
947.39194-1-james.mo...@arm.com/
Thanks,
James Morse (24):
x86/resctrl: Split struct rdt_resource
x86/resctrl: Split struct rdt_domain
x86/resctrl: Add resctrl_arch_get_num_closid()
x86/resctrl: Add a separate schema list for resctrl
x86/resctrl: Pass the schema in resdir's priv
d
the name and pending configuration values for resctrl.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/internal.h | 1 +
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 43 +-
include/linux/resctrl.h| 9 ++
3 files changed, 52 insertions(+),
fs code. Eventually the fs code will generate pairs of CODE/DATA if
the platform supports CDP for this resource.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c | 7 +++
arch/x86/kernel/cpu/resctrl/internal.h | 1 +
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 1 +
include
->num_closid, which is already adjusted for CDP.
Once the CODE/DATA/BOTH resources are merged, resctrl can make the
adjustment when copying the value to the schema's num_closid.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c| 5 +
arch/x86/kernel/cpu/resctrl/
rdtgroup_schemata_show() to walk the schema instead.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 13 -
arch/x86/kernel/cpu/resctrl/rdtgroup.c| 11 +--
include/linux/resctrl.h | 2 ++
3 files changed, 15 insertions(+), 11
paths touching a 'hw'
struct indicates where an abstraction is needed.
No change in behaviour, this patch just moves types around.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c| 32 +++---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 --
property, like the conf_type. Switch these to
walk the schema list. Schema were only created for alloc_enabled
resources so these two lists are currently equivalent.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 38 ++-
arch/x86/kernel/cpu/resctrl
the private pointers varies
between control and monitor info dirs.
If the flags are RF_MON_INFO, its a struct rdt_resource. If the
flags are RF_CTRL_INFO, its a struct resctrl_schema. Nothing in
res_common_files[] has both flags.
Signed-off-by: James Morse
---
Fake schema for monitors may sim
n the next patch.
No change in behaviour, this patch just moves types around.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c| 258 --
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 14 +-
arch/x86/kernel/cpu/resctrl/internal.h| 138 +++-
e user-space
control format at all.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 16 ++---
arch/x86/kernel/cpu/resctrl/monitor.c | 6 +++-
arch/x86/kernel/cpu/resctrl/rdtgroup.c| 43 ++-
include/linux/resctrl.h
struct pseudo_lock_region points to the rdt_resource. Once the
resources are merged, this won't be unique. The resource name
is moving into the schema, so that eventually resctrl can generate
it.
Change pseudo_lock_region's rdt_resource pointer for a schema pointer.
Signed-off-by: J
configuration type. This makes the
static mult and offset parameters set by the arch code redundant.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c| 12
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 17 +++--
include/linux/resctrl.h
into apply_config()
so that odd/even slots in the ctrlval array are used.
This makes it possible to merge the resources.
In future, the arithmetic will be based on the style of the configuration,
not the resource.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c| 15
width, this is now resctrl's
problem.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c| 9 ++---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 +++---
arch/x86/kernel/cpu/resctrl/internal.h| 2 +-
arch/x86/kernel/cpu/resctrl/rdtgroup
s
configuration array, and updates the hardware, make it part of the
arch code interface.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 40 +--
arch/x86/kernel/cpu/resctrl/internal.h| 6 ++--
arch/x86/kernel/cpu/resctrl/rdtgroup.c| 2 +-
the closid from the same place, so they pair up.
Move the closid to be a staged parameter.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 ++
arch/x86/kernel/cpu/resctrl/rdtgroup.c| 6 --
include/linux/resctrl.h | 2 ++
3 files
fig helper.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 99 --
1 file changed, 14 insertions(+), 85 deletions(-)
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 162e415d5d09..0d561679f7e8 100644
e
CPU configuration. Enabling CDP for one resource means all resources
see the different closid values.
Signed-off-by: James Morse
---
It may be possible for MPAM to apply the same 'L3' configuration to
the two closid that are in use, giving the illusion that CDP is enabled
for some resource
rdt_domain_reconfigure_cdp() infers whether CDP is enabled by
checking the alloc_capable and alloc_enabled flags of the data
resources.
Now that there is an explicit cdp_enabled, use that.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 8 +---
1 file changed, 5
ere is only one element in the array, but
eventually resctrl will use the array slots for CODE/DATA/BOTH to detect
a duplicate schema being written.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 49 ---
arch/x86/kernel/cpu/resctrl/rdt
the value on the
L2 or L3 resource if it already exists. This gets removed once the
resources are merged, and there really is only one ctrlval array.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c | 79 +++---
1 file changed, 72 insertions(+), 7 deletion
index in the configuration array.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 5 ++--
arch/x86/kernel/cpu/resctrl/monitor.c | 2 +-
arch/x86/kernel/cpu/resctrl/rdtgroup.c| 35 +++
include/linux/resctrl.h | 3 +-
4 files
each schema. Use the conf_type enum directly as an index.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 16 ++--
arch/x86/kernel/cpu/resctrl/rdtgroup.c| 5 +++--
include/linux/resctrl.h | 4 +++-
3 files changed, 16 insertions
sctrl, which will then create the separate CODE/DATA schema
for its ABI.
Add a helper to add schema with a the CDP suffix if CDP is enabled.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c | 193 ++---
arch/x86/kernel/cpu/resctrl/internal.h | 4 -
arch/x86/k
is that the caches are reset twice, once
for CODE once for DATA.
Signed-off-by: James Morse
---
arch/x86/kernel/cpu/resctrl/core.c | 10 +-
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 10 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu
Hi Alison,
On 09/07/2020 09:22, Alison Wang wrote:
> Add error detection for A53 and A72 cores. Hardware error injection is
> supported on A53. Software error injection is supported on both.
> For hardware error injection on A53 to work, proper access to
> L2ACTLR_EL1, CPUACTLR_EL1 needs to be gr
Hi Neeraj,
On 15/10/2020 07:07, Neeraj Upadhyay wrote:
> 1. Looks like interrupt bind interface (SDEI_1_0_FN_SDEI_INTERRUPT_BIND) is
> not available
> for clients to use; can you please share information on
> why it is not provided?
There is no compelling use-case for it, and its very complex to
Hi Jamie,
Thanks for taking a look,
On 10/11/2020 11:39, Jamie Iles wrote:
> On Fri, Oct 30, 2020 at 04:11:06PM +0000, James Morse wrote:
>> Move the names used for the schemata file out of the resource and
>> into struct resctrl_schema. This allows one resource to have two
>
Hi Henry,
On 06/11/2020 23:25, Henry Willard wrote:
> machine_shutdown() is called by kernel_kexec() to shutdown
> the non-boot CPUs prior to starting the new kernel. The
> implementation of machine_shutdown() varies by architecture.
> Many make an interprocessor call, such as smp_send_stop(),
> t
Hi Reinette,
On 16/11/2020 17:54, Reinette Chatre wrote:
> On 10/30/2020 9:10 AM, James Morse wrote:
>> MPAM has an equivalent feature to CDP, but its a property of the CPU,
>> not the cache. Resctrl needs to have x86's odd/even behaviour, as that
>> its the ABI, b
Hi!
On 03/11/2020 17:31, Nicolas Saenz Julienne wrote:
> crashkernel might reserve memory located in ZONE_DMA. We plan to delay
> ZONE_DMA's initialization after unflattening the devicetree and ACPI's
> boot table initialization, so move it later in the boot process.
> Specifically into mem_init()
Hi Shiju,
On 05/11/2020 17:42, Shiju Jose wrote:
> For the firmware-first error handling on ARM64 hardware platforms,
> CPU cache corrected error count is not recorded.
> Create an CPU EDAC device and device blocks for the CPU caches
> for this purpose. The EDAC device blocks are created based on
Hi Shiju, Jonathan,
On 05/11/2020 17:42, Shiju Jose wrote:
> From: Jonathan Cameron
>
> According to the following sections of the PPTT definition in the
> ACPI specification(V6.3), a high level cache node( For example L2 cache)
> could be represented simultaneously both in the private resource
Hi Reinette,
On 08/07/2020 17:39, James Morse wrote:
> These are the miscellaneous cleanup patches that floated to the top of
> the MPAM tree.
Is there anything else I should do with this series?
(Does patch 10 need an ACK from anyone else?)
Would a branch or pull request make anyone&
Hi Marc,
(CC: +Jon)
On 01/09/2020 15:43, Marc Zyngier wrote:
> Change the way we deal with GIC SGIs by turning them into proper
> IRQs, and calling into the arch code to register the interrupt range
> instead of a callback.
Your comment "This only works because we don't nest SGIs..." on this thr
get_tcr_el1_t1sz());
> vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
> vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n",
> system_supports_address_auth() ?
(I think
Hi Junhan,
On 30/05/2019 19:48, Junhan Zhou wrote:
>> -Original Message-
>> From: James Morse
>> Sent: Thursday, May 23, 2019 1:30 PM
>> To: Junhan Zhou
>>> +union mlxbf_emi_dram_additional_info_0 {
>>> + struct {
>>> +
Hi Robert,
On 03/06/2019 14:10, Robert Richter wrote:
> On 29.05.19 16:12:38, James Morse wrote:
>> On 29/05/2019 09:44, Robert Richter wrote:
>>> Almost duplicate code, remove it.
>>
>>> Note: there is a difference in the calculation of the grain_bits,
>
Hi Thor,
(CC: +Mark, Lorenzo and Sudeep for PSCI.
How should SYSTEM_RESET2 be used for a vendor-specific reset?
The original patch is:
lore.kernel.org/r/1559594269-10077-1-git-send-email-thor.tha...@linux.intel.com
)
On 03/06/2019 21:37, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
Hi guys,
On 31/05/2019 06:14, Borislav Petkov wrote:
> On Fri, May 31, 2019 at 01:15:33AM +, Herrenschmidt, Benjamin wrote:
>> This isn't terribly helpful, there's nothing telling anybody which of
>> those files corresponds to an ARM SoC :-)
>
> drivers/edac/altera_edac.c is one example.
>
>
Hi Hana,
On 30/05/2019 11:15, Hanna Hawa wrote:
> Add support for error detection and correction for Amazon's Annapurna
> Labs SoCs for L1/L2 caches.
>
> Amazon's Annapurna Labs SoCs based on ARM CA57 and CA72, the driver
> support both cortex based on compatible string.
> diff --git a/drivers/e
Hi Chen Zhou,
On 13/06/2019 12:27, Chen Zhou wrote:
> On 2019/6/6 0:32, James Morse wrote:
>> On 07/05/2019 04:50, Chen Zhou wrote:
>>> We use crashkernel=X to reserve crashkernel below 4G, which will fail
>>> when there is no enough memory. Currently, crashkernel=Y@X
Hi Hawa,
On 11/06/2019 20:56, Hawa, Hanna wrote:
> James Morse wrote:
>> Hawa, Hanna wrote:
>>> + edac_device_handle_ce(edac_dev, 0, 0, "L2 Error");
>>
>> How do we know this was corrected?
>>
>> 6.4.8 "Error Correction Code" has &q
Hi Robert,
On 29/05/2019 09:44, Robert Richter wrote:
> In a later patch we want add more information about the memory
> hierarchy (NUMA topology, DIMM label information). Rework memory
> hierarchy detection to make the code extendable for this.
>
> The general approach is roughly like:
>
>
Hi Robert,
On 29/05/2019 09:44, Robert Richter wrote:
> Almost duplicate code, remove it.
almost?
> Note: there is a difference in the calculation of the grain_bits,
> using the edac_mc's version here.
But is it the right thing to do?
Is this an off-by-one bug being papered over as some clean
Hi Robert,
On 29/05/2019 09:44, Robert Richter wrote:
> The ghes driver is not able yet to count legacy API counters in sysfs,
> e.g.:
>
> /sys/devices/system/edac/mc/mc0/csrow2/ce_count
> /sys/devices/system/edac/mc/mc0/csrow2/ch0_ce_count
> /sys/devices/system/edac/mc/mc0/csrow2/ch1_ce_count
top_layer = -1;
> e->mid_layer = -1;
> e->low_layer = -1;
> - *pvt->other_detail = '\0';
> + e->msg = pvt->msg;
> + e->other_detail = pvt->other_detail;
> +
> *pvt->msg = '\0';
> + *pvt->other_detail = '\0';
... so no change? Could you drop this hunk?
Regardless,
Reviewed-by: James Morse
Thanks,
James
Hi Robert,
On 29/05/2019 09:44, Robert Richter wrote:
> Use standard macros for page calculations.
Reviewed-by: James Morse
Thanks,
James
Hi Robert,
On 29/05/2019 09:44, Robert Richter wrote:
> In a later patch we want to have one mc device per node. This patch
> extracts the numa node information for each dimm. This is done by
> collecting the physical address ranges from the DMI table (Memory
> Array Mapped Address - Type 19 of SM
Hi Robert,
On 12/06/2019 19:41, Robert Richter wrote:
> On 29.05.19 16:13:02, James Morse wrote:
>> On 29/05/2019 09:44, Robert Richter wrote:
>>> The ghes driver is not able yet to count legacy API counters in sysfs,
>>> e.g.:
>>>
>>> /sys/devices
Hi Hawa,
On 17/06/2019 14:00, Hawa, Hanna wrote:
>> I don't think it can, on a second reading, it looks to be even more
>> complicated than I
>> thought! That bit is described as disabling forwarding of uncorrected data,
>> but it looks
>> like the uncorrected data never actually reaches the oth
t;emi_base);
> + goto err;
> + }
> +
> + mci->pdev = dev;
> + mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 |
> + MEM_FLAG_LRDDR4 | MEM_FLAG_NVDIMM;
> + mci->edac_ctl_cap = EDAC_FLAG_SECDED;
> +
> + mci->mod_name = DRIVER_NAME;
> + mci->ctl_name = "BlueField_Memory_Controller";
> + mci->dev_name = dev_name(dev);
> + mci->edac_check = bluefield_edac_check;
> +
> + /* Initialize mci with the actual populated DIMM information. */
> + bluefield_edac_init_dimms(mci);
> +
> + platform_set_drvdata(pdev, mci);
> +
> + /* Register with EDAC core */
> + rc = edac_mc_add_mc(mci);
> + if (rc) {
> + dev_err(dev, "failed to register with EDAC core\n");
> + ret = rc;
> + goto err;
> + }
> +
> + /* Only POLL mode supported so far. */
> + edac_op_state = EDAC_OPSTATE_POLL;
> + return 0;
> +
> +err:
> + edac_mc_free(mci);
> +
> + return ret;
> +
> +}
With the MLXBF_EDAC_MAX_DIMM_PER_MC check and offset_in_page()/~PAGE_MASK:
Reviewed-by: James Morse
Thanks,
James
[0]
https://static.docs.arm.com/den0028/b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Hi!
On 16/05/2019 17:48, Hsin-Yi Wang wrote:
> On Thu, May 16, 2019 at 11:32 PM Rob Herring wrote:
>> Doesn't kexec operate on a copy because it already does modifications.
It does!
> This patch is to assist "[PATCH v3 3/3] fdt: add support for rng-seed"
> (https://lkml.org/lkml/2019/5/16/257).
Hi Hawa,
On 13/06/2019 18:05, James Morse wrote:
> On 11/06/2019 20:56, Hawa, Hanna wrote:
>> James Morse wrote:
>>> Hawa, Hanna wrote:
>>>> + if (cluster != last_cluster) {
>>>> + smp_call_function_single(cpu, al_a57_edac_l2merrsr,
encoded.
To the maintainer's scripts its going to look like this:
https://lore.kernel.org/lkml/byapr21mb131946e0b469e74d6054c33390...@byapr21mb1319.namprd21.prod.outlook.com/raw
> -Original Message-----
> From: James Morse
> On 16/05/2019 03:55, Lei Wang wrote:
>&g
Hi Zenghui,
On 13/06/2019 12:28, Zenghui Yu wrote:
> On 2019/6/12 20:49, James Morse wrote:
>> On 12/06/2019 10:08, Zenghui Yu wrote:
>>> Currently, we use trace_kvm_exit() to report exception type (e.g.,
>>> "IRQ", "TRAP") and exception class (E
mata is written while the resource group is in 'pseudo-locksetup'
mode." When we find a pseudo_locksetup group, its configuration is
expected to be overwritten, we can skip it.
Fixes: dfe9674b04ff6 ("x86/intel_rdt: Enable entering of pseudo-locksetup mode")
Signed-off
n-kernel dependency, move the cacheinfo
work earlier so we know its done before resctrl's CPUHP_AP_ONLINE_DYN
work runs.
Cc: Fenghua Yu
Cc: Reinette Chatre
Signed-off-by: James Morse
---
I haven't seen any problems because of this. If someone thinks it should
go to stable:
Cc: #4.10
mata is written while the resource group is in 'pseudo-locksetup'
mode." When we find a pseudo_locksetup group, its configuration is
expected to be overwritten, we can skip it.
Fixes: dfe9674b04ff6 ("x86/intel_rdt: Enable entering of pseudo-locksetup mode")
Cc:
Ack
Hi Amit,
On 09/01/2019 10:13, Amit Daniel Kachhap wrote:
> On Sat, Jan 5, 2019 at 12:05 AM James Morse wrote:
>> On 18/12/2018 07:56, Amit Daniel Kachhap wrote:
>>> This feature will allow the KVM guest to allow the handling of
>>> pointer authentication instr
Hi Amit,
On 28/01/2019 06:58, Amit Daniel Kachhap wrote:
> The keys can be switched either inside an assembly or such
> functions which do not have pointer authentication checks, so a GCC
> attribute is added to enable it.
>
> A function ptrauth_keys_store is added which is similar to existing
>
Hi Amit,
On 28/01/2019 06:58, Amit Daniel Kachhap wrote:
> When restoring HCR_EL2 for the host, KVM uses HCR_HOST_VHE_FLAGS, which
> is a constant value. This works today, as the host HCR_EL2 value is
> always the same, but this will get in the way of supporting extensions
> that require HCR_EL2 b
Hi Amit,
On 28/01/2019 06:58, Amit Daniel Kachhap wrote:
> This feature will allow the KVM guest to allow the handling of
> pointer authentication instructions or to treat them as undefined
> if not set. It uses the existing vcpu API KVM_ARM_VCPU_INIT to
> supply this parameter instead of creating
Hi Amit,
On 28/01/2019 06:58, Amit Daniel Kachhap wrote:
> When pointer authentication is supported, a guest may wish to use it.
> This patch adds the necessary KVM infrastructure for this to work, with
> a semi-lazy context switch of the pointer auth state.
>
> Pointer authentication feature is
Hi Steve,
On 17/06/2020 16:34, Steven Price wrote:
> On 17/06/2020 15:38, Catalin Marinas wrote:
>> On Wed, Jun 17, 2020 at 01:38:44PM +0100, Steven Price wrote:
>>> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
>>> index e3b9ee268823..040a7fffaa93 100644
>>> --- a/virt/kvm/arm/mmu.c
>>> ++
Hi guys,
On 24/06/2020 17:24, Catalin Marinas wrote:
> On Wed, Jun 24, 2020 at 03:59:35PM +0100, Steven Price wrote:
>> On 24/06/2020 15:21, Catalin Marinas wrote:
>>> On Wed, Jun 24, 2020 at 12:16:28PM +0100, Steven Price wrote:
On 23/06/2020 18:48, Catalin Marinas wrote:
> This causes p
Hi Dhananjay,
On 24/04/2020 09:31, Dhananjay Kangude wrote:
> Added edac platform driver for Cadence DDR controller which
> notify the ecc events based on the single or double bit errors
> during memory operations.
Is there any public documentation for this device?
The way you're using syfs her
Hi Pavel,
On 26/03/2020 03:24, Pavel Tatashin wrote:
> Soon, relocation function will share the same page with EL2 vectors.
The EL2 vectors would only be executed with the MMU off, so they don't need to
be mapped
anywhere in particular. (this is something hibernate probably does sloppily).
> A
Hi Pavel,
On 26/03/2020 03:24, Pavel Tatashin wrote:
> Remove excessive empty lines from arm64_relocate_new_kernel.
To make it harder to read? Or just for the churn ...
> Also, use comments on the same lines with instructions where
> appropriate.
Churn,
> Change ENDPROC to END it never return
Hi Pavel,
What happened to the subject?
(it really needs a verb to make any sense)
On 26/03/2020 03:24, Pavel Tatashin wrote:
> If we have a EL2 mode without VHE, the EL2 vectors are needed in order
> to switch to EL2 and jump to new world with hyperivsor privileges.
Yes, but the hyp-stub has an
Hi Pavel,
On 26/03/2020 03:24, Pavel Tatashin wrote:
> Configure a page table located in kexec-safe memory that has
> the following mappings:
>
> 1. identity mapping for text of relocation function with executable
>permission.
> 2. linear mappings for all source ranges
> 3. linear mappings fo
hat covered,
Reviewed-by: James Morse
Thanks,
James
Hi Pavel,
On 26/03/2020 03:24, Pavel Tatashin wrote:
> Currently, kexec relocation function (arm64_relocate_new_kernel) accepts
> the following arguments:
>
> head: start of array that contains relocation information.
> entry:entry point for new kernel or purgatory.
> dtb_
is harmless
as rdtgroup_mkdir() tests these capable flags before allowing the config
directories to be created.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 30 --
1 file changed, 14 insertions(+), 16 deletions
b998
and can be retrieved from:
git://linux-arm.org/linux-jm.git mpam/cleanup/v3
Thanks,
James
[v2] https://lore.kernel.org/lkml/20200430170400.21501-1-james.mo...@arm.com/
[v1] https://lore.kernel.org/lkml/20200214182401.39008-1-james.mo...@arm.com/
James Morse (10):
x86/resctrl: Noth
Removing this duplication means user-space visible behaviour and
error messages are not validated or generated in different places.
CC: Babu Moger
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/core.c| 3 +-
arch/x86/kernel/cpu/resctrl/ctr
max_delay is used by x86's __get_mem_config_intel() as a local variable.
Remove it, replacing it with a local variable.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/core.c | 8
arch/x86/kernel/cpu/resctrl/internal.h | 3 ---
2
Nothing reads struct mbm_states's chunks_bw value, its a copy of
chunks. Remove it.
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
arch/x86/kernel/cpu/resctrl/internal.h | 2 --
arch/x86/kernel/cpu/resctrl/monitor.c | 3 +--
2 files changed, 1 insertion(+), 4 deletions(-)
mains"
error message for affected platforms.
CC: Babu Moger
Signed-off-by: James Morse
Reviewed-by: Reinette Chatre
---
An alternative to this is for Intel non-linear MBA resources to
clear alloc_capable as they can't be configured anyway.
---
arch/x86/kernel/cpu/resctrl/core.c
intel_cacheinfo.c,
name it get_cpu_cacheinfo_id() to show its relation with
get_cpu_cacheinfo().
Now this is visible on other architectures, check the id attribute
has actually been set.
Signed-off-by: James Morse
Reviewed-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl/core.c | 17
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